Layout Minimization

8/6/2019 Layout Minimization

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CLIP: Integer-Programming-Based OptimalLayout Synthesis of 2D CMOS Cells

AVANEENDRA GUPTA

arcadiaOne, Inc.

and

JOHN P. HAYES

University of Michigan

A novel technique, CLIP, is presented for the automatic generation of optimal layouts of

CMOS cells in the two-dimensional (2D) style. CLIP is based on integer-linear programming

(ILP) and solves both the width and height minimization problems for 2D cells. Width

minimization is formulated in a precise form that combines all factors influencing the 2D cell

widthtransistor placement, diffusion sharing, and vertical interrow connectionsin a com-

mon problem space; this space is then searched in a systematic manner by the branch-and-

bound algorithms used by ILP solvers. For height minimization, cell height is modeled

accurately in terms of the horizontal wire routing density, and a minimum-height layout is

found from among all layouts of minimum width. For exact width minimization alone, CLIPs

run times are in seconds for large circuits with 30 or more transistors. For both height and

width optimization, CLIP is practical for circuits with up to 20 transistors. To extend CLIP to

larger circuits, hierarchical methods are necessary. Since CLIP is optimum under the

modeling assumptions, its layouts are significantly better than those generated by other,

heuristic, layout tools.Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design AidsLayout; D.3.2

[Programming Languages]: Language ClassificationsSpecialized application languages

General Terms: Algorithms, Design, Theory

Additional Key Words and Phrases: Circuit clustering, CMOS networks, diffusion sharing,

integer linear programming, integer programming, layout optimization, leaf cell synthesis,

module generation, transistor chains, two-dimensional layout

This research project was sponsored by a grant from Intel Corporation. Authors addresses: A. Gupta, arcadiaOne, Inc., 457 E. Evelyn Ave., Sunnyvale, CA 94086 ;email: [email protected]; J. P. Hayes, Dept. of EECS, University of Michigan, Ann Arbor, MI 48109-2122; email: [email protected] to make digital/hard copy of part or all of this work for personal or classroom useis granted without fee provided that the copies are not made or distributed for profit orcommercial advantage, the copyright notice, the title of the publication, and its date appear,and notice is given that copying is by permission of the ACM, Inc. To copy otherwise, to

republish, to post on servers, or to redistribute to lists, requires prior specific permissionand/or a fee. 2000 ACM 1084-4309/00/07000510 $5.00

ACM Transactions on Design Automation of Electronic Systems, Vol. 5, No. 3, July 2000, Pages 510547.


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1. INTRODUCTION

The layout of an IC affects not only its area but also its performance, yield,and reliability, which, in turn, determine its manufacturing cost. Table Ishows the effect of increase in chip area on the costs of the Intel Pentiummicroprocessor; these figures are taken verbatim from those previously

published in Murray and Hayes [1996]. Just a 1% increase in the Pentiumdie size increases the annual manufacturing costs by $63.5 million; a 15%size increase costs $961 million more. Intense competition among ICmanufacturers has resulted in the conflicting objectives of high designquality and short turnaround time. To meet these objectives, semicustomcell-based designs are now popular in high-volume microprocessors. The ICis partitioned into fairly small, similar units called cells. Each cell ispredesigned, laid out in a fixed layout style, and stored in a cell library.The overall layout methodology then has to efficiently place the cells andinterconnect them to minimize the final area. This cell-based approach

enables designers to concentrate on optimizing relatively small circuits.Since a cell is often instantiated many times in the same design, thetime-consuming effort of optimizing individual cells is well rewarded.

However, cell-based approaches have several disadvantages. Present-daymicroprocessors are typically partitioned into several hundreds of differentcell types. Moreover, each cell may require minor circuit or layout modifi-cations that tailor it to the requirements specific to its placement. This canlead to many different layouts for the same basic cell. In addition, each celllibrary is dependent on a fixed IC process technology. When a designmigrates from one technology to another, cell layouts either have to be

redesigned from scratch or existing layouts must be redone to conform tonew design rules. As a result, cell libraries tend to be extremely large, withthousands of cells whose layouts must be made as efficient as possible.Hence, increasingly, cell synthesis techniques that automatically converttransistor-level circuits into physical layouts are needed. Such techniquesmust produce cell layouts that closely match hand-crafted cells in terms ofarea and speed.

Like most problems in physical design, cell synthesis falls in the categoryof constrained optimization problems, where the goal is to find a solutionthat optimizes a given cost function under a set of constraints. The costfunction can be the cell area, its performance, the length of critical nets, ora combination of these. The constraints can be limits on cell width orheight, the number of diffusion rows, the aspect ratio of the cell boundary,

Table I. Estimated Effect of Die-Size Increases on Pentium Manufacturing Costs [Murrayand Hayes 1996]

Nominal Pentium die 1% die-size increase 15% die-size increase

Die size 160.2 mm2 161.8 mm2 184.2 mm2Die cost 100% 101.5% 122% Annual added cost $63.5M $961MChips fabricated/week 498.1K 97% 67.8%

CLIP: Integer-Programming-Based Optimal Layout Synthesis 511

ACM Transactions on Design Automation of Electronic Systems, Vol. 5, No. 3, July 2000.


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or the maximum allowable size of PMOS and NMOS transistors in thelayout. Since cell layout optimization is NP-hard [Chakravarty et al. 1991],any exact algorithm will, in the worst case, take an exponential amount oftime to run. Therefore, most proposed techniques have avoided optimalalgorithms in favor of fast but inexact heuristic methods. However, Maziaszand Hayes [1992] have shown that for one-dimensional cell layout, exactalgorithms are computationally feasible and can generate significantlybetter solutions than heuristic approaches.

This paper addresses cell synthesis in the more general two-dimensional(2D) style, and shows that exact algorithms are viable for this problemdomain as well. Specifically, we present an algorithmic technique calledCLIP (Cell Layout via Integer Programming) that generates 2D layouts ofoptimal width and height for a wide range of CMOS cells. CLIP is based oninteger linear programming (ILP); the layout problem is modeled as a set oflinear constraints while the optimization objective is formulated as a linearcost function. An off-the-shelf ILP solver program then finds a solution thatoptimizes the cost function while satisfying all constraints. Figure 1 showsan overview of the CLIP approach. While ILP has sometimes been per-ceived as having excessive computational requirements, we show that it ispractical for the 2D cell layout problem. Recent research has also success-fully applied ILP to several other practical CAD problem [Chowdhary andHayes 1995; Kim and Kang 1995; Maulik 1995]

CLIP proceeds in two stages: First, an ILP model that aims at maximiz-ing diffusion sharing among transistors and minimizing vertical inter-rowconnections determines a 2D placement of minimum width Wcell. Then, asecond ILP model generates a 2D layout that has width Wcell and minimizesthe cell height, measured in terms of the total number of horizontal routingtracks required. The final solution specifies the exact location and orienta-tion of each transistor in the 2D plane, as well as the diffusion sharingamong them. For width minimization alone, CLIP is shown to be practicalfor circuits with over 30 transistors. For both height and width minimiza-tion, CLIP is viable for circuits with up to 20 transistors.

Circuit netlist Form P/N pairs

ParameterizedILP model ILP solver No. of P/N rows

Optimum ILP solution

Map to 2-D layout

Data flow

Algorithm flow

Fig. 1. Overview of the ILP-based CLIP technique for cell layout optimization.

512 A. Gupta and J. P. Hayes



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The ILP-based approach of CLIP has several advantages over existingmethods:

(1) Within the modeling assumptions, it guarantees minimal 2D cell width

and has optimal 1D placement as a special case.(2) By modifying the cost function and adding constraints, the basic model

can easily accommodate new design objectives such as cell heightminimization and transistor folding.

(3) It is applicable to the entire class of dual CMOS networks, includingnonseries-parallel networks, and can be extended to dynamic CMOScircuits as well.

(4) It allows easy incorporation of hierarchical methods [Gupta, and Hayes1997; Gupta 1997], which have been shown to extend CLIP to large

circuits with over 50 transistors while yielding near-optimal layouts.

We begin by introducing the 1D and 2D layout styles in Section 2. The 2Dcell width minimization problem in discussed in Section 3, and an ILPmodel CLIP-W for it is presented in Section 4. Section 5 introduces the 2Dheight minimization problem and derives a cell-height model based on thehorizontal track density. The resulting width and height minimizationmodel CLIP-WH is outlined in Section 6. Section 7 presents experimentalresults obtained using CLIP-WH, and compares them with those obtainedusing a commercial heuristic-based layout tool.

2. CELL LAYOUT STYLES

CMOS cell layouts fall into two major categories: one-dimensional or linear,and two-dimensional or multirow. The widely used one-dimensional (1D)style [Barth 1995; Chen and Chow 1989; Hsieh et al. 1991; Maziasz andHayes 1992; Uehara and VanCleemput 1981] is illustrated in Figure 2(b)for the majority circuit of Figure 2(a). It consists of two parallel diffusionislands, called a P/N row, for the PMOS and NMOS transistors, respec-tively. In contrast, the two-dimensional (2D) style [Gupta and Hayes 1997];Maziasz and Hayes 1992; IBM Corp. 1992], which is a generalization of the

1D style, allows transistors to be placed in multiple parallel P/N rows.Figure 2(c) shows the 2D style for a placement in two P/N rows of themajority circuit.

The linear arrangement of transistors in the 1D style allows only limitedcontrol over the cell dimensions. Moreover, long wires may be required toconnect terminals of transistors placed towards the opposite ends of thesingle P/N row, thus adversely affecting a 1D cells performance. Since the2D style places transistors in multiple P/N rows, it offers control over thecells shape and aspect ratio, and so is better suited to the generation oflayouts with constraints on the cell dimensions and performance. Moreover,by adding another (vertical) dimension to transistor placement, 2D layouthas the potential of reducing interconnect complexity, since transistorsthat are strongly connected can be placed in adjacent rows to reduce wire




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lengths. 2D layouts are also necessary in certain applications. For example,most datapath designs consist of 2D arrays of cells. While the width of each

cell row is variable, the width of each cell columnthe datapaths pitchisoften predetermined. Large cells require multiple P/N rows so that theirrow-width does not exceed their pitch.

Fig. 2. (a) A majority circuit and its (b) one- and (c) two-dimensional layouts.




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The first general technique for 1D cell width minimization of dualseries-parallel static CMOS cells was proposed by Uehara and VanCleem-put [1981] Since then, considerable work has been done on 1D cell synthe-sis: [Chen and Chow 1989; Gupta 1996; Hill 1985; Hsieh et al. 1991;

Maziasz and Hayes 1992; Ong 1989; Poirier 1989; and Wimer 1987]. Exacttechniques for layout optimization of series-parallel circuits were proposedby Maziasz and Hayes [1992] and proven to yield optimal layouts inpractical time. However, for nonseries-parallel circuits, width minimizationhas been optimally solved for planar circuits [Maziasz and Hayes 1992] andonly heuristically for nonplanar ones [Carlson 1996]. Techniques thathandle arbitrarily-structured networks [Chen and Chow 1989; Hill 1985;Hsieh et al. 1991; Ong 1989; Wimer 1987] or address practical issues suchas transistor folding [Basaran and Rutenbar 1996; Gupta 1996; Hsieh et al.1991; Malavasi and Pandini 1995] also involve heuristics at some stage of

the synthesis process.Even in the constrained 1D style, few existing techniques efficiently solve

the problem of both width and height minimization [Baltus and Allen 1988;Basaran and Rutenbar 1996; Chen and Chow 1989; Gupta 1996; Ong 1989;Poirier 1989]. Many of these techniques, such as SOLO [Baltus and Allen1988] and GENAC [Ong 1989], rely on heuristics that perform a limitedsearch of the possible transistor placements and their orientations. Otherssuch as LiB [Hsieh et al. 1991] consider height reduction after transistorplacement has been determined. XPRESS [Gupta 1996] optimizes cellwidth but computes cell height heuristically based on the total wire length.

Only the technique of Maziasz and Hayes [1992] tries to explore the entirerange of possible placements and diffusion sharing, to generate a layoutthat is truly optimal in width and height.

In contrast to the 1D style, 2D layout generation has not been studiedvery much, and the few techniques proposed are ad hoc [Baltus and Allen1988; Poirier 1989; Tani et al. 1991; Zhang and Asada 1993]. For example,Poirier [1989] proposed a greedy transistor placement method that handlesconstraints on the number of diffusion rows or the shape of the cellboundary. SOLOs min-cut partitioning heuristic [Baltus and Allen 1988]can generate layouts to conform to a specified aspect ratio, that is, the ratioof the cells width to its height. Zhang and Asada [1993] also allude to anextension of their heuristic area minimization method that produces lay-outs with a specified aspect ratio. A few layout tools, such as Virtuoso[Cadence Design Systems, Inc. 199294], perform 2D cell synthesis but useheuristics that, while capable of handling cells with hundreds of transis-tors, yield nonoptimal layouts even for small cells; such layouts areinadequate for high-performance microprocessor designs that demand thebest possible layout area and performance. As the results in Section 7demonstrate, our technique, which targets cell layout optimization ofpractical but relatively small cells such as the datapath cells used inmicroprocessors, yields layouts whose widths and heights are up to 15%and 25% smaller, respectively, than Virtuoso layouts.




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3. 2D WIDTH MINIMIZATION

Table II summarizes the assumptions underlying the 2D style of Figure2(c) and the associated width minimization problem. Two adjacent transis-tors that have their diffusion terminals on the same net are connected by

diffusion sharing; otherwise they have a diffusion gap between them. Alinear sequence of transistors in which all pairs of adjacent transistorsshare their diffusion terminals is called a transistor chain. Complementary(or dual) P and N transistors are paired to form P/N pairs. The transistorsof a P/N pair are placed with their gate terminals vertically aligned. Hence,two P/N pairs can be connected (abutted) only when both the P and the Ntransistors of the two pairs can share their adjacent diffusion terminals;this is referred to as pairwise diffusion sharing. Moreover, a chain of Ptransistors exists if and only if the corresponding dual N transistors alsoform a chain; such matching chains are called dual chains, or in graph-theoretical terms, dual trails [Maziasz and Hayes 1992]. Henceforth, werefer to a dual chain simply as a chain. A chain is represented by thesequence of gate inputs of its constituent P/N pairs. Therefore, the twochains placed in the bottom and top P/N rows of Figure 2(c) are babc andacc, respectively. The number of P/N pairs in a chain is called its length. Achain cover or a trail cover of a circuit is a set of chains that includes everypair exactly once. A cover with a minimum number of chains is called amin-cover.

Although the CLIP technique presented here is based on P/N pairs(assumption 1), it is easily applicable to nondual CMOS circuits withunequal numbers of P and N devices. For such circuits, after P/N pairshave been formed, the remaining P (or N) devices form pairs in which onlyone device P or N exists. In addition, in subsequent work, the authors

Table II. Assumptions Underlying the 2D Cell Width-Minimization Problem

1. The circuit to be laid out is a dual CMOS circuit of fixed structure (no transistorreordering is allowed).

2. P and N transistors belonging to a pair are vertically aligned so that their terminals that

are on common nets can be connected using vertical wires without requiring a horizontaljog.

3. Alternate P/N rows are flipped to allow the power rails to be shared among adjacent P/Nrows.

4. Intracell routing is restricted to polysilicon and the first layer of metal (metal1), each ofwhich can be used in either direction (vertical or horizontal).

5. When a net spans multiple P/N rows, connections are made to join terminals that are onthe transistors placed closest together. For example, if rows 1, 3, and 6 have terminals ona common net, then the terminals on rows 1 and 3 and on rows 3 and 6 are connected.

6. Two terminals that are on transistors placed in adjacent diffusion rows are connectedusing routes in the channel between the rows. Hence, such connections do not affect thewidth of the cell.

7. Diffusion gaps do not allow a metal1 wire to be routed between them. Also, no wires arerouted over transistor diffusions assuming that they are strapped with diffusion-to-metalcontacts. Hence, all routes that span several P/N rows are routed along the sides of thecell and contribute to the widths of the rows that they pass through.




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have also extended CLIP to handle transistors of unequal sizes by incorpo-rating transistor splitting or folding [Gupta and Hayes 1998].

Alternate P/N rows are flipped (assumption 3) so that the P (N) diffusionislands of each adjacent pair of P/N rows face each other. This allows

adjacent rows to share a common power (ground) wire. The power andground buses, denoted PWR and GND, respectively, are routed in thesecond metal layer (metal2). Transistor terminals that are on PWR or GNDnodes are directly connected to these buses (although this assumption canbe easily removed in our technique). All other interconnections in the cellare restricted to the first metal layer (metal1) and polysilicon only (as-sumption 4). Due to the high resistance of polysilicon, its usage is mini-mized. Further, diffusion usage is limited to connecting adjacent transistorterminals that are on the same net.

For purposes of modeling the cell dimensions, assumptions 5, 6, and 7 in

Table II define the routing within the cell. If a net appears on severaltransistor terminals placed in different diffusion islands, then it is routedsuch that terminals that are placed in the closest rows are connectedtogether using wire segments (assumption 5). Further, if two terminals of anet appear in adjacent diffusion rows, they are connected using wires in thechannel between the rows (assumption 6). Both assumptions 5 and 6 alsohelp in reducing the total wire length. Finally, we assume that diffusiongaps do not allow metal1 wires to be routed through them (assumption 7).If the process technology is such that a gap is wide enough to allow a

vertical metal1 wire, the cost function for cell width (defined later) can be

appropriately modified. Further, we assume that all transistor diffusionsare strapped with diffusion-to-metal contacts, thus preventing any verticalmetal1 wires from being routed over them. This is true in most CMOStechnologies. Hence, each wire that connects terminals of transistors placedin different P/N rows, called an interrow connection, must be routed

vertically along the left or right side of the cell, and contributes to thewidth of the rows along which it is routed. If the technology provides asecond layer of metal for routing at the transistor-level, the cost functionsfor cell width and height can be easily modified to more accurately reflectthe true width and height.

Cost function. IfWcell is the overall width of the cell and Wr is the widthof the r-th P/N row, then the general 2D cell-width minimization problem

can be stated in the following way: Minimize Wcell by placing the P/N pairs

in a specified number numRows of diffusion rows such that the maximum

width among all rows is minimized, that is, minimize Wcell, where

Wcell maxWr : for each P/N row r where r 1, 2, . . . , numRows (3.1)

This objective can also be represented in the form of a minmax functionas follows:

minimizemaxWr : for each P/N row r where r 1, 2, . . . , numRows (3.2)




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In a linear arrangement of k chains C1, C2, . . . , Ck, k 1 gaps areneeded since each chain is assumed to be maximal, that is, no two adjacent

chains C i and C i1 can be merged to form a longer chain. A set of dualchains that includes each pair exactly once is called a chain cover or a dual

trail cover. Hence, in the special case of a 1D layout (numRows 1), thecell width depends on two factors: the number of transistor pairs p in the

circuit and the number of diffusion gaps c 1, where c is number of chainsin the cover. Assuming a virtual grid in which each transistor and diffusion

gap has unit width, Wcell for a 1D layout is defined by the followingequation [Maziasz and Hayes 1992]:

Wcell number of transistor pairs number of chains 1 p c 1 (3.3)

As we will see later, the width Wr of row r in the 2D layout style can be

expressed as Wr pr cr 1 v r, where vr accounts for the interrowconnections.

Width-influencing factors. We now analyze the three major factorschain cover, interrow wires, and diffusion type (P or N) placed at the cellbottomthat influence the 2D cell width.

(1) Chain cover: The effects of interrow wires will be temporarily ignored to

simplify this discussion. We use a CMOS circuit T with 14 P/N pairs,

whose N subcircuit T and dual two-terminal series-parallel multigraph

(TTSPM) representations G and Gd are shown in Figure 3, to illustrate

the influence of diffusion sharing and trail cover selection on 2D cellwidth. Applying the TrailTrace algorithm [Maziasz and Hayes 1992] to

T yields the trail cover TC1 C1 abgh, C2 cd, C3 iklj, C4 efmn. For a 1D layout, TC1 is a min-cover with four chains, C1, C2,

C3, and C4, of lengths 4, 2, 4, and 4, respectively. Hence, TC1 yields a1D cell with a minimum width of 14 4 -1 17 units.

A possible two-row placement using TC1 places the chain sets C1, C2

and C3, C4 in the two rows so that W1 4 2 1 7, W2 4

4 1 9 and Wcell 9. Instead, if one of the chains of length four,

say C3, is split into two subchains, C3, 1 and C3, 2, of lengths three andone, respectively, a two-row placement with chains C1, C2, C3, 2 andC3, 1, C4 still yields Wcell max4 2 1 2, 3 4 1 9.It can be verified that even if chains are split into subchains, the best

two-row placement using TC1 has a width of nine. Consider a different

min-cover for T, namely, TC2 C1 abgh, C2 dce, C3 iklj,

C4 fmn. A two-row placement consisting of chains C1, C2 andC3, C4 in the two rows has Wcell max4 3 1, 4 3 1 8.Hence, different min-covers for the same circuit can yield different 2Dcell widths.

The four chains of the cover TC1 can be placed in the three P/N rows, r1,r2, and r3 in two ways: (1) with r1 C1, C2, r2 C3 and r3 C4,




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we have Wcell 7; (2) if chain C2 is split into two unit-length chains,

C2, 1 and C2, 2 the placement r1 C1, C2, 1, r2 C3, C2, 2, and r3 C4 results in Wcell 6. Therefore, the chains in the min-cover of a1D layout cannot be considered to be indivisible for a 2D placement.While splitting one or more chains in a min-cover effectively increasesthe number of chains (and the number of diffusion gaps), it can reducethe cell width. By the same argument, a 1D min-cover that guaranteesan optimal-width 1D placement, does not necessarily provide a mini-mum-width 2D placement.

(2) Interrow connections: Under assumption 7 (Table II) for 2D layout, eachinterrow wire that connects terminals of transistors placed in differentP/N rows must be routed vertically along the left or right sides of the

cell. Hence, each interrow connection contributes to the width of thediffusion row along which it is vertically routed, and must be consid-ered during 2D layout.

The circuit of Figure 4(a), which has a 1D min-cover of size two,illustrates the effect of transistor placement on interrow connections

and Wcell. Figure 4(b) is a two-row placement of the min-cover C1

hgedba, cifjk. It requires three interrow wires (nets 1, 2, and GND)that run vertically across both rows. The widths of the top and bottom

rows are W1 6 1 1 3 9 and W2 5 1 1 3 8,

respectively; hence, Wcell maxW1, W2 9. Another two-row place-

ment for this circuit using a suboptimal 1D cover C2 baced, ghkj,if is shown in Figure 4(c). This layout requires only one vertical

connection (net 2) and has Wcell max5 0 1, 6 1 1 8.

(3) Bottom diffusion row type: Figure 4(d) is the layout for the circuit ofFigure 4(a) using the cover C1 but with the P diffusion row placed atthe cell bottom. Unlike the layout of Figure 4(b), this layout requiresonly two vertical wires (connecting nets 6 and 9) for interrow connec-tions and has a smaller cell width of eight. Therefore, the placement ofthe P or the N diffusion island at the bottom of the cell affects the

number of interrow connections, and hence the 2D cell width.In summary, the width Wr of each P/N row r in the 2D style depends on

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(a) NMOS sub-circuit T (b) TTSP graph G (c) Dual TTSPM Gd

Fig. 3. A dual TTSP circuits N subcircuit and its graph representations.




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three factors: the number pr of P/N pairs in the row; the number cr 1 of

diffusion gaps where cr is the number of chains in row r; and the number vrof vertical wires that need to be routed along the row. Thus,

Wr pr cr 1 vr (3.4)

The next section presents an ILP model CLIP-W (where the W indicatesthat the model minimizes the cell width only) that generates optimalsolutions to the minimum-width 2D cell layout problem under the assump-tions defined in Table II.

4. WIDTH MINIMIZATION MODEL

Given a set of P/N pairs and the number of P/N rows, the following layout

characteristics must be determined in order to minimize Wcell as defined byEq. (3.1): the row, location, and orientation of each pair, the diffusionsharing among adjacent pairs, the vertical nets that connect transistorterminals across different P/N rows, and the diffusion row type, P or N, tobe placed at the bottom of the cell. The CLIP-W model converts the width

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Fig. 4. (a) Dual TTSPMs for the curcuit z a b c d.e i f j.k g.h,and b d its two-row layouts using different chain covers.




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minimization objective to a linear cost function, and models the 2D celllayout requirements as linear inequalities.

Inputs and outputs. Table III lists the input and derived parametersfor CLIP-W. To represent the position of each pair in the 2D plane, we

introduce place-holders called slots in each row in which P/N pairs areplaced. For a circuit with numPairs pairs, a 1D placement requires

numPairs slots. A 2D placement in numRows 1 requires at least

maxSlots numPairsnumRows slots in each row. Slots are numberedin increasing order from the left. Figure 5 illustrates row and slot numbering. We

also define the following sets of integers: slots 1, 2, . . . , maxSlots ,

rows 1, 2, . . . , numRows, and orients 1, 2, 3, 4, the four pos-sible orientations for each P/N pair.

The boolean array share represents the possibility of diffusion sharing

between two P/N pairs. The element sharep i, o i, pj, oj is set to 1 if pairsp i and pj can be placed adjacent to each other in orientations o i and oj,respectively, with diffusion abuttment. Since each pair has four possible

orientations, two pairs p i and pj, placed with pj to the immediate right of

p i, can be abutted in sixteen ways. Therefore, sharep i, o i, pj, oj is givenby the following logic equation:

sharep1, oi, pj, oj 1 iffoi 1 and oj 1 and Pdrnpi Psrcpj and Ndrnpi Nsrcpjor oi 1 and oj 1 and Pdrnpi Psrcpj and Ndrnpi Ndrnpj

or. . .or oi 4 and oj 4 and Psrcpi Pdrnpj and Nsrcpi Ndrnpj (4.1)

Table III. Input (14) and Derived (57) Parameters for the CLIP-W Model

Parameters Interpretation

1. numPairs, numRows ,

maxSlots

The number of pairs, P/N diffusion rows, and slots,

respectively2. pairs, rows, slots , nets The set of pairs, rows, slots, and nets, respectively3. PpairNets , NpairNets PpairNetsp {gate, source, and drain nets of the P

transistor of pair p}(NpairNets is similarly defined for the N transistors)

4. nDiffAtBottomOfCell A decision variable that is 1 (0) if N diffusion is placedat bottom (top)

5. Psrcpairs , nets,Pgate pairs , nets,Pdrnpairs, nets

Psrcp, n 1 if pair p has net n on the sourcediffusion if its P transistor(Pgatep, n and Pdrnp, n are similarly defined forgate/drain terminals)

6. Nsrcpairs , nets,Ngatepairs , nets,Ndrnpairs , nets

Nsrcp, n 1 if pair p has net n on the sourcediffusion of its N transistor(Ngatep, n and Ndrnp, n are similarly defined forgate/drain terminals)

7. sharepairs , orients ,pairs, orients

sharep i, o i, pj, oj 1 if pair p i in orient o i can sharediffusion with pair pj in orient oj, and 0 otherwise




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The basic decision variables for each pair are represented by binary

arrays Xpair, slots, rows and Xorpairs, orients. While Xp, s, y im-

plies that the pair p is placed in s slot of row r, Xorp, 0 1 states thatp is placed in orientation o. To model diffusion sharing, we introduce a

binary array nogapmaxSlots1, rows, where nogapss, r 1 if the

adjacent slots s and s 1 in the P/N row r do not have a gap between

them, that is, if the pairs that are placed in slots s and s 1 of row r can

share their adjacent diffusions. The nogap variables are illustrated inFigure 5.

The 2D cell width minimization objective is given by Eq. (3.1), where the

width Wr of each row r can now be expressed as follows:

Wr #pairs in row r #gaps in row r #vertical wires

#pairs in row r #pairs in row r 1 #abutments

vr

2 Xrowp, r nogapss, r vr 1 (4.2)

Constraints. We now describe the constraints that enforce a validlayout.

(1) Pair inclusion: Each pair must be placed in exactly one slot and in oneorientation.

sslots

rrows

Xp, s, r 1 @p pairs (4.3)

oorients

Xop, o 1 @p pairs (4.4)

Rows

1

r

numRows

1 2 maxSlotsSlots

nogap[1, 1] nogap[maxSlots1, 1]

nogap[1, r] nogap[maxSlots1, r]

nogap[s, 1]

nogap[s, r]

s s+ 1

Fig. 5. Illustration of rows, slots, and diffusion gaps in a 2D cell layout.




14/38

(2) Slot occupancy: Since each P/N row must have at least one pair in it, weforce the first slot in each row to be filled with exactly one pair.Further, we force slots be filled in left-justified order, that is, a slot s

should be occupied before slot s 1 to its right. These constraints do

not eliminate any optimal placements and are introduced only for ILPmodeling purposes, to reduce the number of placements that must beexplored and, in turn, the run time.

ppairs

rrows

Xp, 1, r 1 @r rows (4.5)

ppairs

Xp, s 1, r 1 @p rows, s slots (4.6)

(3) Diffusion sharing: The variable nogaps, r can be defined by thefollowing logic equation:

nogaps, r for every pair pi and pj of pairs that can potentially share diffusionfor each orientation oj of pi and oj of pj for which sharepi, oi, pj, oj 1

or pi is placed in slot s in row r and pj is placed in orientation oiand pj is placed in slot s 1 in row r and pj is placed in orientation oj) or Xpi, s, r and or Xpj, s 1, r and mergedpi, pj :

@pj pairs : @pi pairs (4.7)

Here mergedp ipj 1 if pairs p i and pj are in orientations such that p ican share diffusion with pj placed to its immediate right.

mergedpi, pj or Xorpi, oi and Xorpj, oj : @oioj orients such that sharepi, oi, pj, oj Xorpi, 1 and or Xorpj, oj : @oj orients such that sharepi, oi, pj, ojor Xorpi, 2 and or Xorpj, oj : @oj orients such that sharepi, 2, pj, ojor Xorpi, 3 and or Xorpj, oj : @oj orients such that sharepi, 3, pj, ojor Xorpi, 4 and or Xorpj, oj : @oj orients such that sharepi, 4, pj, oj (4.8)

Finally, we must ensure that a pair can share diffusions with at most onepair placed to its immediate left or right sides. This is modeled by thefollowing two constraint sets:

pjpairs

mergedp1, pj 1 @pi pairs (4.9)

pipairs

mergedp1, pj 1 @pj pairs (4.10)

(4) Linearizing the cost function: To linearize the nonlinear cost function

(3.2), we replace it by a linear expression minimize Wcell, and introduce

a set of linear inequalities Wcell Wr for each P/N row r that convert

the max function into linear form. Here, Wr is given by Eq. (4.2).

(5) Interrow connectivity: As explained in Section 3, the contribution ofinterrow connections to the width of a row r is measured by the number




15/38

of vertical wires that must be routed adjacent to row r. This, in turn,depends on the number of nets that connect terminals of transistors

placed in rows below r to those placed in rows above r. For example, net

out in Figure 4(d) appears in row m 2 above row r 1, as well as in

the N diffusion of row r itself; hence, it requires a vertical wire adjacent

to row r if and only if the N diffusion appears at the bottom of row r,

away from row m. In contrast, Figure 4(b), in which the P and N

diffusions are interchanged, has net out in the top (P) diffusion of row r.Since out can be routed in the channel between the rows, it does notneed an extra column.

We introduce a two-dimensional array of binary variables verticalNetIn-

Row, where verticalNetInRowr, n is 1 if and only if net n must be

routed vertically along row r, and is 0 otherwise. To represent

verticalNetInRow, we introduce four simpler auxiliary variables:

netAboveRowr, n : nets on terminals of transistors placed in rows

above row r;

netBelowRowr, n : nets on terminals of transistors placed in rows

below row r;

topRowNetr, n : nets on terminals of transistors placed in the top

diffusion island of row r;

bottomRowNetr, n : nets on terminals of transistors placed in thebottom diffusion of row r.

We also use the shorthand notation V verticalNetInRowr, n, X

netAboveRowr, n, Y netBelowRowr, n, and B bottomRowNetr, n.

Figure 6(a) illustrates how the above four variables X, Y, T, and B are

computed for a given net n in row r of a 2D layout. The binary variable

verticalNetInRowr, n is a function of these four variables, which arealso all binary. Hence, as shown in the truth table of Figure 6(b), the values

of verticalNetInRowr, n can be determined by enumerating all sixteenassignments of 0-1 values to the four variables. This leads to the followingreduced sum-of-products expression for V.

V X and Y and not Tor X and B and not Tor Y and not B and T (4.11)

For the example in Figure 4(d), netAboveRow1, out 1,

netBelowRow1, out 0, topRowNet1, out 0, bottomRowNet1, out

1. Thus, according to Eq. (4.11), verticalNetInRow1, out 1.

The variable netAboveRowr, n, defined below, determines whether anet n is present in rows above a given row r if n is present in any row y




16/38

that is placed above r. The variable netBelowRowr, n is similarly

defined for all rows y below row r.

netAboveRowr, n or topRowNety, n or bottomRowNety, n :

@ rows y rows r (4.12)

netBelowRowr, n or topRowNety, n or bottomRowNety, n :@ rows y rows r (4.13)

Finally, the variable topRowNetr, n determines the presence of a net

n in the top diffusion island of a row r by its presence in the top diffusion

island of any chain placed in that row. The variable bottomRowNet r, n issimilarly defined for the bottom diffusion island.

topRowNetr, n or topChainNetsc, r, n Xc, r :@c chains (4.14)

bottomRowNetr, n or bottomChainNetsc, r, n Xc, r :@c chains (4.15)

Linearization. Several sets of constraints in the CLIP-W model arenonlinear, and must be linearized for inclusion in an ILP model. Forexample, constraints (4.11-4.15) for interrow connectivity involve logicoperations such as and, or, and not, and hence are nonlinear. Table IVenumerates the types of logic equations that appear in our model alongwith the sets of equivalent linear inequalities on binary variables. Thistype of linearization is possible since all ILP variables are restricted to 0-1

values. It is exact in that it does not eliminate any feasible integersolutions, and hence preserves optimality. For example, consider the logical

constraint z x and not y, where x, y, and z are all binary variables. By

assigning all four combinations of 0-1 values to x and y, one can verify that

the pair of inequalities z x y 12 and z x y 12 ensure

that z always takes the 0-1 value required by the original logical con-

straint. In these linearizations, a variable x can be substituted for its

logical inverse not x by replacing x by 1 x in the linear inequalities.Constraint (4.11) can be linearized more efficiently by factoring it as

follows:

V v1 or v2 (4.16)

where v1 X and not T and Yor B and v2 Y and not B and T. Eq.

(4.16) can be linearized using Table IV. In addition, v1 and v2 can bedirectly linearized as follows:

v1 X 1 T Y B2 2

v2 Y 1 B T 2




17/38

Constraint (4.7) on nogapss, r can be expanded to a sum-of-products

expression in which each product term has the form (Xp i, s, r and

Xpj, s 1, r and mergedp i, pj). Then, (4.7) can be linearized by rep-

resenting each product by an intermediate 0-1 variable, and linearizing theboolean and and or operators as described in Table IV. However, since(4.7) has a large number of product terms, an efficient linearization should

introduce few intermediate variables. In fact, since at most one of Xp i,

s, r for any slot s in row r, and at most one of Xpj, s 1, r for its

adjacent slot s 1, can be 1 in any solution, (4.7) can be linearized without

introducing additional variables. Moreover, since nogapss, r appearsonly with a negative coefficient in the minimization objective (4.2), it is

sufficient to ensure nogaps, r 0 when necessary. Nogaps, r will beautomatically forced to 1, if possible, when the model is solved, becausethat further reduces the objective value.

Hence, Eq. (4.7) is equivalent to the set of linear inequalities below, one

for each pair of P/N pairs p i and pj that can share their diffusions.

3 nogaps, r Xpi, s, r Xpj, s 1, r mergedpi, pj

3 pkpairs, plpj

Xpk, s, r2 plpairs, plpj

Xpl, s 1, r (4.17)

In other words, for every pair of P/N pairs p i and pj, nogaps, r 1 if

Xp i, s, r Xpj, s 1, r mergedp i, pj 1; however, if p i is notplaced in slot s, then nogaps, r 1 depends on the pair pk p i placed

in slot s. Also, ifp i is placed in slot s but pj is not placed in slot s 1, thennogaps, r depends on the pair p l pj placed in slot s 1.

Constraint (4.8) for mergedp i, pj also contains a sum-of-products

expression with products of the form Xop i, o i and (Xorpj, oj1 or

Xorpj, oj2 or . . . ) for every pair p i and pj of P/N pairs, and for every

orientation oi of p i. Since mergedp i, pj appears as a positive term in

inequality (4.17) for nogaps, r (and hence as a negative term in the

minimization objective), it is again sufficient to ensure that mergedp i, pj isset to 0 when necessary. Hence, Eq. (4.8) is equivalent to the linearinequality

Table IV. Linearization of Logical Constraints

Logical constraint Set of equivalent linear constraints

z x1 or x2 or. . . or xn z x1 x 2 . . . xn

z

x1 x 2 . . . xn

nz x1 and x2 and. . . and xn z x1 x 2 . . . xnnz x y 12

z x and not y z x y 12z x y

z x and y and not w z x y w 13z x y w 1




18/38

2 mergedpi, pj Xorpi, oi ojorients, sharepi, oi, pj, oj

Xorpj, oj

2 ojorients, ok

Xorpi, ok.

Again, in words, for every orientation o i of p i, if Xorp i, o i 1, then

mergedp i, pj 1 if and only if pair pj is placed in some orientation in

which it can share diffusions with p i. However, if Xorp i, o i

0, thenmergedp i, pj is made independent of o i by the last term in the above

inequality.Figure 7 illustrates the diffusion sharing constraints in the CLIP-W

model for the case of a 2-to-1 multiplexer circuit consisting of seven P/Npairs. All possible pairwise diffusion abutments represented by the arrayshare are shown in Figure 7(b). Figure 7(c) lists the logical diffusion

sharing constraints for nogap1, 1 for a single row placement s r 1.Experimental results: The ILP models have been programmed in

AMPL (A Mathematical Programming Language) [Fourer et al. 1993], a

high-level language that allows the model to be described in a parameter-ized form, that is, independently of the input data used for a specificinstance of the model. Although we evaluated several general-purpose ILPsolvers, such as OSL [IBM Corp. 1992] and CPLEX [1990], the specialized0-1 solver OPBDP [Barth 1995] proved to be best suited to our optimizationproblem. All the above solvers are based on branch-and-bound enumera-tion. However, while OSL and CPLEX use linear programming to solve therelaxed linear program at each node in the branch-and-bound search tree,OPBDP (Optimizing with Pseudo-Boolean Davis-Putnam) uses booleansatisfiability. All CLIP run times presented here have been obtained withthe OPBDP solver.

Table V presents optimum-width layouts in 1 through 4 P/N rows for afew representative circuits from the literature. For three of the circuits,

P/N row1

P/N row

r+ 1P/N row

r

P/N rownumRows

topRowNet[r, n] (T)

bottomRowNet[r, n] (B)

netAboveRow[r, n] (X)

netBelowRow[r, n] (Y)

000

0000011111111

000

0111100001111

001

1001100110011

010

1010101010101

X Y T B V

000

0001001001110

(a) (b)

Fig. 6. (a) Illustration of the factors that determine interrow connections and (b) the truthtable for verticalNetInRow r, n.




19/38

Table VI tabulates the contributions of individual P/N rows to the cell

width Wcell in terms of the number of pairs, diffusion gaps, and verticalwires. It is evident from Table VI that, as the number of rows is increased,the average number of pairs and diffusion gaps in each row decreases. Thisdecrease is, however, offset by an increase in the number of interrow

y

s 2

4

1

3

b

a

5

p2

p3

p4

p5p6

p1

p76

share[pi, oi, pj, oj]

Pair pi Orient oi Pair pj Orient oj

p1

3332

4

p2p4p6p7

p7

2224

2

p2

333

p1p4p6

222

p3 13

p4p4

31

p4

323

p2p3p6

242

p5 13

p6p6

31

p6

33324

p1p2p4p5p5

22242

p7 31

p1p1

13

nogap[1, 1] = X[p1, 1, 1] and ( (X[p2, 2, 1] and merged[p1, p2]) or (X[p4, 2, 1] and merged[p1, p4])

or (X[p6, 2, 1] and merged[p1, p6]) or (X[p7, 2, 1] and merged[p1, p7]) )

or X[p2, 1, 1] and ( (X[p1, 2, 1] and merged[p2, p1]) or (X[p4, 2, 1] and merged[p2, p4])

or (X[p6, 2, 1] and merged[p2, p6]) )

or X[p3, 2, 1] and ( (X[p4, 2, 1] and merged[p3, p4]) )


or (X[p6, 2, 1] and merged[p4, p6]) )



or (X[p4, 2, 1] and merged[p6, p4]) or (X[p5, 2, 1] and merged[p6, p5]) )


merged[p1, p2] =

merged[p1, p4] =

merged[p1, p6] =

merged[p1, p7] =

merged[p2, p1] =

merged[p2, p4] =

merged[p2, p6] =

merged[p3, p4] =

merged[p4, p2] =

merged[p4, p3] =

merged[p4, p6] =

merged[p5, p6] =

merged[p6, p1] =

merged[p6, p2] =merged[p6, p4] =

merged[p6, p5] =

merged[p7, p1] =

Xor[p1, 3] and Xor[p2, 2]



Xor[p1, 2] and Xor[p7, 4] + Xor[p1, 4] and Xor[p7, 2]










Xor[p6, 3] and Xor[p2, 2]Xor[p6, 3] and Xor[p4, 2]



(a) (b)

(c)

Fig. 7. (a) A 2-to-1 multiplexer; (b) array sharep i, o i, pj, oj; and (c) constraints fornogap1, 1.




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Table V. CLIP Placements of Minimum Cell Width with Run Times of the OPBDP IntegerSolver

No. Circuit

No.of

trans

No.of

nets1

No. ofP/N

rows

2-D cell width Wcell

Runtime

(secs)2CLIP

Virtuoso[Cadence19921994]

1 2-input parity circuit (Xor)[Baltus and Allen 1988]

10 7 1 5 5 0.012 3 4 0.013 3 4 0.054 4 4 0.16

2 Non-series-parallel bridgecircuit [Zhang and Asada1993]

10 10 1 6 6 0.032 5 5 0.093 4 5 0.074 4 5 0.19

3 2-level implementation ofz

a e f d [Maziaszand Hayes 1992]

12 12 1 7 7 0.03

2 3 4 0.023 3 3 0.064 3 5 0.19

4 2-to-1 multiplexer 14 10 1 8 8 0.062 4 5 0.253 3 3 0.064 3 3 0.25

5 Series-parallel circuit for z a.b c c e f g.h [Uehara and VanCleemput 1981]

16 18 1 8 9 0.012 6 7 0.063 5 7 1.24 5 7 2.3

6 2-level implementation of the

majority function z a.b b.c a.c

18 12 1 10 10 0.2

2 5 6 0.23 4 5 124 4 6 8

7 Series-parallel circuit for z a.b.c d.e.f g h i j

20 22 1 11 11 0.22 7 7 123 5 7 24 5 7 15

8 Series-parallel circuit for z a.b.c.d e.f.g.h i j k l [Maziasz and Hayes1992]

24 24 1 13 14 0.32 9 10 113 5 6 104 5 6 390

9 8-input NAND circuit 24 20 1 14 15 19

2 7 8 93 5 6 434 4 4 58

10 Full adder [Baltus and Allen1988]

28 17 1 16 17 732 8 9 53 5 8 44 5 8 6,415

11 Series-parallel circuit for z a.b.c.d e.f.g.h i j k l m n o p

[Maziasz and Hayes 1992]

32 32 1 18 19 792 9 10 23 8 10 2,4464 6 9 5,216

1. Nets PWR and GND are ignored since they connect directly to the power and ground buses.

2. Run times for CLIP-W were obtained on the HP 9000/735 workstation using OPBDPversion 1.1 with the -h103 heuristic modified as described in Section 4.




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connections. As Figure 8 demonstrates, the cell width initially decreases

with an increase in the number of rows, but the rate of decrease diminishesrapidly due to an increase in the interrow connections. Moreover, as we willsee later, increasing the number of rows often increases cell height due toan increase in the number of routing tracks and the number of transistorsplaced along a vertical column. Thus, for most circuits with a few tens oftransistors, the cell area can decrease when the layout changes from one totwo, or at most three, rows; 2D layout in four or more rows is likely toincrease the area considerably.

Table V also presents run times obtained using CLIP-W with the OPBDP

solver. Since the Xrow variables decide the row in which a pair is placed,they are critical to getting a 2D placement. Therefore, to further improverun times, OPBDPs -h103 variable selection heuristic is modified to first

select an unassigned Xrowp, r variable. If all such variables are fixed,OPBDPs original -h103 heuristic is used. This modification enables thesolver to generate 2D placements early on in the enumeration process,thereby improving run times without losing any optimality. The run timesobtained with the modified heuristic proved to be up to two orders ofmagnitude less than the original CLIP-W. Run times are only a few secondsfor optimal 2D placement in one through four P/N rows for circuits with 30or more transistors. These times tend to increase with circuit size due tothe larger number of 0-1 variables and constraints in the ILP model. For

very large circuits, we have proposed circuit preprocessing and hierarchicalschemes [Gupta and Hayes 1997; Gupta 1997] that effectively reduce the

Table VI. Contribution of individual P/N rows to the optimal cell width Wcell

No. Circuit

No.

of

pairs

No.

of

nets

Wcell maxWr

Wr #pairs #diffusion gaps #vertical wires

No. of P/N rows

1 2 3 4 5

6 2-level implementationof the majority functionz a.b b.c a.c

9 14 10 5 4 4 4(910) (401) (211) (211) (310)

(500) (400) (301) (103)(310) (202) (103)

(210) (211)(211)

8 Series-parallel circuit forz a.b.c.d e.f.g.h i j.k l

[Maziasz and Hayes 1992]

12 26 13 9 5 5 5(121) (612) (401) (401) (400)

(612) (401) (401) (203)

(401) (203) (104)(202) (203)(301)

10 Full adder [Baltus andAllen 1988]

14 17 16 8 5 5 5(1420) (620) (500) (401) (103)

(800) (410) (401) (301)(500) (301) (401)

(311) (310)(310)




22/38

problem size, measured by the number of pairs and nets, and show thatthey yield near-optimal, and frequently even optimal, layouts with dra-matic improvements in run time.

The optimal cell widths obtained by CLIP are significantly smaller thanthose produced by Virtuoso [Cadence Design Systems, Inc. 199294], al-

though Virtuosos run times are much lessa few seconds in all cases. Itshould be reiterated, however, that Virtuoso is a general-purpose toolintended to quickly lay out very large cells; it is not designed to optimizethe layout of small cells of the type we are targeting.

In the remainder of the paper, we extend CLIP-W to an ILP modelCLIP-WH that minimizes the cell height in addition to its width.

5. HEIGHT MINIMIZATION

The overall width and height-minimization CLIP technique proceeds in twostages:

(1) Uses the CLIP-W model to find Wmi n, the minimum cell width, ignoringheight.

(2) Uses CLIP-WH to find a layout of minimum height from among all

layouts of width Wmi n.

Assuming uniform transistor sizes, the height of a cell is determined byits horizontal routing (track) density [Maulik 1995], that is, the number ofhorizontal tracks needed to connect electrically equivalent transistor termi-nals. For example, the 1D layout of Figure 2(b) requires three metal tracks,two in the P/N channel and one in the region above the P diffusion row, andtherefore has a height of three. Track density, in turn, depends on therouting methodology. Several factors, such as the layout style, the number

Fig. 8. Number of P/N diffusion rows vs. cell width.




23/38


24/38

inside the cell and, in turn, the number of horizontal tracks required. Weillustrate this using the two-row layout of Figure 9. Assumption 5 statesthat two terminals that are on opposite sides of a region R are connectedusing wires in region R. Any horizontal track required for such a connec-tion is therefore attributed to region R. For example, terminals 7, 10, and12 in the first P/N row of Figure 9 require a track in region C1. Similarly,the terminal in column 7 of the first row is connected to that in column 1 ofthe second row with a track in region R1,2. If two terminals are on thesame diffusion row of a routing region R, the wire that connects them canbe placed either in R or in the region adjoining R. We assign the trackrequired for such a connection to the P/N channel adjacent to the diffusionrow. This assumption is solely for purposes of modeling the track require-ment of each net, and does not affect the total cell height. This is illustratedby the track in the C1-region required to connect the two terminals incolumns 7 and 15 of the P diffusion of the first P/N row.

As stated by assumption 6, no jogs are allowed while connecting termi-nals that require a horizontal wire segment in a routing channel. Thisensures that if two terminals on the same net require a horizontal segment

in a channel, they are connected using exactly one track. All routes inFigure 9 illustrate this assumption. Finally, assumption 7 asserts that norouting track can be placed over the transistor diffusions; hence each trackcontributes to the cell height.

Computing cell height. In order to determine the track density in eachrouting region, a P/N row in the 2D layout is considered to be made of

vertical columns, each of which corresponds to a terminal of a transistor

placed in that row. Let maxCols be the number of vertical columns in the

cell layout. Then, the number of tracks TR required in a routing region Rdepends on the column that has the maximum number of tracks. The

number of tracks in each column c, in turn, depends on the nets that spanc. Here, the horizontal span of a net in a routing region R is defined by the

Fig. 9. Column representation and routing assumptions.




25/38

set of contiguous columns through which the net must be routed in order to

connect all its terminals that are in region R. Hence, TR can be expressedby the following maximization function:

TR maxnumber of nets that span column c of region R :c 1, 2, . . . , maxCols (5.1)

Assuming equal transistor sizes, cell height Hcell is the sum of all routingtracks required, that is,

Hcell Rregions

, number of tracks required in routing region R Rregions

TR (5.2)

The horizontal span of a net depends on the exact position and orienta-tion of each transistor in the 2D plane. Hence, 2D cell height minimization

translates to finding an assignment of P/N pairs to rows, the individualorientation of each pair, and a linear ordering of pairs in each row such

that the cell width is Wmi n and the number of routing tracks is minimized.We illustrate the above concepts using the two-row layout of Figure 9.

The bottom P/N row has two chains with three and two pairs, respectively,and hence has 15 columns. The top row has one chain with four pairsresulting in 12 columns. The track densities in this layout are as follows:

TC1 2, TR1, 2 1 and TC1 3. Thus, Hcell TC1 TR1, 2 TC2 2 1 3 6.

The total track density of the cell depends on the often complex track

requirements of each net. To simplify our ILP model, we make the followingreasonable assumptions about the routing within the cell:

P/N channel routing: If a net has multiple terminals appearing on the Pand/or N diffusion islands of the same P/N row, all its terminals are

connected by a track in the P/N channel. For example, net n3 in Figure 9has two terminals in the N diffusion and one in the P diffusion of the

first row. Since all three terminals are connected in region C1, net n3spans columns 6 through 13. Net n1, in contrast, has both its terminalsin the N diffusion of the second row. Its track, which spans columns 1

through 12, is assigned to region C2.

Interrow channel routing: If a net appears on both sides of an interrowchannel, only one terminal from each side needs to be connected to theother, since the other terminals have already been connected in the P/N

channel. For example, net n2 has one terminal on the top (column 1) andtwo terminals on the bottom (columns 6 and 15) diffusions of R1,2, onlyone of which (column 6) is connected to the terminal in the top diffusion.

The same is also true of n3.

Vertical interrow connections: As discussed earlier, vertical interrowconnections contribute to the cell width. Such connections contribute tothe cell height as well, as illustrated by net n4 in Figure 9, which




26/38

requires a horizontal track in the C2-region. The CLIP-W width minimi-zation model reduces the impact of these vertical interrow connectionsHence, we assume that vertical interrow connections can be ignored inthe determination of cell height.

Vertical net overlap: We ignore vertical overlaps of nets which, inpractice, can increase the number of routing tracks or the width of a

routing channel. For example, nets n2 and n3 in Figure 9 overlap in

region C1 because a vertical segment of n3 crosses a horizontal segment

of n2. This requires one of these segments to change layers to avoid adesign-rule violation. Such layer changes require contacts that canincrease the channel height.

Under the above assumptions, we now need to compute the track densi-

ties of each P/N and interrow channel. We begin by addressing the P/Nchannels. The number of tracks TR required in a P/N channel R depends onthe nets that occur in each vertical column which, in turn, depends on the

position and orientation of each transistor. Thus, to compute TR, we mustdetermine, for each column c in region R, the number of nets that must berouted horizontally through it. This has traditionally been referred to asthe channel routing problem [Rivest and Fiduccia 1991]. Since channelrouting predefines the position of each net-terminal, it is much simplerthan 2D cell layout where the terminal locations depend on the variablesslots and Xor, whose values are determined only at run time. Hence, the

routing model described here for cell layout can be applied to channel,over-the-cell [Her and Wong 1995], and related routing problems as well.

While channel routing algorithms must consider both horizontal and

vertical constraints to compute TR, cell synthesis techniques have generallyignored vertical constraints [Chen and Chow 1989; Hill 1985; Maziasz and

Hayes 1992]. The fundamental problem is to determine whether a net n

requires a track in a column c. Let the array net of 0-1 variables be such

that netn, c, r 1 if net n exists on a transistor terminal in column c.

We define the 0-1 array span such that spann, c, r 1 if n requires a

horizontal track in column c of row r. Thus, the total number of tracksrequired in column c is simply spann, c, r for all nets n. Then TR,

defined by Eq. (5.1), can be restated in terms of spann, c, r, as follows:

TR maxc1. . . maxCols

nnets

spann, c, r (5.3)We now enumerate the conditions under which a net n spans a column c,

that is, netn, c, r 1. As illustrated in Figure 10, there are three

possible ways for n to span c: (i) n is present on both sides ofc (net n1); (ii)

n is present on c and to its left (net n2); and (iii) n is present on c and to itsright (net n3). These conditions are formalized in the following theorem.




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THEOREM 1. Consider a 2D cell layout in r P/N rows. Define a 0-1 array

net in which netn, c, r is 1 if net n has a transistor terminal (gate,

source, or drain) in column c of the P/N-channel of row r , and is 0

otherwise. Similarly, define a 0-1 array span whose element spann, c, r

is 1 if net n spans (that is, requires a horizontal track in) column c of row r,

and is 0 otherwise. Then, the value of spann, c, r is given by the

following equation:

spann, c, r netn, c, r and or netn, c3, r : c3 c for c 1 majorityspann, c 1, r, netn, c, r, or netn, c3, r : c3 c for c 1 (5.4)

PROOF. If netn, c, r 0, then n spans c only if it is present both to

the left and right of column c. However, if netn, c, r 1, then n spans c

if it is present on at least one other column besides c. Thus, spann, c, runder the following two mutually exclusive conditions:

netn, c, r 0 and netn, c2, r 1 for some c2 c and netn, c3,

r 1 for some c3 c netn, c, r 1 and netn, c2, r 1 for some c2 c or netn, c3,

r 1 for some c3 c

If x netn, c, r, y or netn, c2, r : c2 c and z or netn,

c3, r : c3 c, then the above conditions for spann, c, r 1 can berepresented by the following logic equation:

spann, c, r x.y.z x.y z majorityx, y, z (5.5)

In other words, spann, c, r 1 if any two of x, y, or z are 1. We canfurther simplify Eq. (5.5) using a dynamic programming approach where

the value of spann, c, r is computed from that of the previous column,spann, c 1, r. For the first column, c 1, spann, 1, r 1 if n

exists in column c as well as in some column to the right of c. Thus, for c

1, spann, 1, r netn, 1, r and z. For all other columns c 1,spann, c, r 1 under the following two conditions:

If n already spans column c 1 and is present in any column c3 c,

that is, spann, c, r spann, c 1, r and netn, c, r or z.

If n is present in column c and in a column c3 c, that is, spann, c,r netn, c, r and z.

n1n2

n3

c

Fig. 10. Three ways in which a net can span a column c.




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Combining the above two conditions, we get, for c 1

spann, c, r spann, c 1, r and netn, c, r or z

majorityspann, c 1, r, netn, c, r, z e

Theorem 1 is the basis of our extension of CLIP-W to the new ILP modelCLIP-WH that minimizes cell height and width.

6. WIDTH AND HEIGHT MINIMIZATION MODEL

Any formulation of height minimization must decide on the granularity ofthe grid that defines the vertical columns, and hence the complexity of theresulting model. Here, we define one vertical column for each of the threeterminalssource, gate, and drainof the P/N pairs placed in a P/N row.Figure 11 shows how the columns are numbered in a given row.

Inputs and outputs. In addition to the input parameters of the CLIP-W

model (Table III) and the integer Wcell, we have the integer maxCols, the

total number of columns in each P/N row (which is three times themaximum number of pairs that can be placed in any row of the 2D layout).

The columns are identified by the set cols 1, . . . , maxCols. All the variables in the CLIP-WH model are summarized in Table VIII

along with their decisions or interpretations. We introduce arrays

netnets, cols, rows and spannets, cols, rows of binary variables asdescribed in Section 5. Further, the binary array inter_rownets, rows is

such that inter_rown, r 1 if net n requires a track in the interrow

channel between rows r and r 1. The integer array heightCrows is

defined such that heightCr represents the height of the P/N channel

(C-region) in row r. Similarly, we define the integer arrayheightRrows 1 such that heightRr represents the height of the

Table VIII. Variables in the (13) CLIP-W and (18) CLIP-WH Models

Variables Decision/Interpretation

1. Xpairs, slots, rows Xp, s, r: Is pair p placed in slot s of row r?

2. Xorpairs, orients Xorp, o: Is pair p placed in orientation o?3. nogapslots, rows nogaps, r: Is there a diffusion gap between pairs in slots s ands 1 of row r?

4. netnets, cols, rows netn, c, r: Does net n exist on the top or bottom diffusions ofcolumn c in row r?

5. spannets, cols, rows spann, c, r: Does net n have a horizontal span in column c ofP/N row r?

6. interrownets, rows interrown, r: Does net n require a track in the interrowchannel between rows r and r 1?

7. heightCrows heightCr number of horizontal tracks in the P/N channel ofrow r

8. heightRrows heightRr number of horizontal tracks in the interrowbetween rows r and r 1




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interrow channel (R-region) between rows r and r 1. Since heightCr

and heightRr are both integers, they are represented by arrays ofboolean variables in the actual 0-1 model.

The objective is to minimize the cell height Hcell which, in turn, dependson the track densities in the P/N channels and the interrow channels, andis defined as follows:

minimize Hcell rP/N channels

heightCr r interrow channels

heightRr (6.1)

For a P/N channel in row r, its track density heightCr is determinedby the column that has the maximum number of nets spanning it, and isgiven by the function to be maximized in (Eq. (5.3). This nonlinear functioncan be linearized as follows:

heightCr nnets

spann, c, r @c cols (6.2)

We now need to determine the track density heightRr for each

interrow channel between adjacent P/N rows r and r 1. As discussedearlier, all terminals of nets that appear on both the P and N sides of a P/Nrow are connected in the rows P/N channel. Hence, for a net that appearson both sides of an interrow channel, only one terminal from each sideneeds to be connected to the other. Thus, the track minimization problem inthe interrow channels is defined as follows: For each net that appears on

both sides of the channel, select one terminal to be connected from eachside such that the overall track density in the channel is minimized. This isa complex routing problem, since it involves both terminal selection and

track computation. For example, net n2 in Figure 9 has one terminal on the

top and two on the bottom diffusion row of the interrow channel R1, 2; onlyone of its terminals in the bottom diffusion is connected to the one in thetop diffusion.

For purposes of ILP modeling, we simplify the above routing problem asfollows. We assume that each net that appears on both sides of an interrowchannel (and hence requires a track) is assigned a unique track. Then, the

interrow channel density is equal to the total number of nets that haveterminals on both sides of the channel. For example, the two-row layout in

Figure 9 requires two nets n1 and n3 to be connected in the interrowchannel. Although a single track is sufficient to route both nets as shown in

the figure, our model assigns a track for each net. Thus, heightRr for

an interrow channel between rows r and r 1 is given by the followingequation:

heightRr nnets

interrown, r (6.3)

Constraints. The CLIP-WH model has eight types of constraints: (1)width constraints that restrict the cell width to equal Wmi n; (2) constraints




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to compute netn, c, r; (3) constraints that define spann, c, r for the

P/N channels; (4) constraints that determine interrown, r for theinterrow channels; (5) pair inclusion, (6) slot occupancy; (7) diffusionsharing; and (8) interrow connectivity constraints. Constraints (5 8) are

identical to those in the CLIP-W model. We now describe constraints (1 4)in detail using layouts of the 2-to-1 multiplexer circuit of Figure 7(a) as anillustration. These layouts are shown in Figure 12.

(1) Cell width: Since we must generate layouts whose widths are equal to

the minimum width Wmi n, we must ensure that the width of each row

does not exceed Wmi n.

Wmin 2 ppairs

Xrowp, r sslots

nogapss, r vr 1 @r rows (6.4)

(2) Net presence: If c represents a diffusion terminal (c 1, 3, 4, 6, . . . ),

netn, 4, r depends both on the choice and orientation of the pair

placed in the slot corresponding to c. For example, for c 4, netn,

4, r 1, if there is a pair p placed in slot s 2 and its orientation

causes its diffusion terminal on net n to appear on its left side. Thus, if

c represents a left diffusion column (c 1, 4, 7, . . . ), the correspond-ing slot is c 23, and netn, c, r is given by the equation below.

Here, Nsrc, Ndrn, Psrc, and Pdrn, described in Table III, are inputparameters specified by the circuits netlist.

netn, c, r Xp, c 23, r @p pairsand Nsrcp, n and Xorp, 1 or Xorp, 3or Ndrnp, n and Xorp, 2 or Xorp, 4or Psrcp, n and Xorp, 1 or Xorp, 2or Pdrnp, n and Xorp, 3 or Xorp, 4 (6.5)

The value ofnetn, c, r is similarly defined for columns that represent the

right diffusions c 3, 6, 9, . . . , with the corresponding slot being c3:

netn, c, r Xp, c3, r @p pairs

andNdrn

p, n

and

Xor

p, 1

or Xor

p, 3

or Nsrcp, n and Xorp, 2 or Xorp, 4or Pdrnp, n and Xorp, 1 or Xorp, 2or Psrcp, n and Xorp, 3 or Xorp, 4 (6.6)

However, if c is a gate terminal (c 2, 5, 8, . . . ), then netn, c, r isindependent of the orientation of the pair placed in the corresponding slot

c 13, and is given by

netn, c, r ppairs

if Ngatep, n then Xp, c 13, r (6.7)

Here Ngatep, n and Pgatep, n, defined in Table III, are both 0-1input parameters which are set to 1 if pair p has net n on the gate terminal




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of its N or P transistor, respectively. The above linear constraint is an

equation since, for any column c, at most one of Xp, c 13, r cantake the value 1 in a given solution. Hence, this constraint can be

incorporated directly into the definitions for spann, c, r, thereby elimi-nating the variables netn, c, r, for c 2, 5, 8, etc.

(3) Net span: The constraint for spann, c, r is given by Theorem 1.However, some modifications are required in order to accommodate thepresence or absence of diffusion gaps.

For example, consider the net a in columns 1 and 3 of Figure 11. Since

columns 1, 2, and 3 need a track to connect net a, spana, 1, r

spana, 2, r spana, 3, r 1. Also, since columns 3 and 4 are con-

nected by diffusion sharing, we set spana, 4, r 1. However, net bappears only in columns 9 and 10, which are connected via diffusion

sharing. Hence, spanb, 9, r spanb, 10, r 0. Now consider net c

in columns 6 and 7 of the P and N diffusion terminals of pairs p2 and p3,respectively. These columns are separated by a diffusion gap. Hence,

spanc, 6, r spanc, 7, r 1. Further, we assume that if a net, such

as d, appears on the same (P or N) diffusion of two P/N pairs separated bya gap, it is connected using metal1 to avoid long diffusion wires, and hence

requires a horizontal track. Thus, spand, 12, r spand, 13, r 1.To summarize, if a net appears only on two adjacent terminals that are

connected via diffusion sharing, then it does not require a track; however, ifthe two terminals are separated by a gap, then span for the correspondingcolumns is set to 1 to indicate that a track is required.

Based on the above discussion, the constraint for spann, c, r for the

right diffusion terminals, that is, c 3, 6, 9, etc., is split into two: The

first constraint considers all columns c2 c 2, while the second consid-

ers the column c 1 on its immediate right. The second constraint takes

into account the absence of a gap, defined by nogapc3, r, between

columns c and c 1.

spann, c, r majority spann, c 1, r, netn, c, r,or netn, c2, r : c2 c 2 (6.8)

Fig. 11. Illustration of routing track requirements with and without diffusion gaps.




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spann, c, r majority spann, c 1, r, netn, c, r,netn, c 1, r : nogapc3, r (6.9)

For c 1, 2, 4, 5, 7, 8, . . . (the left diffusion terminal and gates of

transistors), we have

spann, c, r majority spann, c 1, r, netn, c, r,or netn, c2, r : c2 c 1 (6.10)

Further, in the case of commonly used dual CMOS circuits, in which each

P/N pair has the same gate net, we can eliminate the spann, c, r

constraints for gate terminals c 2, 5, 8, etc., based on the followingtheorem:

THEOREM

2. Consider a functional cell layout of a dual CMOS circuitwith P and N transistors of dual P/N pairs placed vertically aligned so asto share their common gate signal. Then, the horizontal track density of a

gate column c is no greater than the maximum of the track densities of its

adjoining diffusion columns c 1 and c 1.

PROOF. All P/N pairs of a dual CMOS circuit have a common gate net.

Hence, each gate column c has exactly one net, say n. The track density of

c can depend only on the following three types of nets: (1) nets that start

before c and stop after c; (2) nets that start before c and stop at c; and (3)

nets that start at c and stop after c. Nets of type (1) contribute one track to

all three columns c 1, c and c 1. Nets of type (2) require a track in

column c 1 and c. And nets of type (3) require a track in columns c andc 1. Since the gate column has exactly one net n, cases (2) and (3) are

mutually exclusive, that is, net n can either stop at c or start from c, but

not both. Hence, the track density of a gate column c can never be greater

than the maximum of the track densities of its adjoining columns c 1

and c 1. e

Therefore, the variables spann, c, r are eliminated for gate columns,

and constraints (6.8) and (6.9) are suitably modified to consider spann,c 2, r instead of spann, c 1, r.

(4) Interrow channel routing: As discussed earlier, we approximate the

track requirement heightRr in each interrow channel by the num-ber of nets that have terminals on both sides of the channel. Thus,

interrown, r for an interrow channel between rows r and r 1 isgiven as follows, where both terms of the and expression are availableas variables that model interrow connectivity (see Section 4), and canbe used directly.

inter_rown, r net n appears on top diffusionand net n appears on bottom diffusion of row r




33/38


34/38

tracks for the interrow channel. Thus, for Figure 12(b), Hcell 1 1 2

4. Again, due to the assumption made for interrow track density in our

model, this value of Hcell is greater than its minimum value of 3 shown inFigure 1(b).

7. EXPERIMENTAL RESULTSFor the circuits of Table V, Table IX presents results on the minimum cell

height Hcell, in terms of the total number of routing tracks required in allP/N and interrow channels, and run times (using the -h3 variable selectionheuristic of the OPBDP solver) obtained by solving the CLIP-W model. Thecell width in all cases was constrained to be equal to the minimum width

Wcell obtained with CLIP-W (Table V).

We observe that in most cases, the increase in Hcell is much less than the

decrease in Wcell when the layout changes from one to two rows. This cantranslate into significant area savings depending on the process technology.These savings are less pronounced for three and four-row layouts, sinceboth the cell width and the number of tracks change very little, if at all,while the number of P/N rows increases. Table IX also breaks down the

optimal cell height Hcell into the contributions of the P/N and the interrowchannels. The contribution of the P/N channels is seen to be monotonicallynonincreasing. This can be attributed to the fact that as the number of P/Nrows is increased, the number of transistors in each row decreases. This, inturn, reduces the horizontal overlap of nets in each row, and hence the P/Nchannel density. Also, CLIP layouts are significantly smaller than thoseobtained by the Cadence tool Virtuoso [Cadence Design Systems, Inc.199294]. On the average, the cell heights obtained with CLIP are 25%smaller than the corresponding Virtuoso designs.

Fig. 12. Layouts of the multiplexer circuit of Figure 7 in (a) one, and (b) two rows.




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CLIP-WHs run times for layouts of up to four P/N rows are in seconds formedium-sized circuits with up to 20 transistors. Moreover, as the results inTable IX demonstrate, an optimal solution is found in a relatively shorttime; the remaining time is utilized in exploring the search space to verifyoptimality. Hence, the ILP solver can often be prematurely terminated toyield near-optimal, or possibly even optimal, solutions. In Gupta and Hayes[1997] and Gupta [1997] we present circuit partitioning and hierarchicalmethods that make CLIP viable for much larger circuits while yieldinglayouts that are at or near the optimum.

Table IX. 2D Placements of Minimum Cell Width Wcell and Height Hcell Using CLIP andthe Corresponding Run Times for the First and Final Optimal Solution

Cct.

no.

No. of

trans.

No. of

rows

CPU time (secs)1 CLIP layout Virtuoso layout2

Firstoptimal

solution

Finaloptimal

solution Wcell3 Hcell

4

Cell

width

Cell

height

1 10 1 0.04 0.05 5 4 (40) 5 42 0.13 0.37 3 6 (31) 4 63 3 4 3 5 (23) 4 64 1 2 4 3 (03) 4 6

2 10 1 0.1 0.5 6 4 (40) 6 42 2 2.5 5 3 (12) 5 33 4 5 4 3 (03) 5 44 2 2 4 3 (03) 5 4

3 12 1 0.1 0.4 7 3 (30) 7 3

2 4 5 3 5 (32) 4 53 0.5 1 3 4 (22) 3 54 6 12 3 4 (13) 5 5

4 14 1 0.3 1 8 3 (30) 8 32 0.5 2 4 4 (22) 5 43 1 8 3 5 (23) 3 74 5 17 3 5 (14) 3 5

5 16 1 0.2 0.3 8 4 (40) 9 42 1 30 6 5 (32) 7 73 36 347 5 4 (22) 7 64 35 516 5 3 (12) 7 5

6 18 1 0.8 5 10 5 (50) 10 6

2 780 5,771 5 6 (42) 6 73 237 3,673 4 6 (33) 5 7

7 20 1 1.3 27 11 3 (30) 11 32 631 1342 7 5 (32) 7 5

8 24 1 2 73 13 3 (30) 14 39 24 1 340 4698 14 2 (20) 15 3

1. Run times are with the OPBDP solver (using its -h3 variable selection heuristic) on theHP 9000/735.

2. Layouts were obtained using the Virtuoso options that are closest to our layout style.3. Optimal cell widths Wcell were obtained with the CLIP-W model presented in Section 4.4. The first and second numbers in brackets are the contributions of the P/N channels and

interrow channels, respectively, to the cell height.




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8. CONCLUSIONS

We have presented the first exact algorithmic technique, CLIP, for simul-taneous height and width optimization of two-dimensional CMOS celllayout. It combines the interdependent problems of diffusion sharing,

vertical interrow connectivity, and horizontal routing track density in acommon problem space that can be efficiently searched for optimal solu-tions using branch-and-bound methods such as those of ILP solvers. TheCLIP-W model precisely formulates 2D cell width minimization in terms oftransistor placement, diffusion sharing, and vertical interconnections.Then, CLIP-WH models cell height accurately in terms of the total trackdensity in all the routing channels. Within its modeling assumptions, CLIPguarantees optimal layouts. It is practical for cells with 30 or moretransistors for width minimzation alone, and for cells with up to 20transitors for both height and width minimization. CLIPs layouts have

proven to be significantly better than those of commercial tools such asVirtuoso. To make CLIP practical for larger circuits, circuit pre-processingand hierarchical methods, which we have presented elsewhere, can reducethe run times while yielding near-optimal results.

REFERENCES

BALTUS, D. G. AND ALLEN, J. 1988. SOLO: A generator of efficient layouts from optimizedMOS circuit schematics. In Proceedings of the 25th ACM/IEEE Conference on DesignAutomation (DAC 88, Atlantic City, NJ, June 1215, 1988), D. W. Shaklee and A. R.Newton, Eds. IEEE Computer Society Press, Los Alamitos, CA, 445 452.

BARTH, P. 1996. Logic-Based 0-1 Constraint Programming. Kluwer operations research/computer science interfaces series. Kluwer Academic Publishers, Hingham, MA.

BASARAN, B. AND RUTENBAR, R. 1996. Efficient area minimization for dynamic CMOScircuits. In Proceedings of the IEEE Conference on Custom Integrated Circuits (Santa

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