A spreadsheet simulation of logic networks

IEEE TRANSACTIONS ON EDUCATION, VOL. 34. NO. I . FEBRUARY 1991 43

A Spreadsheet Simulation of Logic Networks Ali El-Hajj and Karim Y. Kabalan, Member, IEEE

Abslrucf-In this paper a method for simulating logic networks using spreadsheets is presented. This method may be used to simulate combinational, sequential, synchronous, and asynchronous networks. The characteristics of the method make it significant as an important tool in the analysis, design, and test of logic networks in education envi- ronments.

I. INTRODUCTION PREADSHEETS have been initially designed and used for S business and financial applications. Many references [ 11-[4]

are structured to present the characteristics and the features of different spreadsheet programs. The use of these programs has been recently extended to treat some science and engineering problems such as the ones presented in [5]-[7]. An attractive feature of many spreadsheet programs is the existence of Boof- e m functions. Such functions were used by Huelsman in [7] to display the truth table of logic expressions and to simulate the operation of an S-R flip-flop. He concluded that an advanced application of the logic capabilities of spreadsheet programs is to use sections of the spreadsheet to simulate complete IC’s and of the formula capability to provide the desired pin-to-pin wir- ing. In this paper, a method based on Huelsman’s suggestion is presented to simulate a complete logic network using the lotus 1-2-3 spreadsheet program. The presented method has the following advantages:

1) It is flexible and easy to learn since it is based on the use of the spreadsheet. Connections between circuits are very easy to perform.

2) The user is not limited by the number of available gates or flip-flops as in hardware realizations. It is possible to add at any time any gate or flip-flop using the copy command provided that the computer memory is not full.

3) It is possible to follow the evolution of a network step by step or in many steps at a time. In such cases, the user has the freedom to specify the length of a step. (a step corresponds to one or more spreadsheet recalculations). 4) Some unstable states in sequential logic are easily de-

tected by this method where as some advanced electronic equip- ment are required in hardware realization.

5 ) The user may employ this method for the simulation and verification of any circuit before the hardware realization. This will reduce the effort and time, and will minimize the possibility of component damages due to some mistakes.

The primary application of this method is in the university environment where spreadsheet programs are common and in- expensive and costs prevent the availability of sophisticated simulation systems for introductory logic design courses. A

Manuscript received October 31, 1989; revised May 24, 1990. The authors are with the Department of Electrical Engineering, Faculty

of Engineering and Architecture, American University of Beirut, Beirut, Lebanon.

IEEE Log Number 904 1504.

limitation of this method is its inability to model gate delays which is essential in industry.

In order to outline the basic concepts used in the design, analysis, and the way components are used to construct digital systems, this paper is subdivided into two sections. Section I1 deals with the simulation of logic gates and includes examples corresponding to combinational and sequential design. Section 111 discusses the representation of flip-flops with some advanced examples.

11. LOGIC GATE REPRESENTATION The representation of a gate in its standard format is not pos-

sible since a worksheet does not contain graphics capabilities. Therefore, a logic gate is represented by a rectangle containing the name of the corresponding gate where each input or output is symbolized by a dash. The value of the output is a Boolean function of the inputs that characterizes the nature of the gate. As an example, Fig. 1 shows AND, NAND, OR, NOR, and XOR gates with their input-output ports as well as the formula relat- ing the outputs to the inputs. In order to have a clear display, the global column width of the worksheet is set to three which is also convenient for flip-flops. Fig. 2 shows all types of gates on the same worksheet using this setting. The connection between these gates is done by simply giving the input of the next gate a formula corresponding to the address of the output of the previous one. It is possible to obtain as many gates of any kind as needed by using the copy command on the range to which the copied gate belongs. Fig. 3 shows a three-level OR-AND-OR combinational network representing the function

f = c’d(a’ + b) + cd’(a + b ) . (1)

In (l), x’ denotes not ( x ) . Figs. 4 and 5 show the spreadsheet simulation of this network and its response for a = 0, b = 1, c = 1, and d = 0. The columnwise recalculation mode has been selected for many reasons:

1) It can be seen from this example that the final answer is obtained in the first recalculation. The row-wise recalculation requires many iterations before giving the final answer.

2) In the case of sequential networks, the columnwise recalculation requires, in general, less iterations than the row-wise one.

3) The natural mode recalculation gives circular reference errors in sequential logic.

In the case of asynchronous sequential networks when the input changes, some spreadsheet recalculations are, in general, necessary to obtain the new output values. However, it is possible to detect the unstable state obtained before the outputs reach their final values by setting the recalculation mode to manual and the iteration count to one. This remark applies to all sequential circuits and as a result some unstable states are recognized by this method. As an example, Fig. 6 shows the spreadsheet simulation of an S-R flip-flop. When the input is

0018-9359/91/0200-0043$01 .OO 0 1991 IEEE

44 IEEE TRANSACTIONS ON EDUCATION. VOL. 34, NO. 1 , FEBRUARY 1991

A B C D A B C D E F G H I J K L M N O P Q

I

1 2 l - : A : 3 1 - 1 N -(AZ#AND#A3#AND#A4#AND#ASl 4 l - : D :

_ _ _

5 1 - : _ _ - I

A B C D 1 2 l - I N : 3 1 - : A -(#NOT#(A2#AND#A3#AND#A4#AND#ASI)

_ _ _ 12 d'.(#NOT#BllI 0 - : R I (G11) - : D I3 0 - : _ _ _ : 1 - : _ _ _ : 1 4

Fig. 4. Spreadsheet simulation of the circuit of Fig. 3.

A B C D A B C D E F G H I J K L M N O P Q 1 2 0 - : : 3 G - : 0 -iA2#0R#A3#OR#A4#OR#AS)

_ _ _

A B C 1 i: O - : N : 3 0 - : 0 -(#NOT#(AZ#0R#A3#0R#A4#OR#A5)1 4 O - : R :

E _ _ _

5 0 - : _ _ _ :

A B C 1 2 : x : 3 0 - : 0 -~~A3#AND##NOT#A41#0R#(A4#AND##NOT#A3)) 4 O - : R : 5

D _ _ _

I ,

I _ _ _ '

Fig. 1. Spreadsheet simulation of different logic gates.

A B C D E F G H I J K L M N O P Q R S T 1

: x : 2 l - : A I 1 - I N : 0 - : 1 G - : N : 3 1 - : N - l 1 - : A - O 0 - I O - 0 O - : O - l O - : O - O 4 l - : D : l - : N I 0 - : R : O - : R : 0 - i R :

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

? I 5 1 - : - - - : 1 -:-D_I 0 - I _ _ _ : 0 -:---: I _ _ _ I Fig. 2. Spreadsheet display of different logic gates.

33--f

Fig. 3 . Combinational logic circuit representing the functionf = c 'd(a ' + 6 ) + cd'(a + b ) .

changed, two recalculations of the spreadsheet are, in general, necessary to obtain the new output values.

111. FLIP-FLOPS REPRESENTATION

In this section, the simulation of unclocked and clocked flip- flops will be investigated. The S-R flip-flop will be studied in detail and the simulation of the most common types of flip-flops is also included.

8 9 10 11 1 2 13 14

a : o a ' : 1

b : l b ' : 0

c : 1 C'. 0

d : O d ' . 1

__- 0 - : I 1 - : o - 1 0 - I R 0 - : _ _ - :

1

Fig. 5. Spreadsheet response to the circuit of Fig. 4.

A B C D E F 1 2 3 5: 1 - : N : 4 (F10) - I 0 - 0

_-_

8 9 (F41 - I N 10 R : 0 - ; 0 - 1 11 0 - : R 12 0 - : _ _ - : 13

_ _ _

Fig. 6 . Spreadsheet simulation of an unclocked S-R flip-flop using two NOR gates.

9

Fig. 7. Spreadsheet simulation of an unclocked S-R flip-flop

column width setting). The J-K flip-flop is similarly represented by replacing S and R by J and K , respectively, and by changing the output formulas to Q = [ ( Q and not ( K ) ) or (Q' a n d J ) ] where Q' = [not ( Q ) ] .

B. The Clock Simulation Fig. 8 shows the spreadsheet simulation of a clock. In this

figure, Cell C1 represents the length of a clock cycle in terms of the number of recalculations performed by the spreadsheet. Cell C 2 represents a counter incremented by one at each iteration and that retums to one if its value reaches the content of cell C1. Cell C4 represents the clock: its state is zero and becomes one when the value of the counter C 2 becomes equal to the value stored in cell F1 and then retums to zero in the next iteration. Cell J1 represents a flag that initializes the clock and the counter. The clock will operate if this flag is set to one otherwise the counter will take a value of one and cannot be incremented. This flag is also used to reset the clock to its initial state if the calculation is not necessary to continue after some iterations.

A. The Unclocked Flip-Flop

The use of two gates, as in Fig. 6, to represent an unclocked S-R flip-flop is not practical. As an alternative, a box with inputs S and R and outputs Q = [not (Q' or R ) ] and Q' = [not ( Q or S ) ] , is adopted. This representation (Fig. 7) provides the same function as in Fig. 6 (g was replaced by Q' to match the

EL-HAJJ AND KABALAN: SPREADSHEET SIMULATION OF LOGIC NETWORKS 45

& a C D E F G H I J A B C D E F G A E C D E F G 5 5 6 6 CLR 1

1 CYCLE: 6 HIGH ; 2 FLAG : 1

3 7 7 _ _ - _ _ I _ _

2 COUNT:@IF(@MOD(C3,C1)=0,1,(C3+1)) @IF(Jl=O.O.C2) _-__-_--

5 9 9 - I

4 CLOCK:@IF~(C2=F1)YAND#(J1=11#AND#(C2~11,1.0) 8 1 - : S Q I - 1 8 1 - : S Q : - 1

Fig. 8. Spreadsheet simulation of a clock

To follow the operation of a synchronous network cycle by cycle, the iteration count of the spreadsheet is set to the same value of cell C1, and a manual recalculation is used. In general, the value of the iteration count and the type of recalculation (manual or automatic) are used to follow the operation of a network at the desired speed.

C. The Clocked Flip-Flops Simulation

Fig. 9(a) shows the representation of a clocked S-R flip-flop. The inputs are: S ( B 8 ) , R(B10), and the clock whose value is defined in the previous section has been assigned the name CK. To be able to detect changes in state of the clock, the value of cell (B12) is given to (B11) . In order to prevent a change of state of S or R at the beginning of a clock cycle before the output Q is calculated (this is possible if the position of the flip-flop in the worksheet is not in the first few columns), the values of S and R are reproduced at some other convenient addresses ( E 8 for S and E10 for R for example). This should be done before the beginning of the current clock cycle; for example; at the end of the previous clock cycle where no significant calcula- tions on the worksheet may be performed. The formulas at these addresses are then

10 0 -:R 0:- 0 10 0 -:R a ; - 0 11 12 0 -:CK : 14

11 12 0 -:CK

14 15

13 1 _ _ _ _ - _ _ _ ~ 13 1-- _ _ _ - _ _ 1

PR

(a) (b)

Fig. 9. (a) Spreadsheet display of a clocked S-R flip-flop. (b) Spreadsheet display of a clocked S-R flip-Hop with clear and preset inputs.

A E C D E F G A B C D E F G 5 5 6 6 CLR 1

(a) (b)

Fig. 10. (a) Spreadsheet display of a clocked D flip-Hop. (b) Spreadsheet display of a clocked D flip-Hop with clear and preset inputs.

The simulation of a J-K flip-flop is similar to that of an S-R flip-flop, but the symbols S and R are respectively replaced by J and K, and the output formula used in this case is given by

Q' = JQ' + K Q . ( 6 )

The corresponding worksheet formula with clear and preset inputs is then

G8: @1F(E15 = 1 , 1 ,@iF(E6= 1,0,@1~(B12 = ~ # A N D # B ~ 1 =o, (E8) : @IF($C$2=$C$l,B8,E8)

(E 10) : @IF($C$2 = $C$ 1 , B 10,E 10). ( 2 ) The outputs Q and Q' are then functions of E 8 and E10 instead of B 8 (for S ) and B10 (for R ) directly. For display conve- nience, the cells ( B l l ) , ( E 8 ) , and (E10) have been hidden from the user. Moreover, the formula used in Section 111-A to simulate an S-R flip-flop requires two spreadsheet recalculations and thus two cycles for an S-R flip-flop or a special clock with larger pulses different from that used for the clocked D and J-K flip-flops. To solve this problem, and since the state S = R = 1 is not allowed, the following formulas are used [8]:

Q+ = S + R'Q

Q" = not ( Q + ) . ( 3 )

In this case, all flip-flops will use the same clock defined in the previous section. For an S-R flip-flop where the state changes occur on a low to high transition, the formulas for the outputs Q ( G 8 ) and Q ' ( G10) are given by

G8: @1~(B12= ~ # A N D # B ~ 1 =O,E~#OR#

( (#NOTE 1 O)#AND#G8) ,G8)

G10: (#NoT#G~). (4 )

For a flip-flop where the state changes occur on a high to low transition, the condition B12= ~ # A N D # B ~ 1 =0, is replaced by

(E~#AND#G~O)#OR#((#NOT#E IO)#AND#G~),G~))) ( 7 )

In the case of a D flip-flop (see Fig. 10) the formula used is

Q+ = D ( 8 )

which gives the worksheet formula:

G8: @IF@ 15 = 1, l ,@1~(E6 = 1 ,0,

@ I F ( B ~ ~ = ~ # A N D # B ~ ~ =O,E8,G8))). (9)

D. Simulation of Complex Networks The connections between flip-flops follow the same rules as

in the case of logic gates. It is then possible to construct a complete logic network from gates and flip-flops and to follow its evolution step-by-step or continuously with very small effort. As an example, Fig. 1 1 shows a synchronous modulo 10 counter [9] and its simulation on the worksheet. The four outputs of the flip-flops represent the count number which is actually equal to 4. In each manual recalculation, the count number is incremented by one and is reset to zero when it reaches the value of 10. The user can easily follow and verify the operation of this counter.

B12=0#AND#Bll=l. If the S-R flip-flop has clear ( E 6 ) and preset ( E 1 5 ) inputs active at a high state [see Fig. 9(b)], the formula giving Q becomes

IV. CONCLUSION A method for simulating logic networks using spreadsheets

has been presented. This method is capable of simulating com- G8: @IF(E15= 1,1,@1~(E6= 1,0, binational, sequential, synchronous, and asynchronous net-

works. The method suggested has been tried with success on many examples. It is easy to learn, and it saves a lot of time and effort for its user. It can be easily extended to simulate other

@r~(B12= ~ # A N D # B ~ 1 =O,E~#OR#

((#NOT#E~~)#AND#G~),G~))). ( 5 )

46

I

IEEE TRANSACTIONS ON EDUCATION. VOL. 34. NO. I . FEBRUARY 1991

(b) Fig. 11, (a) Synchronous mod-10 counter. (b) Spreadsheet simulation of

the counter of Fig. 1 l(a).

logic IC’s and opens new horizons in the use of spreadsheet programs. A disadvantage of this method is that it does not al- low us to study the timing problems. This limits the use of the method to educational applications since time delays are very important in the industry.

ACKNOWLEDGMENT

The authors are grateful to one of the reviewers for his con- structive and detailed comments. The assistance provided by F. Nazzal is greatly appreciated.

REFERENCES

[ 11 Symphony Reference Manual, Lotus Development Corp., 1985. [2] Lorus 1-2-3, Software and Reference Manual, Release 2. Cam-

[3] Microsoji Multiplan, Electronic Worksheet and Reference Man- bridge. MA: Lotus Development Corp., 1985.

ual. Microsoft Corporation, Redmond, WA, 1983.

[4] Supercalc, User’s Guide and Reference Manual, SORCIM Corp., San Jose, CA, 1982.

[SI S . R. Trost and C. Ponernachi, Visicalc fo r Science and Engi- neering. Berkeley: Sybex, 1983.

[6] W. J . Orvis, 1-2-3 For Scienrisrs and Engineers. Berkeley: Sy- bex, 1987.

[7] L. P. Huelsman, “Electrical engineering applications of micro- comuuter spreadsheet analysis programs,” IEEE Trans. Educ. , . - vol.’E-27, pp. 86-92, 1984.

MN: West, 1985. [SI C . H. Roth, Jr., Fundamentals ofLogic Design, 3rd ed. St. Paul,

[9] J . P. Remblier, J. Renouard, and J . Szylowicz, Logique Stquen- tielle, Ecole Superieure d’tlectricitk, Paris, 1980.

Ali El-Hajj was born in Aramta, Lebanon, 1959. He received the B.S degree in physics from the Lebanese University, Lebanon, in 1979, the Degree of “Ingenieer” from L’Ecole Supeneure d’Electricite”, France, in 1981 and the “Doctor Ingenieer Degree” from the Uni- versity of Rennes I, France, in 1983

From 1983 to 1987, he was an assistant professor of Electrical Engineering at the Le- banese University Since 1987, he has been with the Electrical Engineenng Department,

Faculty of Engineering and Architecture, American University of Bei- rut. He has contributed on the design of many CAD packages for education in different domains in Electrical Engineering His research interests are in numerical analysis, optimization techniques, and software development.

Karim Y. Kabalan (M’88) was born in Jbeil, Lebanon. He received the B.S. degree in physics from the Lebanese University, Lebanon, in 1979, and the M S . and Ph D. degrees in electrical engineering from Syracuse University, Syracuse, NY in 1983 and 1985, respectively.

During 1986 Fall semester, he was a visiting assistant professor of Electrical Engineenng at Syracuse University. Since then, he has been with the Department of Electrical Engineering, Faculty of Engineering and Architecturc,

American University of Beiruit. His research interests are in numerical solution of electromagnetic field problems and software development

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A spreadsheet simulation of logic networks