A Photonic Interconnect Layer on Siliconphotonics.intec.ugent.be/download/ocs105.pdf · 1 A Photonic Interconnect Layer on Silicon Dries Van Thourhout – MNE ‘07 A Photonic Interconnect

1

A Photonic Interconnect Layer on SiliconDries Van Thourhout – MNE ‘07

A Photonic Interconnect Layer on SiliconDries Van Thourhout – MNE ‘07

Electrically pumped

Array of InPmicrodisk sources

Silicon wire waveguides

Towards microdetectors

2

© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be

The photonics research group at INTEC/IMECP. Dumon, W. Bogaerts, G. Roelkens, J. Van Campenhout, F. Vanlaere, J. Schrauwen, S. Verstuyft, L. Van Landschoot, J. Brouckaert, G. Priem, D. Taillaert, S. Scheerlinck, P. Debackere, S. Selvarajan…D. Van Thourhout, P. Bienstman, R. Baets

The Silicon Process division at IMECVincent Wiaux, Stephan Beckx, Johan Wouters, Diziana Vangoidsenhoven, Rudi De Ruyter, Johan Mees

PICMOS partnersJ.M. Fedeli, L. Di Cioccio (LETI) (molecular bonding, processing)C. Lagahe, B. Aspar (TRACIT) (planarization)C. Seassal, P. Rojo-Romeo, P. Regreny (CNRS-Lyon) (processing, epitaxy)R. Notzel, X.J.M. Leijtens (TU/e) (epitaxy)

European Union, Belgian and Flemish government

Acknowledgements


A Photonic Interconnect Layer on Silicon

OutlineSilicon photonics: why, how, who ?Passive structuresTowards active devices: InP on SOIAn application: on-chip optical interconnectConclusion and outlook

3


Electronics vs. PhotonicsElectronics

Single material: Silicon(also provides insulator SiO2)

One platform: CMOS

Large market: highly tuned, matureprocesses

One main building block:the transistor

Common ITRS roadmap(dominated by a few largecompanies)

Size: 10nm few um

PhotonicsMany incompatible materials: GaAs, InP, Polymers, LiNbO3 ,...

Many processing technologies

Limited market: primitive processes

Many building blocks: resonators, lasers, detectors, ...

Many factions pushing their ownsolutions

Size: few um few cm

Pentium 4


Silicon photonics… the solution to all our problems

Transparent at telecom wavelengths (1.3um, 1.55um)

High refractive index contrast ultra-compact circuits

“Compatible” with CMOS-processingHighest quality processesHigh yield, high repeatability

4


Typical waveguide structure

SiO2 (1-2um)

Waveguide Definition

Width (500nm) x Height (220nm)

Silicon

Similar waveguide structure used by many other groupsIMEC, LETI, Pirelli, MIT, IBM, Luxtera, NTT, NEC, Cornell, Yokahama …

Typical loss: 1.5dB/cm – 3dB/cmDominated by LER(see also poster P-NSC-37 by S. Sardo e.a.)

Pattern definition: ebeam lithography, nanoimprint, DUV litho


Our current Fabrication Process

Si-substrate

SiO2

SiPhotoresist Photoresist

AR-coating

wafer Photoresist(UV3)

Bare Soft bake AR coating Illumination(248nm or 193 deep UV)

bakePost Development Resist Hardening

Silicon etch Resist strip

5


Basic structures

(b)

Exce

ssbe

ndlo

ss [d

B/9

0°]

0.08

0.06

0.04

0.02

01 2 3 4 5

0.004dB/90°0.01dB/90°

0.027dB/90°

0.09dB/90°

Low loss bendsLow loss bends <0.3dB excess loss for splitters<0.3dB excess loss for splitters

Radius [um]

97% transmission in crossings97% transmission in crossings


Wavelength dependent devices

6


Complex filters9x16 AWG

16 channels, 200GHz channel spacing

36 arrayed waveguides

0.1mm2 footprint

shallow etchdeep etch

waveguide

500nm800nm

10µm

10µm

5µm

2µm

100µm

1520 1525 1530 1535 1540 1545 1550 1555 1560wavelength [nm]

-30

-25

-20

-15

-10

-5

0

trans

mis

sion

[dB]

1 2 3 4 8 16 1

FSR

• 2.2dB insertion loss (on-chip)• 18dB crosstalk suppression


Increasing Index Contrast

Glass photonic ICsLow Contrast - Fiber Matched(doped silica vs pure silica)

Waveguide: 10x10 µmBend Radius ~ 5 mm

III-V photonic ICsMedium Contrast (InGaAsP vs InP)

Waveguide: 2x1µm Bend Radius ~ 500µm

5 mm

Silicon photonic ICsUltra-high Contrast

(silicon vs silica)Waveguide: 500x200nm

Bend Radius < 5µm

200

µm

5 cm

7


Is this Nano ?

Typical linewidth: 400nm to 500nm

Hole pitch: 300nm to 500nn

Photonic crystalRing resonator


Is this Nano ?

Typical linewidth: 400nm to 500nm

Hole pitch: 300nm to 500nn

BUTLinewidth needs to be controlled within 1nm (or below ) !

LER < 2nm !

Holes, gaps, narrow lines all on same litho level !

Photonic crystalRing resonator

Tran

smis

sion

[dB

]

Wavelength [nm]

1nm linewidth change

> 1nm shift in resonance frequency

through

drop

8


Use for sensing …Two dimensional strain sensor

Silicon circuits transferred to polyimide film

Biosensor

Reference



OutlineSilicon photonics: why, how, who ?Passive structuresTowards active devicesAn application: on-chip optical interconnectConclusion and outlook

Silicon has indirect bandgap• Lot of research going on to overcome this problem

(nanocrystals, raman …)• Thus far not satisfactory

Integrate III-V with Silicon

Silicon has indirect bandgap• Lot of research going on to overcome this problem

(nanocrystals, raman …)• Thus far not satisfactory

Integrate III-V with Silicon

9


III-V on Silicon ???Flip-chip bondingFlip-chip bonding

Thin film deviceintegration

Thin film deviceintegration

(IO-project)

(Duke Univesity)

III-V epi on SiliconIII-V epi on Silicon

Alignment ?Reliability ?Mass production ?

Integration throughdie-to-wafer bonding

Integration throughdie-to-wafer bonding


Proposed integration processStarting point: Processed SOI-waveguide wafer

248nm DUV lithographyFabricated in IMEC pilot CMOS-line

10


Proposed integration processPlanarization

PlanarizationSiO2-deposition and CMP (Collaboration with LETI/TRACIT)or: BCB spin-on-layer (IMEC)


Proposed integration processDie-to-wafer bonding

Bonding InP-dies on top of planarized SOI-waferLow alignment accuracy requiredFast pick-and-place

11


Proposed integration processSubstrate removal

Remove InP-substrate down to etch stop layerRemove etch stopThin membrane remains (200nm ~ 2um)


Proposed integration processHardmask deposition

Decontamination and hardmask depositionAlignment of waveguides and devices through lithographic methods

Micro-disk sources

DBR sources

Detectors

12


Proposed integration processProcessing of InP-optoelectronic devices

Mesa etching and Metallization“Waferscale” processing !!! (but on 2cm2 pieces)


Die-to-wafer BondingMolecular bonding (fusion)

InP on SOI-waveguides on CMOS demonstrated (LETI, TRACIT)

Polymer bondingPlanarization and bonding in single step (IMEC)

Ultra-thin bonding layers (sub 200nm demonstrated)

InP-layer

Si-wire

13


III-V/Silicon photonicsBonding of III-V epitaxial layers

Molecular die-to-wafer bondingBased on van der Waals attraction between wafer surfacesRequires “atomic contact” between both surfaces

- very sensitive to particles- very sensitive to roughness- very sensitive to contamination of surfaces

Adhesive die-to-wafer bondingUses an adhesive layer as a glue to stick both surfacesRequirements are more relaxed compared to Molecular

- glue compensates for particles (some)- glue compensates for roughness (all)- glue allows (some) contamination of surfaces

While established technology for SOI, IIIWhile established technology for SOI, III--Vs often do not Vs often do not meet the requirements for molecular bondingmeet the requirements for molecular bonding


Bonding TechnologyRequirements for the adhesive for bonding

Optically transparentHigh thermal stability (post-bonding thermal budget)Low curing temperature (low thermal stress)No outgassing upon curing (void formation)Resistant to all kinds of chemicals

Si

CH3

CH3

Si

CH3

CH3

O

1,3-divinyl-1,1,3,3-tetramethyldisiloxane-bisbenzocyclobutene

400C400C

250C250C

<0.1dB/cm<0.1dB/cm

OKOK

HCl,HHCl,H22SOSO44,H,H22OO22,,……

DVS-BCB satisfies these requirements

14


Bonding TechnologyOverview of the bonding process

Die/wafer cleaning most critical step in processingSOI wafer: standard clean – 1 (H2SO4:H2O2:H2O @70C)

Lifts off particles from surface and prevents redeposition

InP/InGaAsP: removal of sacrificial InP/InGaAs layer pair

Si-substrate

SiO2

SiDVS-BCB DVS-BCB DVS-BCB

DVS-BCB coating

Wafer cleaning

Solvent evap + prepolymerization

Die attachment

DVS-BCB

DVS-BCB curing (pressurized)


Bonding Technology

200nm

Cross-sectional image of III-V/Silicon substrate

InP-InGaAsPepitaxial layer stack

DVS-BCBSiO2

Si

Si Si WGDVS-BCB

SiO2

InP/InGaAsPepitaxial layer stack

200nm

15


Integrated Devices: laser diodeIntegrated laser diodes

Fabry-Perot laser cavity by etching InP/InGaAsP laser facets

Inverted adiabatic taper coupling approach


Integrated Devices: laser diodeIntegrated laser diodes

Only pulsed operation due to high thermal resistivity DVS-BCBIntegration of a heat sink to improve heat dissipationContinuous wave operation achieved this way

16


Hybrid Laser by INTEL/UCSB



OutlineSilicon photonics: why, how, who ?Passive structuresTowards active devices: InP on SOIAn application: on-chip optical interconnectConclusion and outlook

17


On-chip optical interconnect ?

PIC IBM chipITRS-roadmap

IBM Cell processorMulticore processor chipNow: ~ 1 TBit/s data bandwidthBy 2015: 35-70TBit/s expected !Note: 10MBit/s.km = 1Tbit/s.cm

IBM Cell processorMulticore processor chipNow: ~ 1 TBit/s data bandwidthBy 2015: 35-70TBit/s expected !Note: 10MBit/s.km = 1Tbit/s.cm

ITRS-roadmap requests research in alternative interconnect options

Optical one possible optionDeployment expected around 2015

ITRS-roadmap requests research in alternative interconnect options

Optical one possible optionDeployment expected around 2015

communication


On-chip optical interconnect ?Our goal: build photonic interconnect layer on CMOS

Using on-chip microsources and detectorsCompatible with IC-productionAt reasonable price waferscale processesBetween topmost metal layers

18


Integrated microdisk laserMicrodisk laser design

Whispering-gallery modesCentral top contactBottom contact on thinlateral contact layer (ts)Hole injection througha reverse-biasedtunnel-junction

Si substrate

SiO2Si waveguide

top contactbottom contact active layer

tunnel junction

InP

2Rdisk

dox

wSi

t

ts

Microdisk thickness 0.5 < t < 1µm

Evanescent coupling to SOI wirewaveguide (500x220nm2)

→ European research programme PICMOS (Photonic Interconnect Layer on CMOS by Waferscale Integration,

FP6-2002-IST-1-002131)


Integrated microdisk laser

Si substrate

SiO2Si waveguide

top contactbottom contact active layer

tunnel junction

InP

2Rdisk

dox

wSi

t

ts

InP island

25 µm

microdisk

SOI waveguide

Si substrate

SiO2 Si wire

BCBInP - InGaAsP

130-nm bonding layer

19


Measurement setupcamera

camera image

Single-mode fiber

probe needles SM fiberfiber couplers

microdisks


0

5

10

15

20

25

30

0 0.5 1 1.5 2Current (mA)

Out

put p

ower

(µW

)

0

0.5

1

1.5

2

2.5

Volta

ge (V

)

CW power

Pulsed peak power

CW Voltage

Continuous-wave lasing1-µm thick, 7.5-µm devices exhibit

continuous-wave lasing

Threshold current Ith = 0.5mA, voltage Vth = 1.5-1.7Vslope efficiency = 30µW/mA, up to 10µW

(Pulsed regime: up to 100µW peak power)

-90

-80

-70

-60

-50

-40

-30

-20

1560 1580 1600 1620 1640Wavelength (nm)

Spec

tral

pow

er (d

Bm

)

0.9mA

J. Van Campenhout et al., "Electrically pumped inp-based microdisk lasers integrated with a nanophotonic silicon-on-insulator waveguide circuit" Optics Express, May 2007

20


Temperature dependence

0

100

200

300

400

400 600 800 1000 1200 1400 1600 1800current [uA]

pow

er [a

.u.]

“Laser emission up to 70°C”(pulsed operation)

T=10T=10°°CC

T=20T=20°°CCT=30T=30°°CC

T=40T=40°°CC

T=50T=50°°CC T=60T=60°°CC

T=70T=70°°CC

D = 6µm

1567

1568

1569

1570

1571

1572

0 10 20 30 40 50Tamb [°C]

peak

wav

elen

gth

[nm

]

1Kpm86 −≈dTdλ

14 K012)( −−≈InPdTdn

13 K017)( −−−≈BCBdTdn


Fit to experimental data

Model can be fitted to pulsed experimental data, assuming:uniform injection: injection efficiency =0.36x0.7=0.25coupling loss = 3cm-1 (simulation)tunnel-junction p-doping Na = 2x1018cm-3

(design target Na = 2x1019cm-3, SIMS analysis: Na ~ 8x1018cm-3 )fitted scatter loss = 8cm-1 (passive ring resonators: 7-13cm-1)

Consistent fit, except for tunnel-junction p-doping and saturation effect

0 0.5 1 1.5 2 2.5 30

5

10

15

20

25

30

Current (mA)

Opt

ical

Pow

er (

µ W)

0

0.5

1

1.5

2

2.5

3

Vol

tage

(V)

pulsed data

CW data

21


Sources vs. modulatorsSource based approach

Conceptually simple

Direct modulation

No wavelength matching needed

High temperature operation ?

Integration process ?

Off-chip source + modulators

Simpler integration

Resonator wavelength sensitive to temperature variations

Power needed for modulators?

Off-chip source needed + fibrecoupling

Xu e.a., Optics Express Oct. 06


Full LinkDemonstrator die (contains 256 optical links)

detector III-V dielaser III-V die

200mm SOI wafer

7mm

9mm

120 Microdisklasers

120 DBRmicrolasers

264 Micro detectors(TU Eindhoven / Cobra)

Poin

t-to-

poin

tlin

ks

Poin

t-to-

poin

tlin

ks

FIB

RE

GR

ATI

NG

CO

UPL

ERS

Bro

adca

stlin

ks

FIB

RE

GR

ATI

NG

CO

UPL

ERS

22


Pulsed operation of the link

Detector not biased (0V), negligible dark current

Performance under pulsed operation:Threshold current < 700 µA & Slope efficiency ~ 1.1 µW/mADetector efficiency of 0.23-0.29 A/W.

Duty cycle = 8% Period = 1 µsmonitor grating

on-chip detector


CW operation of the link

Detector not biased (0V), negligible dark currentCW laser performance:Threshold current ~ 600 µA & Slope efficiency ~ 1 µW/mADetector efficiency of 0.27-0.59 A/W.Unstable output power above 1.5mA

Micro-disk is lasing in two directionsOutput direction varies in time + as functon of applieed voltage

23


SOI waveguide

SOI OpticalInterconnect

layer

ElectricalInterconnect

layer

Silicon transistor layer

microdetectormicrolaserIII-V material

On-Chip Optical InterconnectNext step: integrate photonic interconnect on CMOS

Through wafer-to-wafer bonding

Or: Above IC processing using amorphous silicon


OutlineIntroduction & specifications

The integration process

Electrically pumped microsources

Microdetectors

Full optical point-to-point link

Conclusion and outlook

24


Outlook & conclusionWe demonstrated:

Ultra-dense waveguiding< 2um pitch (waveguide-to-waveguide)

First electrically pumped micro-disk sources on silicon platform

500uA threshold current

Micro-detectors on silicon platform1.0A/W

Full point-to-point link

Fabrication using waferscale processesIn CMOS-pilot lineInP processing does not pose contamination problem


Outlook & conclusionWe still need to:

Improve source performance Towards 50uA threshold current – 10GHz modulation speed – 30% internal efficiencyThrough improved processingThrough improved device designImproved high temperature operation

Full fabrication in CMOS pilot-line

Integration with CMOS electronic driving circuit

Implement WDM-functionality

WADIMOSWavelength division multiplexed photonic layer on CMOS

EU funded project starting Jan ’08See you in 2011 …

λ1

λ2

λ3

λN

λ1,λ2 ... λN-1,λN

λ1

λ2

λ3

λN

λ1,λ2 ... λN-1,λN

λ1

λ2

λ3

λN

Single wavelength

Multi-wavelength sources

25


The photonics research group at INTEC/IMECP. Dumon, W. Bogaerts, G. Roelkens, J. Van Campenhout, J. Schrauwen, S. Verstuyft, L. Van Landschoot, J. Brouckaert, D. Taillaert, S. Scheerlinck, S. Selvarajan, K. De Vos, D. Van Thourhout, P. Bienstman, R. Baets

The Silicon Process division at IMECVincent Wiaux, Stephan Beckx, Johan Wouters, Diziana Vangoidsenhoven, Rudi De Ruyter, Johan Mees

PICMOS partnersJ.M. Fedeli, L. Di Cioccio (LETI) (molecular bonding, processing)C. Lagahe, B. Aspar (TRACIT) (planarization)C. Seassal, P. Rojo-Romeo, P. Regreny (CNRS-Lyon) (processing, epitaxy)R. Notzel, X.J.M. Leijtens (TU/e) (epitaxy)

ePIXnet Silicon Photonics Platform (IMEC+LETI) for organizing MPW runs on a a cost-sharing basis

Also for you ! See www.siliconphotonics.eu

Acknowledgements

Documents

A Photonic Interconnect Layer on Siliconphotonics.intec.ugent.be/download/ocs105.pdf · 1 A Photonic Interconnect Layer on Silicon Dries Van Thourhout – MNE ‘07 A Photonic Interconnect