A Manufacturing Technology Perspective of: Embedded … Manufacturing... · Bernd K Appelt Director WW Business Development April 24, 2012 A Manufacturing Technology Perspective of:

Bernd K Appelt

Director WW Business Development

April 24, 2012

A Manufacturing Technology Perspective of:

Embedded Die in Substrate

and

Panel Based Fan-Out Packages

© 2012 ASE Group. All rights reserved.

Table of Content

Definitions

Wafer Level Fan-Out Technology

Panel Level Fan-Out Technology

Panel Level Embedded Technology

Summary

1

© 2012 ASE Group. All rights reserved. 2

Emdedded Component Technology

WL Fan-out = eWLB = aWLP

PL Fan-out = aEASE+

PL embedded = aEASI


Emdedded Component Technology

3

Passive

componentDie / WLP Passive

component

Die

Passive


component

Die

Passive

component

Passive


component

Passive

component

Die

Passive


component

DiePassive

component

Passive

component

Passive


component

Passive

component

DiePassive

component

Passive

component

Ultimate Objective

Miniaturization of SiP

Die

Passive

component

Die / WLP Passive

Die / WLP Die

Die

DieDie

Passive

component

Passive

component

Passive

component

Die / WLP Passive Passive

Die / WLP Die

Die

Die / WLP

Die

Die / WLPDie / WLP

DieDie


WL Fan-out = eWLB = aWLP

Key attributes

Wafer Level process environment

Low CTE Mold Compound

Long term proven process technology ex WL molding

Yield > 99%

Design optimum when die designed for flip chip

Business Model: one stop shop

4


eWLB = aWLP Roadmap

Technology Item HVM Available 2012 2013 2014

Max. Package Size (mm2) 8X8 10X10 11x11 12x12 13X13

Mold / PKG Thickness (mm) 0.49/0.74 0.25/0.5 -- -- --

Ball Pitch/Size (mm) 0.5/0.3 0.4/0.25 0.3/0.17 0.3/0.15 --

RDL Trace

Width/Space (um)

20/20 15/15 8/8 6/6 --

Thickness (um)

7.4 10 10 12 --

Polymer Opening (um)

6.7 um Polymer

30 20 20 10 --

Number of RDL Layers 1 1 2 >2 --

Min. Die Pad Pitch (um) 70 55 55 45 --

Min. Die Pad Pass. Opening (um) 60 50 50 40 --

Multi Die Single die 2 dies 2 dies >2 with discrete passive

--


aWLP Technology Development

Small Die

Large Package

Thin Package

2D Multi-die

2D Multi-die w/ Passive

3D Double-sided

Multi-RDL

Fine Pitch Die

New Polymer for TC Enhancement

12” aWLP


aWLP Technology

2D Multi-die Passed Package & Board Level Testing on Std. structure

2 die 2D package OM in qual phase (Q1’12)

Minimum spacing between dies & at die edge are tested at 50 um

2D Active Die & embedded SMT Passives One die with SMT capacitor engineering build

0402 & 0201 capacitors are successfully put on Reconstitution wafers

2 die with one IPD engineering build

Capable of handling 4 um thick UBM IPD w/o mold flash using Std. adhesive (10 um glue layer), and with thicker adhesive can cover thicker UBM

8X8 2-Die Test vehicle 50µm Gap between Dies 50µm Mold Perimeter

SMT Capacitor & Die

Capacitor

Silicon

Die placement finished

Silicon

Capacitor

Debonding finished

IPD & 2 Die


8

aWLP 3D Double Sided

Two approaches for 3D aWLP are ongoing

• Through Mold Laser Via

High level of mold filler makes clean laser via difficult. Development ongoing for

optimum process.

Rough sidewall challenges metallization of via.

• Embedded TSV Die for 3D Feed through

Embeds small TSV die in mold compound as a 2D SBS aWLP for 3D

interconnectivity (Q2’12).

14x14 one die with two TSV die eTSV die image

TSV hole


aWLP Technology

MultiLayer RDL

Enables RDL layout for high density chips

Five RDL designs for evaluation

Fine Pitch Die Pads & Lines/Spaces

RDL trace line/space (Qualification phase)

THB (leakage measure) TV 7.5x7.5 mm

RDL L/S: (1) 8/8; (2) 10/10; (3) 12/12; (4) 15/15

THB1000 (Q2’12)

Current leakages on RDL 8/8 um meet the criterion (I < 10-10A by 5V input)

Finer pad pitch and polymer opening

Testing capability of current process flow and material sets for pad pitches below 50µm & polymer opening achieved 10 um

OM – 8/8 SEM – 8/8

Achieved L/S 8/8 um.

40 µm Pad pitch


PL Fan-out = aEASI+

Key attributes

Panel Level process environment

Low CTE laminate + ABF

Cu terminals on die

Long term proven process technology ex embedding

Design based on flip chip and/or wire bond die

Test as module as usual

Yield > 90%

Business Model: multiple stop shop

wafer to substrate mfg to OSAT

10


ASE Fanout Panel Development Panel Fanout

ASE is developing a panel process version of fanout packaging

Focusing on lower pin count, Higher Power fanout packages

Initial Single Die prototypes passed all package & Board level testing

2D 2-Die PFO in development

3D Double sided PFO in concept design phase

11

30µm Laser Via


8x8 mm package; 3x3x0.15 mm internal chip – 196 I/Os; 200 um bump pitch; 400 um ball pitch

Structure A Passed standard package level reliability

(MSL3+HAST+TCT+HTST)

Structure B Passed standard Package level reliability

Substrate FO Prototype Builds

Blind via dia. = 70 um

RDL L/S = 20/20 um Solder resist ~18 um

Prepreg as

encapsulation

~160 um 2L substrate

(~100 um possible)

RDL L/S = 20/20 um

Chip

Substrate


Dielectric Lamination > Vacuum Lamination

Via Formation / Desmear > Laser Drill

> Roughen Dielectric Surface

Patterning Formation > Seed Layer > Photo-Litho

> Cu Plating > Stripping/Etching

Solder Resist & Surface Finish > Pretreatment > Solder Resist > Exposure

> Development > SR Curing > Surface Finish

Ball mount & Saw

After Solder Resist

X-section of Package

RDL Pattern

Process Flow – Structure A


Process Flow – Structure B

Substrate

Chip

Substrate

Chip

Bare substrate > Strip format

> 2L , 1/2/1, 2/2/2

Substrate

Chip Placement > Flip chip bonding

> Reflow

Chip Encapsulation > Prepreg routing

> Strips reconstitute into ¼ panel or

full panel

> Prepreg stacking -> lamination

> Route into strip format

¼ panel Strip

510mm

405

mm

Prepreg

Substrate

Ball mount & Saw > Ball placement & reflow

> Saw into unit

Chip

Substrate

¼ panel, after prepreg stacking

Substrate

Chip Prepreg

X-section of 1-package


2-die Package

Package Specification •Package size: 8x8 mm

•Die size: 3.1x3.1 mm x 2

•Package THK: 400 um

•Die THK: 150 um

•Die I/O: 196

•Die pad pitch: 200 um

•Ball pitch: 400 um

•L/S: 20/20 um

•Blind via diameter: 70um

X-section of 1 package

Chip1 Chip2

Interconnection of RDL to

Chip thru blind via

Top view of RDL

pattern: L/S 20/20um

Solder resist

opening for ball

mount


2-die aEASI+


Double-sided Fan-out Package

Core layer Mechanical drill Cu stud formation Pattern formation

Dielectric lamination Adhesive dispensing

& die placement Blind via formation Pattern formation

Solder Resist

Process Flow

Ball mount & Saw

Technology extension for 3D or multi-die package application • Package on Package application

• Multi-chip or component assemble on package (MCM)

Layer1

Layer2

Layer3


Package Quality - Reliability


•Die size: 3.1x3.1 mm


•Die THK: 150 um

•Die I/O: 196

•Die pad pitch: 200 um


Reliability condition Lot1 Lot2 Lot3

Pre-condition

- T/C cycle: -55 ℃ ~ 125 ℃, 5X

- Baking: 125 ℃, 24hrs

- MSL3: 30℃, 60% RH, 192 hrs

- Reflow: 260℃, 3X

HAST

- 130'C/85%RH , 33.5 psig, 96/192

hrs

Passed Passed Passed

TCT

- -55 ℃ ~ 125 ℃

500/1000X Passed Passed Passed

1500X Passed -- --

HTST

- 150 ℃, 500/1000 hrs Passed Passed Passed

Inspection items: •Cosmetic inspection

•SAT

•Open/Short Test


Package Quality – Board Level Reliability



•Die THK: 150 um

•Lead count: 180


Reliability item Condition Result

Drop Test 30 times

(JESD22-B111) Passed

Thermal cycle

-40 ℃ ~ 125 ℃,

500/1000/1500/2000X

(JESD22-A104C)

Passed

Inspection items: •Cosmetic inspection

•Open/Short Test


Package Quality – Unit Warpage

•Package size : 8x8 mm

•Die Size : 3.1x3.1 mm

•Package THK : 430 um

•No solder ball

The maximum warpage of fan-out package is around 52 um, convex, at 260 ℃ – Factor: reflow times, 3x & 6x

– Test flow: reflow 3 or 6x -> warpage measurement (shadow moire)


Technology Attributes 2012

2013 2014 2015 Standard Advanced

Die

Die I/O pitch, um 150 130 100 80 80

UBM Cu THK Cu pad, 7um Cu pad, 7um Cu pad, 7um Cu Pad, 5um or Al Pad

Pad Dia. 130 110 80 60

Die Thickness, um 150 125 100 75 50

RDL

LW/LS, um 25/25 20/20 20/20 15/15 12/12

Via/Land 70/130 60/110 50/80 30/60 30/60

Pad(RDL), um 130 110 80 60 60

Ball Pitch, mm 0.5 0.4 0.4 0.35 0.3

Ball Pad, um 310 300 290 250 250

Solder

Resist

SRO, um 250 250 250 220 220

SRR, um +/-30 +/-25 +/-20 +/-15 +/-15

Surface Finish OSP, ENIG, ENEPIG

Solder Ball Lead-free

Carrier Thickness, um 200 150 100 100 60

Package Thickness, um (no solder

ball) 480 400 330 300 210

Panel Level Fan-out: Roadmap


PL Fan-out = aEASI

Key attributes

Panel Level process environment

Low CTE laminate

Cu terminals on die

Long term proven process technology ex embedding

Design based on flip chip and/or wire bond die

Test as module as usual

Yield > 90%

Design software for embedding lacking

Substrate test of embedded lacking

Extended Cycle time

Business Model: multiple stop shop

wafer to substrate mfg to OSAT 22



aEASI Structures - Structure & Feature

LGA Type BGA Type

Feature

Thin package thickness (< 0.4mm)

Excellent electrical performance

Double side cooling for better thermal performance


SiP Module - Embedded Die Substrate - Structure & Features

Features

Yield enhancement by Know good substrate.

Prefabricated known good substrate, before die / component embed, substrate inter-connection and out layer build-up process.

• High density circuit / multiple layer design in base substrate

• The base substrate manufacture by existing panel type production line.

• Following component embedding and out layer processing at embedded line.

Enable highly integration 3D PKG solution with assembly and SMT technology.


a-EASI


a-EASITM

MOSFET a-QFN ( ASE TV1) Project Status Run3 Sample Build----Done

MOSFET QFN ( ASE TV2) Project Status Run1 Sample Build----Done

MOSFET ( ASE TV5) Project Status Run1 Sample Build----Done

TV1/TV2/TV5 Reliability Test Schedule


Chip Cu Bump Cu Bump

Bump Pitch

(A)

(A)

(B)

(B)

(C) (D) (E)

(F)

(F)

(C)

(D)

(E)

(F)


a-EASITM PKG Roadmap

2012 2013 2014 2015

BGA Type

MCM

LGA Type

SiP Module

Passive


component

Die

Passive


component

Die

Passive

component

Passive


component

Passive

component

Die

Die / WLP

Die

Die / WLPDie / WLP

DieDie

Passive


component

DiePassive

component

Passive

component

Passive


component

Passive

component

DiePassive

component

Passive

component

Die

Passive

component

Die / WLP Passive

Die / WLP Die

Die

DieDie

Passive

component

Passive

component

Passive

component

Die / WLP Passive Passive

Die / WLP Die

Die

2016


Summary

Embedded Technology bursting into market

Standardization needed

aWLP – aEASI+ - aEASI solutions with distinct resolution and cost profiles

ASE can offer one stop shopping for all three soltuions

30


Thank You

www.aseglobal.com

Documents

A Manufacturing Technology Perspective of: Embedded … Manufacturing... · Bernd K Appelt Director WW Business Development April 24, 2012 A Manufacturing Technology Perspective of: