A Low Power High-Side Current SenseSAR ADC for Automotive Applications

Stefan Dietrich, Sebastian Strache, Jan Henning Mueller, Lukas Lohaus, Ralf Wunderlich, and Stefan Heinen

Integrated Analog Circuits & RF Systems Laboratory

RWTH Aachen University, Aachen, Germany

Email: IAS@rwth-aachen.de

Abstract—Direct current measurement is one of the mostimportant control characteristics for DC-DC converters. Thissensitive method is used for current control of converters, whichis much faster and more accurate than voltage control. Unfortu-nately, the sensitivity of the current measurement is also its majordrawback. Especially in automotive applications, electromagneticinterference of the increasing number of electrical appliancesseverely degrade the performance of analog signal processing.Having proven to be more robust and error-prone, digital signalprocessing has to be preferred. This work presents a universalhigh-side current measurement at automotive battery voltagelevels up to 24V with direct analog-to-digital (A/D) conversionin a 180 nm technology. The A/D converter has been realizedas 9 bit successive-approximation (SAR) ADC, with a samplingrate of 10MS/s to detect DC-DC converter switching frequenciesabove 1MHz. The combined circuit area of 0.2mm2 dissipatedless than 2mA at 1.8V supply voltage. Simulation results of theextracted layout reflect the transient waveforms of a DC-DC LEDdriver during continuous and discontinuous conduction mode.

I. INTRODUCTION

In todays automotive electrical applications, battery powermanagement attains higher importance as a direct result of therapidly increasing number of on-board functionality. Modernhigh- and mid-class cars not only introduce driver supportelectronics like ABS, ESP or fuel consumption monitoring, butalso an increasing number of energy-intensive direct controlof critical applications. These applications include e.g. radar,engine performance, or driver information & entertainment[1]. The trend towards a more and more automatic driver andinformation exchange within the car open up development oftwo different fields to be combined into one genre. Typicallyoperating at a 12V car battery voltage, electronic componentsfirst have to withstand voltages higher than 60V for reliableactivity [1]. To keep up with the future car information tech-nology, second, smaller technology nodes and higher systemintegration are desired to keep the costs. This leads to thecombination of high voltage devices in a sufficiently smalltechnology node to use superior digital control on chip, asit is typically presented in modern 130 nm or 180 nm CMOStechnologies. Besides of that, direct current measurement forcurrent control in many DC-DC converters have proven to bemore accurate and faster than their voltage control counter-parts.

Fig. 1 shows a general principle of a high-side currentmeasurement technique across a shunt resistor, as it is widelyknown in literature.

Rshunt

HSCS

Ctrl

PowerStage

RloadCVin

Integrated Circuit (IC)

Fig. 1. Principle of high-side current measurement.

High-side current sense techniques as stated in Fig. 1normally are purely analog in literature [2]–[4] and havesuperior characteristics. They intend to drive analog-to-digitalconverters (ADC) [2], but the drawback of these systems aretheir big technology node ≥ 0.6 μm [2]–[4]. Suitable ADCsfor the suggested high-side current senses have not beenpresented and the big technology node prevents them to befully integrated with digital signal processing on one chip.Even if a second ADC integrated circuit (IC) is used, enormouseffort is necessary to realize the ADC, which is capable ofquantizing the high-side current sense full scale range. Fromsystem perspective, it then remains unclear, if this amount ofsystem complexity and resolution is desirable to control a DC-DC converter, or if a comparatively less accurate, integratedhigh-side current sense with its ADC topology achieves thesame results.

Hence, current sensing and analog-to-digital conversionstay separated and multi-chip solutions are the result. Thisfact is a disadvantage when it comes to a reduction of theform factor and costs.

By combining direct current measurement at battery volt-age levels and a small digital integration, the control loopis intended to be digitized as early as possible in the signalchain to avoid coupling effects from the electrically pollutedautomotive environment. Digital signal processing is widelyknown to be more robust and error-prone than analog signalprocessing and is preferred as soon as system complexity rises.

II. PROPOSED SYSTEM ARCHITECTURE

The proposed system architecture is illustrated in Fig. 2.The topology consists of an active divider at the input, twoseries amplifier stages, the capacitor array of the successive-approximation (SAR) ADC and the digital control domain.

RBig

RBig

Rsmall

Rsmall

Mdiv

MdivOP1 Vcm

Vfb1

Rfb11

Rfb12

R

R

Rvar

Rvar

VcmVfb2

Vfb2

Rfb21

Rfb22

OP2 Comp

Vinp

Vinn

Vcm

VcmVDDVSS

VDDVSS

S

S

C0 C1 Cn-1

C0 C1 Cn-1

LSB…MSB

DIGITAL

Select negative Ref / Caps

Select positive Ref / Caps

Input Divider SAR Cap-Bench2x Amplifier Stages Digital Domain

OP1

V+

V-

Vcm

Fig. 2. High-side current sense SAR ADC architecture.

An external shunt resistor Rshunt of choice for currentmeasurement is placed externally and the voltage across theresistor is sensed at nodes V+ and V−. The high ohmicresistive divider RBig and Rsmall converts the high voltagebased current signal to the low voltage 1.8V domain. Thedifferential resistive feeback Rfb11 and Rfb12 generates thefeeback voltage Vfb1, which is compared to the common-modevoltage Vcm = 0.9V by the operational amplifier OP1. Thecontrol of the two transistors Mdiv prepares the differentialcurrent signal between V+ and V−, so that the current signalis centered at Vcm.

Two differential amplifier stages are used for amplificationand linearization of the current signal, so that it is accuratelystored on the SAR ADC capacitor bench. The gain of thedifferential amplifiers OP2 of each stage is digitally controlledby the resistive network R and Rvar and are independentof each other. Rvar is realized as parallel circuit of eightdifferent resistor values. The dimension of the different Rvar

is logarithmical, so that the gain of each amplifier stage canbe changed linearily by ±1 dB steps. Additional common-mode feedback with OP1 and Vcm is included in the amplifierstages for common-mode correction. In the feedback loop,the differential voltage feedback Vfb2 of Rfb21 and Rfb22

is compared to Vcm, as it is presented in the input divider.For normal operation, amplifier stage 1 is designed to operatewith high gain and low input offset, whereas amplifier stage 2operates highly linear with high slew rate and high current tocharge the capacitors of the SAR ADC.

The capacitances of the SAR ADC are realized as fourlayer fringe capacitor array with minimum capacitance valueC0 = 16 fF. The designed 8 bit resolution of the ADC results ina total load capacitance of around 4 pF per single-ended outputand 8 pF in total. Based on the knowledge of the maximuminput current range of the signal processing structure, thedifferential gain amplifiers are digitally controlled to provideequal signals at Vinp and Vinn at the input of the capacitor

bench for current signals half of the designed maximuminput current. For lower input currents, the negative outputof the analog devices gets higher than the positive outputwith decreasing currents. For higher than half-rated currents,operation is vice versa, so that the positive output gets higherthan the negative output. With this method, an additional ninthbit can be used as sign bit to increase the ADC resolution.To realize the signed output of the SAR ADC, the referencevoltages VSS and VDD of the positive and negative capacitorbench can be inverted.

The SAR comparator is a latched comparator, which holdsthe sampled value for digitalization during process, until it isreseted and updated again by the main 100MHz clock. Thesampling time of the SAR ADC is typically one clock cycle,which equals to 10 ns. With regard of the 9 bit ADC resolution,this results in a theoretical conversion speed of the circuit of

ts = (9 + 1) · 1

100MHz= 100 ns, (1)

which is equivalent to

fs =100MHz

10= 10MS/s. (2)

To improve the sampling accuracy of the high-side currentsense structure, the sampling time of the SAR ADC can beincreased digitally to a maximum of four clock cycles, whichrelaxes the requirements of the amplifiers. The settling timeof the differential amplifier stages is then decreased from amaximum of

tsettlemin =|Vsupply − Vcm|1 clock cycle

=0.9V

10 ns= 90V/μs

(3)

to tsettle,max = 22.5V/μs. To charge the SAR ADC capacitorbench during one clock cycle, the required minimum current

TABLE I. CHARACTERISTICS OF THE COMMON-MODE AMPLIFIER

OP1.

Parameter OP1

ADC 48.8 dBf−3 dB 43.5 kHz

ft 7.3 MHzPhase Margin 67.2◦

Gain Margin 29.7 dB

PSRR @ 100 kHz 31.5 dBPSRR @ 1 MHz 23.3 dB

VDD 1.8 VIDD 5 μA

VDD

IDCVinp Vinn

Vout

Cc

M1 M2

M3

M4

Fig. 3. Common-mode amplifier OP1.

in the output stage of the second differential amplifier iscalculated to

IC(t) =CloaddV

dt= Cload · |Vsupply − Vcm|

1 clock cycle

=8 pF · 0.9V

10 ns= 720 μA,

(4)

which explains the high current consumption of the high-side current sense of around 2mA at 1.8V. Longer samplingtimes decrease the required current in the output stages of thedifferential amplifiers and increases the sampling accuracy, butat the expense of sampling frequency.

III. DESIGN IMPLEMENTATION

A. Common-Mode Amplifier

The common-mode amplifier OP1 is visualized in Fig.3. The amplifier consists of a single-stage PMOS differentialinput pair M1 and M2 with cascoded NMOS current mirrorload M3 and M4. The cascoded load increases the outputresistance of the topology, so that the gain of the OP isincreased. The characteristics of the common-mode amplifierOP1 are summarized in Table I.

From Table I it can be seen that the DC gain ADC =48.8 dB of the one stage amplifier is comparable to a twostage amplifier. Due to the small load capacitances the currentconsumption of OP1 IDD = 5 μA is quite low, so that thecontribution to the systems’ power dissipation is negligible.

Capacitor Cc is used as high frequency short and asfrequency compensation to increase the phase margin of thecommon-mode control loop of the input divider and of the twomain amplifiers.

Vcmfb

VmainVload2Vload2

Vload1 Vload1

Vcmfb

VdivpVdivn

IcnIcp

Voutn Voutp

VDD

M1 M2

M3 M4M5 M6

M7 M8

Fig. 4. Differential gain stage of OP2.

TABLE II. PROPERTIES OF THE AMPLIFIER STAGE OP2.

OP2Parameter Cload = 8 pF Cload = 0

Closed Loop Gain ADC 26.1...32.9 dB 26.1...32.9 dBf−3 dB 2.86...5.2 MHz 38.5...39.2 kHz

ft 34.5...44.5 MHz 0.81...1.57 MHzPhase Margin 22.6...60.9◦ 61.5...84.3◦

Gain Margin 11...19 dB 50...53.3 dBSlew Rate 90 V/μs 90 V/μs

CMRR 75.4 dB 75.4 dBPSRR @ 100 kHz 50 dB 50 dBPSRR @ 1 MHz 34.7 dB 34.7 dB

VDD 1.8 V 1.8 VIDD 1.1 mA 1.1 mA

B. Differential Gain Amplifier

Fig. 4 shows the differential gain stage of the main ampli-fier OP2. With a differential NMOS input pair M1 and M2,the first stage operates on a PMOS current source load M3 andM4 for high open loop gain. The input pair features additionaldigitally controlled offset correction, which is represented bythe two controlled current sources Icp and Icn. With thismethod the divided input signal is amplified and centered atVcm. The current sources Icp and Icn are driven such thateither Icp supplies current to the left side and Icn draws thesame current at the right side of the differential input stage, orvice versa [5]. Special care has to be taken to the dimensionsof current supplied or drawn by Icp and Icn, or otherwise thetwo current sources will overwrite the input signal at Vdivn

and Vdivp.

The output M5 and M6 of the first stage of OP2 operateson a current source load M7 and M8 and additional common-mode feedback with OP1 is applied at to M5 and M6. TableII summarizes the properties of the differential amplifier stageOP2.

The differential output stage of OP2 has to provide highoutput current and high bandwidth, so that the load capacitorbench of the SAR ADC with 4 pF per single output is chargedin one period of a 100MHz clock. For system stability, it hasto be taken into account that two different configurations haveto be considered. During the sample period, the SAR capacitorbench is directly connected to the second amplifier stage. Inthe conversion period, the capacitors are disconnected from theamplifier stage, so that OP2 runs without load capacitance.A frequency compensation, which takes the charge perioddependent load capacitors into account has therefore beenimplemented. Fig. 5 shows the Bode diagram of the frequency

-60

-40

-20

0

20

40

Gai

n [d

B]

SAR connectSAR disconnect

10 k 100 k 1 M 10 M 100 M 1 G

-100

0

100

200

Frequency [Hz]

Phas

e [d

eg]

SAR connectSAR disconnect

30

34.8 MHz

21.5°

1.3 MHz

71.3°

Fig. 5. Load capacitor dependent Bode diagram of OP2.

Vmain

Vload2Vload1

VDD

IDC VbpVbn

M2

M3

M1

M4

M5

Fig. 6. Differential gain amplifier biasing of OP2.

response of OP2.

The blue curves represent the Bode diagram while the SARis in the sample period. The dashed red curves indicate theconversion period, when the capacitor bench is disconnected.When the ADC is in the sample period, the capacitor benchhas a low-ohmic connection to the output of the differentialamplifier, so that the resulting RC product is low and thedominant pole is in the higher frequency domain. This resultsin a bandwidth of ft ≈ 35MHz for the amplifier. Theachieved 21.5◦ indicate the frequency compensation issue.When the ADC is in the conversion period, the capacitors aredisconnected and the RC product of the dominant pole pairis high. Hence, the dominant pole is in the lower kHz range,so that the frequency response of the amplifier is similar to anintegrator. The bandwidth turns out to be low and frequencycompensation is not a problem. The transient settling of theamplifier during the conversion period is not harmful for thestability of the amplifier, as there are multiple clock cyclesbefore switching to the sampling period again.

For completeness, the bias circuitry of the differential gainamplifier is illustrated in Fig. 6. Running at IDC = 10 μA biascurrent, the bias network is a cascade of current mirrors to setthe right operation voltage for the amplifier. The voltages Vbn

Comp

Vinp

Vinn

Vcm

Vcm

S

S

C0 C1 Cn-1

C0 C1 Cn-1

LSB…MSBVcm

VDDVSS

VDDVSS

Fig. 7. Basic CR SAR ADC topology.

VDIG

Vcmp Vcmn

Ven

Ven Ven

VDD

M1 M2

M3

M5

M4

M6

Fig. 8. SAR ADC comparator.

at M2 and Vbp at M3 represent the bias levels of the digitallycontrolled offset correction. The global current source of theamplifier differential input pair is biased with the input diodeM1 level Vmain, whereas the operating points of the two loadcircuits Vload1 at M4 and Vload2 at M5 had to be separated asa result of the transistor geometry and used operating points.

C. Successive-Approximation Analog-to-Digital Converter

The basic topology of a charge redistribution (CR) SARADC is given in Fig. 7, which has first been mentioned in [6].

During the charge phase, the differential input signalVinp − Vinn is connected to the top plates of the positive andnegative capacitors, respectively, while the bottom plates areconnected to the common-mode voltage Vcm. The differentialinput signal is sampled and held, so that no further S&Helement is necessary. During the conversion phase, the topplates of the positive capacitors are connected to VDD, whilethe top plates of the negative capacitors are connected to VSS .The bottom plates are open connection, so that the storedcharge on the capacitors is evaluated at the input of the SARcomparator [7].

The comparator of the proposed SAR ADC, which canbe found in [8] is constituted in Fig. 8. The input voltages

TABLE III. PARAMETERS OF THE SAR ADC.

Parameter OP1

Resolution 8 + 1 bitC0 16 fFCLK 100 MHz

# Unit Cells 256 + 256Ctot 4 pF + 4 pF

Vcm 0.9 VVDD 1.8 V

Vcmp and Vcmn at the NMOS input pair M1 and M2 representthe charge of the positive and negative capacitor benches. Thevoltage Ven denotes the clocked enable signal with which thecomparator samples the actual input of the capacitor-benchduring ”on” time. When Ven is deactivated, the comparatorholds the sampled value with the cross-coupled latch inverterstructure M3 to M6. The latched signal is amplified andbuffered by additional inverter stages, before VDIG is sampledin the digital domain. The basic design parameters of the SARADC are summed up in Table III. The capacitor unit cell equalsto C0, which represents one least significant bit (LSB). Thehigher order bits are calculated by binary weighting of C0,so that the most significant bit (MSB) equals to 128·C0 perdifferential capacitor bench. The useage of unit cells opensroom for energy saving techniques, like capacitor splitting forthe MSB, which has been implemented.

IV. PERFORMANCE EVALUATION

The high-side current sense CR SAR ADC topology hasbeen implemented in a novel DC-DC LED driver and aperformance evaluation has been done with a converter currentof 0...1A [9]. The SAR current range has been set to -50...950mA, so that the sign bit toggles at 450mA. Thismethod avoids ADC bit overflow at both boundaries, givesreasonable overcurrent protection and compensates for the notideal rail-to-rail voltage operation of the differential amplifiers.The (external) sense resistor has been chosen to 100mΩ.With a 8+1 bit resolution, approximately 4mA correspond to1LSB, which is equivalent to a voltage drop of 400 μV acrossthe sense resistor. The transient performance of the high-sidecurrent sense for a DC-DC converter in continuous conductionmode (CCM) is illustrated in Fig. 9. The upper part of Fig.9 shows the differental input voltage V+ and V− at theexternal sense resistor Rsense. The DC current in the CCMhas been set to 500mA, which equals to a DC voltage of50mV across Rsense. The current ripple of 200mA results ina peak current of 400...600mA and makes the sign bit toggle,as soon as the current drops below 450mA, which can beseen in the lower part of Fig. 9. The voltages VINP, VINN,and VCM illustrate the output voltage of the second high-side current sense differential amplifier. The glitches in thetransient behavior are the result of the discrete sampling of theSAR ADC capacitor benches. The differential voltage VINP -VINN is represented by the sampled conversion value output ofthe SAR ADC, which is constituted by continuous, ideal backtransformation to the analog domain. The conversion time ts isidentified to be 100 ns, what results in a sampling frequency of10MS/s for the ADC. The signal swing of the high-side currentsense SAR ADC is calculated by the maximum conversionvalue for both sign bit cases ”0” and ”1”. From Fig. 9 it can

0.05

0.1

0.15

0.2

0.25

Vol

tage

[V]

Conversion Value

2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4"0"

"1"

Time [μs]

Sign Bit

9

9.02

9.04

9.06

Vol

tage

[V]

V+V-

0.7

0.8

0.9

1

1.1

Vol

tage

[V]

VINPVINNVCM

Bit

Fig. 9. Transient performance in converter CCM of the high-side currentsense SAR ADC.

be seen that the achieved voltage gain in this case is

AV =20 log

(max (Conversion Value) | Sign Bit

ΔV+

)

≈ 20 log

(240mV + 40mV

20mV

)= 23 dB.

(5)

Fig. 10 shows the transient performance of the high-sidecurrent sense during discontinuous conduction mode (DCM)of a DC-DC converter. The alignment of Fig. 10 is equivalentto Fig. 9. During DCM, the peak current always stays below450mA, so that the sign bit remains ”1”. The plot of the signbit has therefore been neglected. However, it has to be takeninto account, that the peak current converges to 450mA whenthe sign bit is ”1”. This can be identified as the conversionvalue decreases from the maximum negative value. For currentvalues below 450mA and active sign bit, the output of thedifferential amplifiers VINN > VINP.

Table IV briefly sums up the performance key points ofthe signal chain and compares the results to prior publishedworks. In the introduction it is mentioned that a reasonablecomparison to other works is difficult to handle. Typicalcurrent monitoring architectures are presented as stand-aloneICs with outstanding characteristics with respect to a reducedintegrated solution with its adequate ADC. Nevertheless, itshould be mentioned, that the high-side current sense in thiswork offers serious advantages in size and performance, whichalso comes from the reduced technology node.

0.2

0.4

0.6

0.8

1

Vol

tage

[V]

Conversion Value

2 2.5 3 3.5 4 4.5 5 5.5 6

Time [μs]

9

9.01

9.02

9.03

Vol

tage

[V]

V+V-

0.5

1

1.5

Vol

tage

[V]

VINPVINNVCM

Fig. 10. Transient performance in converter DCM of the high-side currentsense SAR ADC.

TABLE IV. COMPARISON TO PRIOR WORKS.

Parameter [2] [3] This work

Technology 0.8 μm 1.5 μm 0.18 μm

Size 2.5 mm2 3.9 mm2 0.2 mm2

Stand-Alone IC Yes Yes No

VDD 2.8...5.5 V 1.5...28 V 1.8 VIDD 850 μA < 46 μA 2 mAVin 1.9...30 V 0...28 V 9...24 V

CLK —– —– 100 MHzCMRR —– > 90 dB 97.1 dBfs —– —– 10 MS/sGBW —– —– 35 MHzResolution —– —– 9 bit

Inpu

t Div

OP2 OP2OP1

OP1SAR

Bias

Fig. 11. Chip layout of the proposed architecture.

A chip layout is given in Fig. 11. The high-ohmic activevoltage divider is placed at the input to the left. The twoamplifier stages are placed mirrored. The analog part of thehigh-side current sense with the mentioned elements occupies250 μm x 580 μm = 0.145mm2. The CR SAR ADC occupies210 μm x 370 μm = 0.077mm2, which mainly consists of thedifferential capacitor benches.

V. CONCLUSION

This work presents an integrated low power high-sidecurrent sense for up to 24V. To increase the robustnessespecially in automotive applications, digital signal process-ing is preferred, so that a signed charge-redistribution (CR)successive-approximation (SAR) analog-to-digital (ADC) con-verter is introduced in the same technology. A combination ofamplification and linearization of a current signal informationacross an external sense resistor of choice beforehand realizesan ADC resolution of up to 9 bit with a system clock of100MHz, which results in 10MS/s. The input current rangehas been set to 0...1A, so that 1LSB correspond to 4mA,which offers sufficient resolution and speed for most DC-DC converter applications in this environment. The high-sidecurrent sense and the CR SAR ADC have been implementedin a 180 nm technology, which withstands voltages up to 60V.With a supply voltage of 1.8V, the topology occupies a chiparea of 0.2mm2 and draws a supply current of 2mA. Thetopology is designed for DC-DC converters with switchingfrequencies of more than 1MHz and has been implemented ascurrent monitor in a DC-DC LED driver for general lighting.

ACKNOWLEDGMENTS

This work has been funded within the ”Energy efficientand intelligent lighting systems” project by the ENIAC JointUndertaking (project ID: 270707-2) and the German FederalMinistry of Education and Research (FKZ: 16N11438, Sub-project: Erforschung von Elektronikbausteinen fur energieef-fiziente, intelligente Beleuchtungssysteme).

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