A Low-Power 9-bit Pipelined CMOS ADC for the front-end

electronics of the Silicon Tracking System

Yuri Bocharov, Vladimir Butuzov, Dmitry Osipov,Andrey Simakov, Eduard Atkin

National Research Nuclear University MEPHI

Outline• Motivation• Proposed ADC architecture• Power Reduction Techniques• Sharing of amplifiers and comparators• ADC clocking• Test results• Power Consumption• Conclusion

MotivationADCobjective:• Resolution: 7-9 bit• Sampling Rate : 10-20 MSamples/s • Power Consumption:10-20 mW

Typical ADC’s Power Consumption > 30 mW

Circuit Overview

Power Reduction Techniques

• Sharing of amplifiers of the adjacent stagesThe number of amplifiers reduced twice• Sharing of comparators the adjacent stages

The number of comparators reduced from 17 to 11• The capacitors of the first stages of a pipeline are

scaled down along a pipeline

Sharing of amplifiers• During the sampling

phase operational amplifiers are either in the offset correction mode or not used at all. If offset correction is not required, the amplifiers can be switched alternately between adjacent stages to be connected to the stage, which is in a residue estimation mode.

Sharing of comparators• The stages can share the

comparator because after latching of its output in flip-flop registers at the beginning of a sampling phase, during the rest of this phase, comparator is not active and therefore it can be used in the adjacent stage, which is in the residue estimation mode

a block-diagram of a circuitry that contains a differential comparator shared by the stages numbered as i and i+1.

Schematic diagram of the comparator• regenerative latch with a

built-in preamplifier, clocked by non-overlapped timing sequences.

• consummates current only at clock switch

• More then 30% of the total power consumption of comparators is reduced

ADC clocking• A latch signal of Comparator should

have a frequency twice the ADC sampling rate. It requires an extra low-power frequency-doubling block.

Proposed Frequency Doubler CircuitADC clocking scheme

Scaling technique

• The sampling capacitors of the first stages of the chain are scaled down along a pipeline.

The SHA and MDAC of the first stage use the capacitors of 0.8 pF, while the MDAC of the fourth and further stages use the capacitors of 0.25 pF.

Topology

• Technology UMC 180 nm • Area 0,4 мм2

Testing

ADC’s Performance

Power ConsumptionAmplifiers56%

Digital logic and Comparators 5%

Reference source 39%

• Total Power Consumption: 14 mW• Core Power Consumtion: 8.6 mW

Conclusion

• the proposed 9-bit ADC uses only 4 amplifiers and 11 comparators instead of 8 amplifiers and 17 comparators with the conventional pipeline architecture.

• The partial sharing of amplifiers in the first stages of a pipeline enabled to keep their accuracy

• The effective number of bits (ENOB) is 8.0• The core power consumption is 8.6 mW. It occupies of

an active area of 0.4 mm2.

Thanks for your attention