A Highly Reliable Digital Current Control using an

IEEJ Journal of Industry ApplicationsVol.3 No.4 pp.296–303 DOI: 10.1541/ieejjia.3.296

Paper

A Highly Reliable Digital Current Control usingan Adaptive Sampling Method

Aromhack Saysanasongkham∗Non-member, Masayuki Arai∗∗ Non-member

Satoshi Fukumoto∗∗∗ Non-member, Shun Takeuchi∗∗∗∗ Student Member

Keiji Wada∗∗∗∗ Member

(Manuscript received Dec. 20, 2013, revised March 20, 2014)

A sampling algorithm to immunize digital control power converters with triangular carrier waveforms against switch-ing noise is introduced. Many converter circuits employ a sawtooth carrier waveform; however, no optimal samplingmethod has been presented that avoids switching noise. As demonstrated by the experiments conducted in this research,there are cases where converter circuits are not correctly controlled and sample values are affected by switching noisevia current sensors or AD converters. As a result, the output is unstable and inaccurate thus reducing the reliability ofthe converter.

This paper proposes an adaptive sampling method for a digital control current-mode power converter circuit on anFPGA (Field Programmable Gate Array) with the PWM (Pulse Width Modulator) sawtooth carrier waveform. To avoidnoise overshoot and undershoot during the MOSFET’s switching process, the sampling timing of the AD converter isadaptively tuned according to the duty ratio of each switching cycle. We further introduce a random phase noisegenerator, to conduct simulations as realistic as practical experiments. We also present simulation and experimentalresults of the proposed methodology illustrating cases of successful noise avoidance. Thus, we verify that the proposedsampling method improves the reliability of power converter circuits.

Keywords: digital current control, PWM control, sampling method, reliability, sawtooth carrier waveform

1. Introduction

Digital controllers based on digital signal processors(DSP), micro-controllers for inverter circuits and DC-DCconverters have been widely used owing to their multi-functionality (1). Recently, these controllers are being used inhome appliances, electric vehicles, etc. Field ProgrammableGate Arrays (FPGAs) have been employed to control con-verter circuits and can be found in many other applicationsbecause the processing time is at least 10 times less than thatof DSPs (2)–(4). As a result, a converter circuit’s transient re-sponse and stability are improved.

In general, the output signals of current and voltage sen-sors in the inverter circuits are converted to digital signals byanalog to digital converters (ADC). And a synchronous sam-pling method is commonly applied to digitally control thepower circuit (5) (6). In this sampling method, the sample valueis taken one or two times per switching cycle synchronizing

∗ Graduate School of System Design, Tokyo MetropolitanUniversity6-6, Asahigaoka, Hino, Tokyo 191-0065, Japan

∗∗ College of Industrial Technology, Nihon University1-2-1, Izumi-cho, Narashino, Chiba 275-8575, Japan

∗∗∗ Faculty of System Design & Graduate school of SystemDesign, Tokyo Metropolitan University6-6, Asahigaoka, Hino, Tokyo 191-0065, Japan

∗∗∗∗ School of Science and Engineering, Tokyo MetropolitanUniversity1-1, Minamioosawa, Hachioji, Tokyo 192-0397, Japan

with the carrier. According to the sampling theorem, whenthe switching frequency is equal to the sampling frequency,an anti-aliasing filter is required before the ADC to elimi-nate the reactor current ripple. However, if the samplingfrequency is synchronized with the switching frequency andthe average current can be sampled, then the switching rippleturns into a hidden oscillation (7). If, in addition, the targetedcarrier waveform is known, the average current can be easilydetected (8). Therefore, several researches on digital controlof current-mode power converters without anti-aliasing fil-ters are reported. Such a scheme is also better for stabilitysince the use of anti-aliasing filter can influence the dynamiccharacteristics of current control.

However, the sample values may be affected by the switch-ing noise via the sensors and ADCs (9). As shown below, thesample values can be affected significantly when the duty ra-tio is extremely high or low. The switching noise, in this con-text, is an overshoot/undershoot voltage and a damped volt-age oscillation during the MOSFET switch-on and switch-off. Because the characteristic of the switching noise differsin each circuit and each environment, it is very difficult to de-sign an appropriate filter for a converter. Consequently, thereliability of the digitally controlled power converter may bereduced.

For digitally controlled power converter circuits, the ef-fect of switching noise on the ADC’s values is one of themost significant issues, and many researches have been pre-sented in the literature concerning this matter. For instance, a

c© 2014 The Institute of Electrical Engineers of Japan. 296

Digital Current Control using an Adaptive Sampling Method（Aromhack Saysanasongkham et al.）

sample noise reduction method using a reset integrator is in-troduced (10). The capability of computers currently availablehas enabled real-time digital feedback control of the PulseWidth Modulator (PWM) inverter. Furthermore, with the ex-tension to multi-rate sampling, by implementing digital con-trol circuits on the FPGA and others, the performance and therobustness of the converter circuits can be significantly im-proved (3) (11). Yokoyama et al. presented a high-speed multi-sampling method in a low carrier frequency to improve theperformance and enhance the robustness of such circuits (2).Another approach to cope with the sample noise introducedby the ADC is to implement analog low-pass filters (12). How-ever, it is uncertain how the noise may affect the control cir-cuit or which noisy path may surround the input lines. Fur-thermore, filters implementation introduces an additional costthat has to be considered and at the same time, it can prove tobe significantly space consuming (13).

As a promising strategy for a fundamental type of syn-chronous sampling method, an alternating-edge-sampling ispresented to improve immunity against switching noise (7).The sampling points are tuned based on the duty ratio to avoidnoise. However, only the sampling algorithm for a triangularcarrier waveform is presented. The sampling timing is tunedto either sample at the upper peaks or the lower peaks of thecarrier. Numerous applications also use a sawtooth waveformas a carrier signal for producing a PWM waveform (14)–(16). Thereliability of such applications may also be at risk, and thus,a novel sampling method for sawtooth carrier waveforms hasto be investigated.

This paper proposes an adaptive sampling method for im-proving the reliability of power converter circuits using asawtooth carrier waveform. The sampling timing is tunedadaptively and sample values are selected such that they arenot affected by the switching noise. In particular, the samplevalues are taken adaptively based on the duty ratio. For thereasons mentioned above, an anti-aliasing filter is not imple-mented in this research. Because the switching noise cannotbe easily characterized to design a proper filter, this paperproposes a sampling method that avoids the effect of switch-ing noise without any filter.

First, the vulnerabilities of an undefended samplingmethod are exposed in a pilot study, in which a digitally con-trolled current-mode power converter is implemented on anFPGA. Second, the proposed sampling method is applied tothe above converter in a simulation that uses the parametersobtained in the pilot study. To simulate the switching noise,a random-phase noise generator is introduced. It allows tosimulate switching noise as closely as possible to the real en-vironment. As a result, the simulator can reliably replicateproperties of practical converter circuits. The simulation re-sults in this paper, demonstrate that the effects of real life con-verter circuits can be replicated accurately, and that the pro-posed method can effectively avoid the switching noise. Fi-nally, we present an implementation of the proposed methodon an actual FPGA-based digital control current-mode DC-DC converter, with a PWM sawtooth carrier waveform. Ex-perimental results are included to validate the effectivenessof the proposed method.

Fig. 1. Digital control current-mode power converter

Fig. 2. PWM feedback control diagram

2. Digital Control Current-mode Power Con-verter

This research utilizes an FPGA-based digital controlcurrent-mode power converter with a PWM sawtooth carrierwaveform as a target circuit. The FPGA board is a CycloneII with a parallel ADC for sampling the feedback current (17).In related works, a switching frequency of less than 20 kHzis used for the current control converters implementing thesawtooth carrier waveform (14)–(16). In this paper, the switch-ing frequency of the target circuit is set to 20 kHz and so isthe sampling rate. Hence, one sample will be taken in eachswitching cycle. The clock frequency of the controller circuitis 10 MHz. One switching cycle, T , is divided to 500 clocks,(0th to 499th). The supplied parameters are: Vin = 300 V, L =14 mH and R = 40 Ω, as depicted in Fig. 1.

The duty ratio of the converter circuit is controlled by thePWM feedback control. The PWM signal in each cycle is de-termined by the sample value from its previous cycle on thebasis of the output current and the reference current (18). ThePWM feedback control is implemented as shown in Fig. 2.The dashed line shows the processes that are executed withinthe FPGA. Because the computational performance of theFPGA is very high, the calculation can be executed in a fewclock cycles, which corresponds to a small percentage of thesampling interval.

Firstly, an error current ΔI is calculated by subtracting thereference current from the output current. Accordingly, theerror current is multiplied by a constant gain Kp, where

Kp =K

Vtri=

64300= 0.213. · · · · · · · · · · · · · · · · · · · · · · · (1)

Finally, further calculations, as shown in the PWM feedbackcontrol diagram, are executed in order to complete the currentfeedback control loop.

Meanwhile, the transfer function of the control system canbe derived as follows.

297 IEEJ Journal IA, Vol.3, No.4, 2014


Fig. 3. Switching noise components when the MOSFETis turned on and off

Fig. 4. Sampling Method to detect average sample valuewith PWM sawtooth carrier

I∗out(s)Iout(s)

=K Vin

Vtri

R + K Vin

Vtri

1

1 + LR+K

VinVtri

s. · · · · · · · · · · · · · · · · · (2)

Given Vin = Vtri = 300 V, and K = 64, the 1-A step responseis

Iout(t) =K

R + K(1 − e−

R+KL t) = 0.615(1 − e−9035t).

· · · · · · · · · · · · · · · · · · · · (3)

The synchronous sampling method is commonly appliedto digitally controlled power converter in various applica-tions (19). However, as shown in Fig. 3, the output current andvoltage Vd are corrupted by switching noise. Hence the sam-ples may be affected by the switching noise.

Since no filter is used in this paper, in order to correctlycontrol the power converter and detect the average current,the current has to be sampled at the center point of either theswitch-on or switch-off, as shown in Fig. 4.

Initially, the synchronous sampling method is applied tothe target circuit to verify the cases affected by the switch-ing noise. In this verification process, two experiments areconducted and in each experiment, the sample is taken differ-ently, as shown in Fig. 5. In the first experiment, the samplevalues are taken at the center point of the switch-on to detectthe average current. In the second experiment, the samplingsare taken at an arbitrary point, the 50th clock cycle of theswitching cycle, synchronously. In each experiment, the out-put current Iout is observed.

Figure 6 shows the result of the first experiment. Since

Fig. 5. Sampling timing for each experiment to verifythe vulnerability of the converter circuit

Fig. 6. Experimental result when sample values aretaken at the center point of the switch turned-on

Fig. 7. Experimental result when sample values aretaken at an arbitrary point (50th clock)

the converter successfully eliminates the effect of the switch-ing noise, the output current is expected to be very close toits theoretical value. However, because the duty ratio of theconverter circuit is extremely low, at 8.2%, the sample valuesare affected by the noise resulting in an inaccurate output cur-rent. Figure 7 shows the result of the second experiment, inwhich the sample values are affected by the switching noise.The waveform obtained shows an unstable, fluctuating outputcurrent.

The experimental results confirm that when the duty ratio isvery low the synchronous sampling method is affected by theswitching noise. This, however, also implies that the same ef-fect is present when the duty ratio is very high. Sample valuescan still get affected by noise when they are taken at a staticpoint, especially when the duty ratio changes. Therefore,



Fig. 8. Flow chart of the proposed method

without a proper sampling methodology, the reliability of theconverter circuit is at risk. To enhance it, a countermeasurefor the effect of noise on the sampling method with sawtoothcarrier waveform should be investigated.

3. An Adaptive Sampling Method

In this paper, an adaptive sampling method for improvingthe reliability of converter circuits using a sawtooth carrierwaveform is proposed. As mentioned earlier, the duty ratioin each cycle is decided on the basis of the information fromits previous cycle. In other words, by using the informationfrom the controller of the converter, the switching timing ofthe MOSFET can be exactly known. Thus, by leveragingthe fact that the presence of noise can be timed accurately,we can adaptively tune the sampling times to avoid noise atturned-on and off of the MOSFET.

Figure 8 illustrates the flow of the proposed method. Fun-damentally, the sampling times are tuned on the basis of theduty ratio. As shown, the output current is initially sampled.Secondly, the sampled current is used for the current con-trol and the duty ratio is calculated. In the proposed method,this calculation result of the duty ratio is used to calculate thesampling time. If the duty ratio is over 50%, then the sam-ples are taken at the center of the turn-on phase. On the otherhand, if the duty ratio is below 50%, the samples are taken atthe center of the turn-off phase.

Figure 9(a) shows where the samples are taken when theduty ratio is over 50%. The sampling point for the switchingcycle Tn, had already been decided during the switching cycleTn−1. Similarly, the sample value taken within the Tn cycle,determines the duty ratio of the pulse at switching cycle Tn+1.Hence, the times when noise is generated can be accuratelyestimated, and the samples are selected accordingly to avoidit. Figure 9(b) shows where the sample values are taken whenthe duty ratio is under 50%.

The calculation time overhead for the adaptive samplingmethod on an FPGA is relatively very small since multiplemodules can be used concurrently. Additional processingtime would be within a few clocks of the maximum.

4. Simulation

This research utilizes SIMetrix/SIMPLIS (20) for the circuitsimulator. It is a powerful circuit simulation program devel-oped for high-speed modeling. In particular, it is very capable

(a) Case of duty ratio over 50%

(b) Case of duty ratio under 50%

Fig. 9. Sampling timing for the proposed method

at treating switching electrical sources, where analog and dig-ital circuits can be simulated concurrently. All the simula-tions are programmed schematically by using the embeddedmodules in the SIMetrix/SIMPLIS program.

To verify the effect of noise, simulations are conductedusing synchronous sampling for the digital control current-mode power converter with sawtooth carrier waveform andparameters defined in Sect. 2. The adaptive sampling methodis then implemented and another simulation is conducted onthe same circuit.

4.1 Random Phase Noise Generation In order tosimulate the converter circuit as closely to the real environ-ment as possible, this paper also introduces a novel switchingnoise generation method. Based on the observations from theexperiments above in Sect. 2, it is obvious that the magnitudeof the switching noise varies randomly in each switching. Tosimulate such noise, we propose a random phase noise gen-erator. Its circuit consists of an LC resonance and a phaserandomization part.

To achieve the phase randomization an 8-bit linear feed-back shift register (LFSR), as shown in Fig. 11, is used.An LFSR is widely used to generate pseudorandom num-bers (21) (22). In essence, this is a shift register that shifts thesignal one bit at a time, towards the direction of the mostsignificant bit when the clock signal is on. In order to forma feedback mechanism, some of the outputs are combinedwith an exclusive OR (XOR) gate. When the output of theflip-flops are loaded with a seed value (anything except all0s, which would cause the LFSR to produce an all-0 pattern)and when the clock signal is input to the LFSR, it generatesa pseudorandom pattern. Hence, the only signal needed togenerate the random patterns is the clock.

The mechanism for random phase noise generation isshown in Fig. 10. First, the generator uses the clock predictorto set the timing for the charge. When the one-clock-before-switching timing arrives, a pseudorandom number will begenerated by the LFSR. Accordingly, the random number



Fig. 10. The block diagram of random phase harmonic generator

Fig. 11. A linear feedback shift register(LFSR) imple-mented in the simulation

Fig. 12. Waveform of the harmonic noise generatedwith a static noise generator

will be converted to an analog value which approximatelydistributes from 0 to 10 V (later referred to as Vrandom). Fi-nally, Vrandom is applied to the capacitor LC resonance circuitand the charging takes place during a 1/2 clock width timeinterval. Next, the virtual wave with harmonic is triggered bythe drive signal for the switching of the main circuit. By sub-tracting it from the original square waveform, the harmoniccan be generated. To induce the switching noise into thecontrol circuit, the harmonic is then added to the feedbackcurrent from the main circuit. For the random phase noisegenerator utilized in this paper, the resonant frequency andthe damping time are tuned on the basis of the experimentalresults in Sect. 2.

Figure 12 shows the waveform of the generated switch-ing noise without the proposed random phase noise. On theother hand, Fig. 13 illustrates the waveform of the switch-ing noise output when the random phase noise generator is

Fig. 13. Waveform of the harmonic noise generatedwith a random phase noise generator

implemented. Because the imposed Vrandom to the LC ca-pacitor changes at every switch randomly, the generated har-monic also changes. As depicted, the proposed random phasenoise can generate noise with different magnitudes at eachswitching. Therefore, by implementing the proposed switch-ing noise generator, a realistic simulation of the converter cir-cuit can be conducted.

4.2 Simulation Results The simulation result of thepower converter when samples are taken at arbitrary points(50th clock), but without the random phase noise, is shownin Fig. 14. The input in this case is static switching noise,meaning that the applied Vrandom to the LC capacitor will notchange at each switching activity. As shown, the simulationresult produces an average current output of 690 mA. Thisvalue, however, is inaccurate; it depends on the samplingpoint. In short, the switching noise fails to be characterizedas in practice and the output current does not fluctuate whensamples are affected by switching noise, as shown in the ex-perimental result above. On the other hand, with the sameconditions, Fig. 15 demonstrates the benefit of the randomphase noise generator. The result is identical to the exper-imental result shown in Fig. 7, in which the average currentis 583 mA. Therefore, by introducing the random phase noisegenerator, the switching noise can be characterized and hencethe simulation can give results that are very close to the ex-perimental ones.

The simulation result of the digital control current-modepower converter with the PWM sawtooth carrier waveformand adaptive sampling is depicted in Fig. 16. It is seen that



Fig. 14. Simulation result of the power converter whensample values are affected by static noise

Fig. 15. Simulation result of the power converter whensample values are taken synchronously at a static point

the converter can successfully avoid switching noise by adap-tively tuning the sampling points. Furthermore, since the av-erage current is also detected, a stable and accurate outputcurrent of 615 mA is obtained.

4.3 Spectrum Analysis The spectrum analysis of thesimulation results are depicted in Figs. 17 and 18. In eachfigure, the spectrum analysis results of two simulations areshown. One is the power converter without the adaptive sam-pling method, no noise injection and the sample values aretaken at the end of the ramping period. The other is whenthe adaptive sampling method is implemented and randomphase noise is injected. As a result, although the waveform ofthe latter may include a switching noise component, it showsan arguably identical result with the waveform of the formernear a multiple frequency of 20 kHz. Therefore, it is verifiednot only in the time domain but also in the frequency domainthat by implementing the proposed sampling method correctcontrol of the converter circuit can be expected.

Regarding the simulation results, the effectiveness of theproposed method in avoiding the effects of switching noiseon samples is verified. Hence, correct control and stable out-put current from the converter circuit can be expected. Thus,

Fig. 16. Simulation result of the proposed method im-plemented on a digital control power converter with aPWM sawtooth carrier waveform

Fig. 17. Spectrum analysis of the simulation results

Fig. 18. Enlarge waveform of the spectrum analysis ofthe simulation results

the reliability of the converter circuit has been improved.

5. Experimental Result

An experiment is also conducted to investigate the effec-tiveness of the proposed method in practice. The proposedmethod is implemented on an actual digital control current-mode power converter using an FPGA with a PWM sawtooth



Fig. 19. Experimental result of the proposed methodimplemented on a digital control power converter witha PWM sawtooth carrier waveform

carrier waveform.The experimental result is shown in Fig. 19. In real-

ity, the converter circuit also shows successful avoidance ofthe switching noise, a stable and accurate output current of615 mA. Therefore, it is verified that by implementing theadaptive sampling method on a digital control current-modepower converter circuit, the effect of noise on sample valuescan be successfully avoided, and a stable and accurate outputcurrent can be obtained. Hence, the reliability of the circuitis enhanced.

6. Conclusion

This study has confirmed the presence of switching noiseon digital control power converters employing synchronoussampling techniques. Experimental results indicate that thereare cases when the noise may affect sample values. The re-liability of the power converter circuit may therefore be re-duced. As a countermeasure to enhance the reliability of thecircuit, an adaptive sampling method is proposed. By adap-tively tuning the sampling time on the basis of duty ratio,successful noise avoidance is achieved. Simulation and theexperimental results verify the effectiveness of the proposedmethod. A random phase noise generator is also introducedto make the simulation of the power converter circuit as re-alistic as possible. Both the simulation and the experimentalresults indicated successful noise avoidance, indicating thatthe converter circuit is correctly controlled. Accurate andstable output current is obtained using a relatively small cal-culation overhead. Consequently, the reliability of the powerconverter circuit with a PWM sawtooth carrier waveform isimproved by implementing the proposed adaptive samplingmethod.

AcknowledgmentThe authors would like to convey the appreciations to Pro-

fessor Toshihisa Shimizu, Tokyo Metropolitan University, forhis guidance and support throughout this research.

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Aromhack Saysanasongkham (Non-member) received his B.E. de-gree in 2011, from Polytechnic University, Kana-gawa, Japan. He received his M.E. degree in 2013 andis currently a Ph.D. candidate at Tokyo Metropoli-tan University, Tokyo, Japan. His research interestsinclude dependable designs for processors and net-works. He is a member of IEICE.



Masayuki Arai (Non-member) received his B.E., M.E., and Ph.D.degrees in 1999, 2001, and 2005, respectively, allfrom Tokyo Metropolitan University. From 2001 to2013 he was a Research Associate at the same univer-sity. Currently, he is an Assistant Professor at Collegeof Industrial Technology, Nihon University. His re-search interests include VLSI design and test, as wellas dependable systems. He is a member of IEEE andIEICE.

Satoshi Fukumoto (Non-member) was born in Hyogo Prefecture,Japan, on June 29, 1962. He received the B.S.E.,M.S. and Ph.D. degrees from Hiroshima University,Japan, in 1987, 1989 and 1992, respectively. From1992 to 2000 he was working at the Department ofInformation Network Engineering, Aichi Institute ofTechnology, Japan. Since 2000 he has been workingat Tokyo Metropolitan University, where he is now aprofessor of the Faculty of System Design. His re-search areas include dependable computing, parallel

and distributed systems, networks, design for testability, and reliability the-ory. He is a member of the Institute of Electronics, Information and Com-munication Engineers of Japan, the Information Processing Society of Japan,the Operations Research Society of Japan, IEEE, and ACM.

Shun Takeuchi (Student Member) received the B.E. degree in elec-trical engineering, from Tokyo Metropolitan Univer-sity, Tokyo, Japan, in 2013. He is currently workingtowards the M.E. degree in the same university. Hisresearch interests include digital current control usingFPGA.

Keiji Wada (Member) received the Ph.D. degree in electrical engi-neering, from Okayama University, Okayama, Japan,in 2000. From 2000 to 2006, he was a ResearchAssociate at Tokyo Metropolitan University, Tokyo,Japan, and the Tokyo Institute of Technology. Since2006, he has been an Associate Professor with TokyoMetropolitan University. His research interests in-clude medium-voltage inverter, electro- magnetic in-terference filters, and active power filters.


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A Highly Reliable Digital Current Control using an