A CMOS Micro-power and Area Efficient Neural Recording and Stimulation Front-End for Biomedical Applications

Circuits Syst Signal ProcessDOI 10.1007/s00034-014-9935-x

A CMOS Micro-power and Area Efficient NeuralRecording and Stimulation Front-End for BiomedicalApplications

Sami Ur Rehman · Awais Mehmood Kamboh

Received: 6 June 2013 / Revised: 30 October 2014 / Accepted: 31 October 2014© Springer Science+Business Media New York 2014

Abstract This paper presents an ultra-low power and small area analog front-endfor an implantable multichannel neural signal recording and stimulation interface,to be used in wirelessly powered implantable Brain-Machine Interfaces. For a givenfunctionality and performance, area, power, and noise-response are the three criticalparameters that define the suitability of a design for implantation. The three maincomponents of a typical neural implant are the analog front-end, the digital processor,and the wireless data and power transceiver. Among them, neural front-end is the mostpower and area hungry module. This paper presents an 8-channel analog front-endprototype for simultaneous recording and stimulation, employing a novel architecturewhich significantly improves power and area consumption of the chip over currentstate of the art. In contrast to published architectures, the multichannel recording pathis centered on a single super-performing tunable gain-bandwidth amplifier instead ofemploying a separate stand-alone amplifier for each electrode. The resulting circuitryrequires smaller area and less power compared to all previously published designs.Designed in 0.5µm CMOS with VDD of 1.8 V, the 8-channel recording path consumea total of 77µW of power and a net area of 0.24 mm2, allowing scalability to a highchannel count. The stimulation path utilizes 8 stimulators, each employing an 8-bitmultibias DAC with a current amplifier to drive electrode–electrolyte high impedanceload. Each stimulator consumes full scale power of 224µW and entire stimulationpath occupies an area of 0.32 mm2.

S. U. Rehman (B) · A. M. KambohDepartment of Electrical Engineering, School of Electrical Engineering and Computer Sciences,National University of Sciences and Technology, Islamabad, Pakistane-mail: [email protected]

A. M. Kambohe-mail: [email protected]

Circuits Syst Signal Process

Keywords Filter amplifier · Dneural recording · Neural stimulation · Brain–machineinterface · Electrode potential

1 Introduction

Last few years have seen a remarkable improvement in our ability to measure neuro-electrical activity from multiple neurons simultaneously, which have attracted unprece-dented attention of scientists and clinicians worldwide. High density microelectrodearrays have enabled measurement of neural signals up to the resolution of a singlecell [14]. This has enabled researchers to try to unlock the mysteries of neural codingby identifying specific neural patterns and diagnose brain related ailments such asParkinson’s disease, epilepsy, and seizures. Equally important is our improved abil-ity of stimulating individual or group of neurons by applying an external stimulus;enabling researchers to study neural plasticity and build intelligent prosthetic devicesfor the amputated persons [8].

Traditional transcutaneous ways of recording data from tethered electrodes presentconstricting problems ranging from infection to limited patient mobility, rendering thetechnique suitable only for investigational and clinical use. Wireless data and powertelemetry have emerged as a possible solution to most of these problems.

Neural signals comprise of the action potentials, also known as neural spikes, andthe local field potentials (LFP). Neural spikes have amplitudes ranging from 10 to50µVpp and lie in a frequency band of 300 Hz to 7.5 KHz. LFPs have amplitudestypically ranging from 1 to 10 mVpp and lie in a frequency band of 25 mHz–100 Hz [7].Both these components provide important information about individual and collectiveneuron activity, respectively.

Design of a wirelessly powered implantable system has its own set of limitationsand trade-offs. Since the neural signals could be as weak as a few microvolts, they caneasily be corrupted by noise, the analog front-end therefore needs to have a very lowinput referred noise. Area footprint for implanted modules must be as small as possiblebecause the surgical burr hole made to implant a device in the cortex has typical area onthe order of 1 cm2. Additionally, to keep valued-silicon consumption and fabricationcosts minimum, chip area needs to be curtailed. However, in vivo neural recordingis safety critical because even a 1 ◦C rise in chip temperature with respect to thesurrounding tissue can burn and kill the information carrying tissues; this translates tothe net power consumption density of 0.58 mW/mm2 by the implant [20]. Low poweroperation, therefore, in implants is one of the most critical parameters. To conservepower, most of the analog circuitry is designed in sub-threshold regime instead offield-affect regime; however, reduced power increases thermal noise and decreasessettling time of analog modules. Similarly, reducing frequency-dependent flicker noisedemands increased device sizes which resultantly increase the overall area of the chip.These tradeoffs have to be catered for while designing robust biomedical electronics.

Typical wireless BMI systems have two main components, one implantable on-chipmodule and one external on-board module. The implanted module is physically inter-faced to the cortex, while the external module acts as wireless power source and inter-face to external world. Figure 1 shows a complete architecture of such a system with


Fig. 1 Complete architecture of BMI chip implant and its external module

bi-directional wireless data transfer and wireless power transfer. Data from implant toexternal module, called reverse telemetry, contains information about recorded neuralsignals, while date from external module to implant, referred to as forward teleme-try, contains settings and commands for neural stimulation. The implantable modulecontains analog front-end modules for recording and stimulation of neural tissuesinterfaced to the microelectrode array, converters for digital to analog and vice versa,digital circuitry for programmability and for performing command and control func-tions, power regulation circuits, and finally modulator/demodulators for wireless datatelemetry.

In cortical micro-systems, the front-end analog neural circuitry has a very significanteffect on the constricting parameters discussed above. Wirelessly powered neuralrecording systems must be ultra-low power but also exhibit low input referred noise,both of which have an inverse relationship. This tradeoff is expressed as the noiseefficiency factor (NEF) [21]. Ultra-low power and low noise requirements make thefront-end amplifier one of the most critical components in neural signal recordingpath. A Neural amplifier is required to receive input from the microelectrode, purifyand amplify the neural signal and send it to the analog to digital convertor (ADC)for digitization and further processing. On the other hand, in reverse telemetry, astimulator or spike generator takes a digital bit stream as input and yields a controlledlow frequency current spike at the stimulating microelectrode.

For the last few years, designing low area-power biomedical front-ends has been anarea of growing importance. There have been several efforts starting with a landmarkarchitecture presented by Harrison [7] which could record multiple biomedical signals,but is somewhat power-inefficient by modern standards. However, this architecture hasserved as a benchmark and starting point for several designs in later years.

A 128-channel neural stimulation and recording interface is discussed by Shahrokhiet al. [20] consuming moderate area and power. Ghovanloo discusses gain-bandwidth


Fig. 2 Designed neural recording and stimulation interface for BMI chip

tenability in [24]; Wattanapanitch and Sarpeshkar’s [23] gain and bandwidth tunable32-channel neural interface is power and area efficient but slightly compromised interms of NEF. In [13], authors have proposed a novel operational trans-conductanceamplifier (OTA) sharing architecture to reduce the NEF. One of the drawbacks ofoperating major chunk of analog circuitry in sub-threshold region for power saving isthe inherent nonlinearity introduced in the amplifier design. A technique to reduce theflicker noise and to enhance linearity of ultra-low power neural amplifier is describedin [12,18], respectively. In most multichannel systems, each channel has its own highperformance amplifier, its own filter, and its own ADC [1,2]. In addition, many designsrequire a separate amplifier and filter for LFPs. For such designs when the channelcount is increased, the toll is taken on area and power consumption. Such designsbecome impractical in terms of power and area consumption requirements placed onsuch chip implants as discussed above. To conserve area, some architectures use asingle ADC combined with an analog mux [20,23] as shown in Fig. 2, to convertseveral input analog signals into a single digital output stream.

Stimulation paths share some of the abovementioned parameters such as implantsize, power consumption, but have some additional requirements such as stimulationstrategy, biphasic output current, ESD protection, spiking rate, etc. Although thereare several good designs for stimulators, the stimulation path is not as extensivelyresearched and published as the recording path. In [9–11], current mode stimulatorsfor visual prosthesis are presented, but these designs consume considerable amount ofpower and occupy silicon area to unacceptable levels which make such designs suitableonly for low channel systems. Other than charge balancing, [15] also discusses ESDprotection of stimulating electrodes.

In this paper, we propose a new architecture of neural analog front-end for multi-channel recording and stimulation, efficient in terms of area and power. This uniquedesign is best suited for systems with large number of electrodes. As described above,existing neural recording designs report dedicated neural amplifiers for each electrode.


This work, on the other hand, suggests using power and area efficient preamplifierswith each electrode, multiplexing the data from preamplifiers and using one super-performing, gain-programmable, and band-tunable filter to record both spikes andLFPs. The design challenge of this architecture is rooted in the stringent requirementplaced on settling time of the amplifier and the speed of each component in general. Thepaper is organized as follows. After presenting the overall analog front-end architec-ture, Sect. 2 discusses the details of neural recording path and presents its architecture,circuit design, and noise analysis. Neural stimulation path and its design are discussedin Sect. 3. The results are discussed and compared against state of the art in Sect. 4.Finally, Sect. 5 draws conclusions from presented work.

The front-end presented in this paper consists of both the recording and stimulationpaths, as shown in Fig. 2. Both simulation and recording paths operate independentlyand are separated by a channel select switch. A multichannel implant, when insertedin the body of a living organism, can either be connected to a motor neuron (carryingsignal from brain to receptor cells on skin) or a sensory neuron (carrying data fromreceptor cells to brain). In certain implants, the same microelectrode array may beinterfaced to both the motor and sensory neurons, without allowing much control overwhich individual electrode touches which kind of neuron. The 8-channel prototypepresented here addresses this issue by interfacing each electrode to both the stimulatingand recording circuitry. The two paths are separated using analog multiplexors. Thisrequires the subsequent recording and stimulation circuitry to be designed to overcomeany loading effects because of the shared interface. At any given time, any electrodecan be configured as either recording or stimulating. Thus, all the channels could beconfigured for recording, or stimulation, or a mix of both. The unused stimulation orrecording path can be cut-off from the power supply rail to conserve power.

2 Neural Recording Path

2.1 Architectural Description

The idea we intend to hypothesize is based on the observation that in traditional sys-tems as in Fig. 3, each amplifier is a fully fledged high performance circuit which isthe most power and area consuming component of the entire front-end. In multichan-nel systems where multiple copies of such power hungry modules are required theoverall power consumption increases to unacceptable level. If somehow, one super-performing amplifier could be designed that can serially record data from multiplechannels replacing these amplifiers, the overall power and area consumption for amultichannel system could be significantly curtailed. Such an architecture can pro-vide an opportunity to design efficient high channel count neural sensor interfacewhich can fulfill the medical requirements of power and area placed on such medicalimplants, and hence for their possible commercialization.

The new architecture we propose, as shown in Fig. 4, is based on dividing theamplification stages into two parts. Close to electrodes are the fixed-gain small-sizeddifferential preamplifiers which are followed by a mux and then the second amplifi-cation stage in the form of a super-performing gain-bandwidth programmable filter


Fig. 3 Traditional neural signal front-end architecture

Fig. 4 Proposed neural signal front-end architecture

amplifier is appended to record both spikes and LFPs. In essence we have attemptedto reduce the area and power by pushing the analog mux closer to electrodes andsequentially recording neural signals within a time window which ensures no signalon any channel is missed. One critical drawback of this architecture is the constrictingrequirement of settling time of the super-performing filter amplifier since the datais serially recorded from all the available channels, multiplexed and is input to thefilter amplifier which must be fast enough to amplify/filter all the recorded signals.However, a robust design of such an amplifier can be implemented if the constrictinganalog tradeoffs are taken care of and this is what we have achieved in our design. Ourprototype currently deals with only 8 channels and the settling time of the designedfilter amplifier easily enables the processing of data multiplexed form 8 channels.

2.2 Circuit Level Design

2.2.1 2:1 Mux and Preamplifier

During stimulation phase 2:1 mux, as shown in Fig. 2, has to deal with large ampli-tude signals but during recording phase the signals from electrodes could be onlyfew tens of µVs. It is pertinent to mention here that useful biomedical information


is stored in the number of occurrences of spikes and LFP signals and not in theiramplitudes. Amplitude loss of spikes and LFP signals during recording phase in 2:1mux is less of a concern provided we do not lose their frequency information. Thisstill requires us to keep the noise level and on-resistance of the mux to its minimum.We have employed transmission gate muxes with dummy transistor in our design,as detailed in [17], to reduce channel charge injection and clock feed-though. Thedesigned switches have low leakage current of few picoamperes, low feed-thoughcapacitance in order of a femto farads, noise level below 20µV, on resistance ofmerely 8� and off resistance of roughly 25 M�. The on resistance of a transmissiongate is given as RON = 1/μCOX

WL (VGS − VTH). By properly controlling the device

sizes we were able to keep the noise level and on resistance of the switches to therequired level, although achieving such specifications in scaled CMOS nodes is quiteambitious due to enormous analog impairments.

To achieve high common mode rejection, the preamplifier in the proposed archi-tecture, as shown in Fig. 4, should be differential in nature. We are using a typicaldifferential amplifier with active loads and a fixed gain of around 20 dB. The input dif-ferential pair and the load pair are sized to minimize the thermal and flicker noise andachieve high input impedance as it acquires weak neural signals immersed in noise.

2.2.2 Gain-Bandwidth Tuneable Filter Amplifier

From preamplifiers, the signal is input to a transmission gate-based multiplexer andthen fed in to a filter with controllable gain and bandwidth. The filter-amplifier adjustsits bandwidth and gain to measure spikes or LFPs as determined by the control signals.Because of its balance in speed, resolution, power, and area successive approximationregister (SAR) ADC is best suited for biomedical applications and is preceded by theneural amplifier.

Considering the highest neural signal frequency of 7 kHz, the sampling frequencyis set at 20 ksps per channel. Since the output signals from 8 channels have to betime-multiplexed, this translates to a maximum allowed scan time of 6.25µs for eachchannel. This implies that every channel will receive the signal, filter/amplify it, anddigitize it within 6.25µs after every 50µs. Therefore, although the proposed archi-tecture utilizes fewer circuit blocks to conserve power and area, the settling time ofthe filter-amplifier poses a serious challenge. The gain-bandwidth programmabilitymeans that any of the channels can be used to record LFPs or spikes as needed.

The filter-amplifier block in Fig. 4 consists of a gain stage followed by band-tunable filter stage as shown in Fig. 5. The capacitive feedback sets the mid-band gain(Cin/Cfeed), the low cut-off frequency is adjusted by Vtune, and the high-pass cut-offfrequency depends on Cc, apart from OTA trans-conductance and its gain.

The design uses a fully differential telescopic OTA in the gain stage as shownin Fig. 6. Input differential pair, M1 and M2, is the major source of device size-dependent flicker noise in the designed OTA. Similarly, a high input trans-conductanceis required to suppress thermal noise. Therefore, large PMOS devices operating in sub-threshold regime/weak inversion regime instead of field effect regime are used not onlyto constrict noise but also to conserve power.


Fig. 5 Band-tunable and gain-programmable filter

Fig. 6 Telescopic OTA used in neural amplifier

Transistors M3 and M4, also operating in sub-threshold, are cascaded with inputdifferential pair to enhance the output impedance. M5–M12 comprise the currentsteering circuit while M13–M20 together make the common mode feedback circuit(CMFB). Coefficient (IC), given as drain current over saturation current, is the primaryparameter that describes the region of operation of a MOSFET and must be lessthan 0.1 for a device in sub-threshold regime. With IC known, trans-conductance anddevice size in sub-threshold regime can easily be calculated using a procedure nicelyelaborated in Harrison’s amplifier architecture [7].

2.2.3 Analog to Digital Converter Design

For a sampling frequency of 20 kHz and required resolution of 8 bits, SuccessiveApproximation Register (SAR) ADC was designed which is considered ideal forbiomedical applications. A typical SAR ADC consists of a comparator, DAC capacitivearray, and SAR logic circuitry as shown in Fig. 7a. The ADC computes the 8-bit digitalcode of the analog signal in 8 clock cycles; 1 bit is calculated per cycle. Therefore, thecomparator clock is 8 times the sampling frequency. The SAR ADC search algorithm


VDD

GND

Vin+ Vin-

CLK CLK

Vbias

Vout+

Vout-M7

5M 6MM4M3

M2M1M8

M9

M10

M11

(a) (b)

Fig. 7 a SAR ADC architecture and b comparator circuit

is as follows. First, the reference voltage is applied across MSB cap (with value of128*Cunit) while all the rest capacitors have zero voltage across them. Due to referencevoltage across MSB capacitor, the charge evenly distributes across the entire capacitivearray and the resultant voltage on the upper plates of capacitors is compared with theinput voltage. If Vin is high, comparator output jumps to Vdd and the MSB bit is set. IfVin happens to be lower than the voltage across the capacitor array, MSB bit is reset.This is the end of first cycle. Now the same procedure is repeated for the next cycleand the next bit is computed. We have used 10 fF as unit capacitance, and thereforethe net capacitance, excluding the parasitic, is around 2.56 pF.

Figure 7b shows the comparator schematics used in our design which is earlierreported in [19]. In the comparator architecture, M1 and M2 are the input differentialpair while M7 is the current source. M8 and M9 and M10 and M11 are complementaryinverters. When the clock signal is low M3 and M6 are switched on and they force theoutput terminals of inverters to zero. When the clock is high a comparison process iskick started as M3 and M6 are turned off.

As the gate voltages of differential pair are different, different saturation currentflows through them and the drain terminals of both M1 and M2 move to a lower voltageat different rates. If the gate voltage of M1 is higher than that of M2, the drain terminalwill move more quickly to a lower voltage than its counterpart and finally switch onthe feedback PMOS M5 which will force Vout− to zero. Since the drain voltage of M1was low enough, Vout+ is latched to Vdd.

2.3 Noise Analysis

As mentioned earlier noise is another critical parameter in neural recording. Thermalnoise, produced due to random motion of electrons, is the dominant source of noisealong with flicker noise which is produced in a MOS due to “dangling bonds” appearingat the interface of silicon substrate and gate oxide. In a MOS, thermal noise is modeledas a current source connected between drain and source and given as 4kT γ gm, wherek is Boltzmann constant, γ is the gate coupling coefficient with a typical value of 2/3,and gm is the trans-conductance of the MOS under consideration. Similarly, flickernoise can be modeled as a voltage source in series with the gate of device given by


K/Cox ∗ (W L) ∗ f , where K is the process-dependent parameter with a typical valueof 10−25V 2 F , Cox is the gate oxide capacitance, W L represents the device size, andf is the frequency of operation.

In cascaded structures, like telescopic in our design, the cascade devices contributenegligible noise. Therefore, in the designed OTA, M1–M2 and M5–M6 are the domi-nant sources of noise. Equation (1) shows modeling thermal noise for the input differ-ential pair while Eq. (2) refers to output referred thermal noise voltage by multiplyingEq. (1) with output impedance

I 2n,thermal,M1+M2 = 2(4kT γ gm(1,2)) (1)

V 2n,thermal,M1+M2 = 2(4kT γ gm1,2) ∗ (Rout)

2. (2)

Similarly for M5 and M6, in Fig. 6, the output thermal noise voltage can be given byEq. (3)

V 2n,thermal,M5+M6 = 2(4kT γ gm5,6) ∗ (Rout)

2. (3)

Now, calculating flicker noise for the input differential pair, we have 2K/Cox ∗ (W L) ∗f . But this flicker noise voltage appears at the gate terminal of the device and it mustbe multiplied with the gain of input differential pair to replicate it on output node. Thegain of input differential pair is gm Rout. Equation (4) shows output referred flickernoise of M1 and M2

V 2n,flicker,M1+M2 = 2K

Cox(W L)1,2 f(gm1,2)

2(Rout)2. (4)

Similarly for M5 and M6 output flicker noise voltage is given in Eq. (5). Note that thenoise voltage at the gate of M5 and M6 will be multiplied by the gain of these devicesinstead of input differential pair

V 2n,flicker,M5+M6 = 2K

Cox(W L)5,6 f(gm5,6)

2(Rout)2. (5)

Equation (6) shows all these output referred noise voltages combined at the outputnode terminal

V 2n,total,out = 2(4kT γ gm1, 2) ∗ (Rout)

2 + 2(4kT γ gm5,6) ∗ (Rout)2

+ 2KCox(W L)1,2 f (gm1,2)

2(Rout)2

+ 2KCox(W L)5,6 f (gm5,6)

2(Rout)2.

(6)

Now dividing Eq. (6) with the square of gain we get input referred noise shown inEq. (7). Input referred noise clearly indicates that flicker noise primarily depends on


Fig. 8 a Variable-gain and band-tunable filter output plots. b SAR ADC output with an input voltage toADC held at 1 V. c Neural signal amplifier time domain output. d Pulsed input to the filter amplifier (top).Resulting settling time of designed single supply filter amplifier (bottom)

device sizes while the thermal noise is directly proportional to load trans-conductanceand inversely proportional to input trans-conductance

V 2n,total,in = 2(4kT γ )

[1

gm1,2+ gm5,6

(gm1,2)2

]+ 2K

Cox f

[1

(W L)1,2+ (gm5,6)2

(W L)5,6(gm1,2)2

].

(7)

2.4 Neural Recording Interface Layout Results

2.4.1 Gain-Bandwidth Variability

The OTA has a DC gain of around 76 dB and common mode rejection ratio of 72 dB.Figure 8a shows plots for different gains, lower and higher cut-off frequencies obtainedby setting appropriate values of feedback switching capacitors, ‘Vtune,’ and couplingcapacitor, respectively, in Fig. 5 using control circuit (not shown). Table 1 shows thevalues of these parameters corresponding to curves in Fig. 8a.

2.4.2 Transient Response

Figure 8c shows the time-multiplexed output of neural signal amplifier after beingsampled and held when the inputs to the electrodes were sinusoids of relevant fre-


Table 1 Parameter variation forgain-bandwidth tunability

A B C D E

Cin/Cfeed 50 100 100 25 50

Vtune (V) 1.2 0.7 0.5 0.7 0.5

Cc (pF) 5 2.5 5 5 5

BW (kHz) 10 9.9 1 9.9 9.9

quencies and amplitudes. The SAR ADC output for a 1 V input value shown as digitalcode, comparator output, and the voltage variation at DAC capacitive array for 8 clockcycles is also shown in Fig. 8b.

2.4.3 Noise Performance

Noise efficiency factor is used to determine the noise characteristics of an analog front-end. The theoretical floor of NEF, when the two input differential PMOS are the onlysource of thermal noise, (ignoring flicker noise), is 2.9 as calculated in [21]. UsingEq. (7), at 2.2µA current for OTA, the input referred noise turned out to be around6µVrms while its measures value was calculated as 6.4µVrms. This corresponds to aNEF of 4.6 which is quite acceptable to process the neural signals under consideration.

2.4.4 Settling Time

As discussed in Sect. 2, with a channel rate of 6.25µs/channel the settling time require-ment of the neural filter amplifier becomes approximately 1µs, while 4.5µs are allottedto SAR ADC to produce the corresponding digital code. Settling time of the amplifiercan be decreased or increased with a trade-off on power consumption. Smaller settlingtime requires more power. This becomes important if the number of channels in thesystem needs to be different from the 8-channel prototype. Figure 8d shows that thesettling time of the filter amplifier lies well within this specifications when a step inputis applied.

2.4.5 Static and Dynamic Specifications of ADC

Figure 9 shows the power spectral density of the designed SAR ADC with signal tonoise and distortion ratio (SNDR) of around 47 dB and hence effective number of bits(ENOB) of 7.5 bits.

Figure 10 shows the INL and DNL plots for the designed ADC. INL/DNL valuesremain less than ±1 LSB which is a necessary condition for monotonic behavior ofADC.

2.4.6 Statistical Simulations for ADC

Device mismatch and process variations can significantly degrade the performance ofsensitive analog circuitries like filters, comparator, current-weighted DAC capacitivearray, etc. and can result in unacceptable yield loss [4]. Although the impact of mis-


Fig. 9 Dynamic range and ENOB of the designed ADC. Vertical axis, Y0, denotes the magnitude ofharmonics in dB and horizontal axis, X0, denotes the frequency range in kHz

Fig. 10 INL and DNL plots of the designed ADC

match and process variations is more pronounced in sub-micron CMOS nodes (90 nmand below), even in relatively stable nodes, like 0.5µm, poorly laid out circuitries canexperience significant performance degradation.

In SAR ADC, performance of comparator and DAC capacitive array are prone todevice mismatch and alterations of process parameters like gate leakage, thresholdvoltage, dopant fluctuations, etc. For comparator, the input differential pair is sizedsuch that not only 1/ f noise but transistor mismatch is also minimized. By followingthe famous 1√

W Llaw as detailed in [16] mismatch and process variations can be

averaged out over a large area. Similarly, DAC capacitive array was properly laidout to minimize the process alterations and mismatch. In order to capture the errorintroduced by the lithographic and process variations, we ran Monte Carlo (MC)simulations on SAR ADC and computed error of the digital estimate generated bySAR ADC to the applied analog input value.

The binary output of ADC was converted into its analog form using: (MSB ∗2N−1+MSB2 ∗ 2N−2 + . . . LSB)/2N which should ideally be equal to the analog inputapplied to ADC. The difference between the applied analog input and computed analogoutput, using above formulae, corresponds to the error generated by the ADC whichalso includes the ADC quantization error and is plotted in Fig. 11. From Fig. 8c, we see


Fig. 11 Statistical error generated by the ADC for 15 runs. Thick dotted lines represent ±3σ limits

that the analog input of ADC varies from 0.5 to 1.7 V; therefore, for MC simulations weswept the ramp input signal from 0.5 to 1.5 V, applied the error estimation methodologydiscussed above and computed statistical error for the designed ADC. From Fig. 11, wesee that error is largely dominated by the quantization error of the ADC (quantizationerror of 8 bit ADC is ±1.9 mV, i.e., ±LSB/2).

2.5 Complete Recording Interface Simulation Results

Figure 12 provides complete layout simulation results of the recording interface withspike and LFP waveforms resembling real neural signals. For our test structure, channel1 was applied with LFP and rest of the channels with spikes of the amplitude andfrequency as shown in the figure. An 8-bit shift register in verilog A was implementedto serialize the ADC bits and its output is shown in Fig. 12a. Figure 12b shows outputfrom 508 to 514µs, a time window where the peak of spike at channel 2 is beingdigitized. A formula to convert the 8 bit binary digital ADC output to its decimalformat was implemented in Spectre Calculator for both spikes and LFP, and MonteCarlo simulations (200 runs) for decimal digital codes of 150 (10010110) and 100(01100100) showing the impact of process spread and mismatch on interface circuitis displayed in Fig. 12c, d.

3 Neural Stimulation Path

3.1 Architecture

A neuro-stimulator delivers low amplitude electrical pulses to excite specific neuraltissues and requires a pair of electrodes: a positive anode and a negative cathode. Animplantable stimulator must be power and area efficient, should have long life-time,be robust and reliable, should have high output impedance and good linearity, and be


Fig. 12 a Shift register output, b 8 bits of the ADC for the time when spike is maximum, and c, d MonteCarlo simulations when the decimal ideal digital code was 150 and 100, respectively


Fig. 13 Typical current mode stimulator architecture

independent of stimulation channels. There are two recognized modes of neural fiberstimulation; voltage mode stimulation in which the output of stimulator is a voltagesignal and therefore current drawn by the load depends on its impedance. The othermethod is current mode stimulation in which the output current amplitude is directlycontrolled by the DAC current and is independent of load impedance. Current modestimulation is a preferred method because the quantity of charge delivered to neuralload can be easily controlled unlike in voltage controlled stimulation. Figure 13 showsblock level representation of such stimulators with N-bit DAC and a current outputamplifier.

3.2 Stimulator Design

These stimulators use binary-weighted current DACs in which the aspect ratio ofMOS is altered to achieve binary current weighting. But, due to process variations,achieving the exact transistor sizes could become problematic and resultantly introducenon linearity.

Binary-weighted n-bit current mode DACs mostly consist of n trans-conductorspositioned in parallel with their respective currents combined at a single node. Atrans-conductor amplifier drain current in saturation region is defined by (8)

ID = μnCOX

2

W

L(VGS − Vth)

2, (8)

where μnCox is the technology parameter and the drain current therefore depends onlyon W /L and the VGS. In order to create binary weighted currents for all branches ofDACs, we either can have power-of-two W /L or VGS. Equation (9) provides binary-weighted current equations for 0 < x < N

ID,x = 2x ∗[μnCOX

2

W

L(VGS − Vth)

2]. (9)

To maintain better linearity and preserve area designers in [6] uses multibias tech-niques to produce required currents while keeping a constant aspect ratio. In [22],a stimulation circuit for cardiac cells in 0.13µm technology employing microwavecircuit design techniques including components like LC oscillators and frequencydividers is reported. But such a circuit is inefficient in terms of power and area fordeep brain stimulation.


B0

Vbias0

VDD B1

Vbias1

VDD B7

Vbias7

VDD

Vcascode

Vswitch Vb3

Vb2

GND

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11 M12

M13

M14

M15Vb1

Fig. 14 Stimulator design at circuit level

3.2.1 Circuit Level Implementation

We have used a multibias approach in our design where the power-of-two currentsform trans-conductors are produced using appropriate gate voltages and cascade loadsas shown in Fig. 14. In the above circuit M1 and M2 constitute 2 to 1 switch withtheir output connected to the gate of M3, the trans-conductor amplifier. This commonsource amplifier along with the cascade load, M4 MOS, produces a current which isdouble compared to current of adjacent common source trans-conductor. M5–M15make the output current amplifier.

3.3 Layout Simulation Results

The combined current from the 8 bit DAC is input to M5 and M6 which are thereference branch for the cascade current mirror defined by M9, M10, and M11. M7and M8 form an NMOS switch and define the width of the spike generated at theoutput node. Current micro-stimulators demand a wide swing current output amplifierto drive the highly capacitive electrode–electrolyte impedance. Therefore, our designcontains high output impedance cascaded structure (M12–M15) to drive the electrodeimpedance and produce voltage independent stimulus current. The full scale currentof this amplifier is ±80 µA when connected with 10 k� resistive and 10 nF capacitiveload which is a typical value of electrode/tissue interface impedance for stimulatingretinal neurons [20].

Equations (10) and (11) show the DNL and INL error, respectively, for an 8 bitDAC

DNL = I(x+1) − Ix

�LSB, (10)

INL = Ix − x�LSB + I0

�LSB, (11)


where �LSB = (I(255) − I(0))/256 and 0 ≤ x ≤ 8. As explained in Sect. 2.4.5,technological variations and device mismatch can degrade the performance of currentmode DAC discussed above. In [5], a methodology to evaluate process variationson system performance based on statistical model of MOS transistors is presentedfor current mode DACs. This technique is analytically sound and avoids using timeconsuming MC simulations but requires rigorous mathematical analysis. To minimizethe generated data and time consumed we applied MC simulations for only 50 runs tocompute INL and DNL for designed current mode DAC. These statistical simulations,as shown in Fig. 15, include the contribution of both device mismatch and processvariations.

The output current variation with the input digital code is shown in Fig. 16 whileFig. 17 provides post-layout simulation current and voltage waveforms of the stimu-lator.

Fig. 15 MC plots for INL and DNL of the designed DAC array

Fig. 16 Stimulator current variation with input digital code


Fig. 17 Left Stimulator full scale biphasic output current with some capacitive latency. Right Correspondingoutput voltage waveform for electrode/electrolyte load measured w.r.t reference electrode

4 Results and Comparison

Table 2 provides a detailed comparison of the presented recording and stimulationpath with the state of the art. Note that the power and area parameters are for analogfront-end circuitry and are scaled to 8 channels for a fair comparison among differentarchitectures. From the comparison table, it can be seen that the most power andarea efficient neural recording path have been proposed by Wattanapanitch et al. [23],built in 180 nm technology, and consuming 81.25µW of power and 0.29 mm2 of areafootprint when their 32 channel prototype is scaled down to 8 channels.

It can be seen that for comparable NEF and bandwidth, the proposed architecture,designed with VDD of 1.8 V, results in smallest power consumption of 77µW in therecording path (down from 81.25µW in 0.18µm to 77µW in 0.5µm technology) and224µW in the stimulation path. In addition, the recording path provides good gain eventhough the design uses a comparably less expensive CMOS technology. Similarly, thearea consumption of recording path is, again, minimum for our proposed architecturewhile the stimulation path area is comparable to the state of the art. During stimulation,utilizing a current mode DAC in its design, it provides a full scale biphasic current of±80µA. It must, however, be noted that the results presented in this paper are basedon post-layout simulations whereas most of the works in Table 2 are measurementresults from fabricated circuits.

Figure 18 shows the final layout of the entire 8-channel prototype of analog front-end including recording and stimulation paths. The recording path consists of gain-bandwidth tunable filter amplifier and SAR ADC while the stimulation path consistsof 8 stimulators, one for each electrode.

5 Conclusions

A low power and low area multichannel neural recording and stimulation front-endis presented in 0.5µm n-well CMOS technology. Post-layout simulation results showthat the designed architecture shows improved power and area compared to the designsreported to date. The presented front-end architecture primarily differs in three aspectsfrom the state of the art. First, it time-multiplexes neural signals from 8 electrodes to beprocessed by a single, quick-settling, highly gain-bandwidth tunable filter-amplifier,thereby saving considerable amount of power and area. Additionally, the architecture


Tabl

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Com

pari

son

with

rece

ntly

publ

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Tech

node

(µm

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path

Stim

ulat

ion

path

Filte

ram

plifi

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DC

Tota

lpow

er(µ

W)

Tota

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a(m

m2)

Bip

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ent

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ifier

Tota

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(µW

)

Tota

lare

a(m

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NE

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ain

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0.35

5.5

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K6.

2SA

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20.

3250

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nalo

gS/

H43

9.3

0.32

[10]

0.18

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182

1.33

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224

31.

33

[23]

0.18

4.4–

649

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65SA

R81

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0.29

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[1]

0.35

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1.2

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Fig. 18 Layout of complete analog front-end with recording and stimulation path

can record both low frequency LFPs and high frequency neural spikes, enabled by thegain-bandwidth scalability introduced in the design. Second, power efficient design ofOTA in the filter-amplifier is power efficient with its input differential pair operating inweak inversion regime. The telescopic architecture is designed to have a very low inputreferred noise. Third, we have introduced a mechanism by which the same electrodecan be used for recording or stimulation purposes, as required by the experiment,depending on the site of implant, and the particular neuron in contact. These threedesign features allow for a highly flexible, yet low area-power integrated circuit formultichannel neural interfaces. Comparison to recently published works corroboratesthat our design is well suited for systems in which the channel count runs into tens orhundreds providing both recording and stimulation capability in the same chip.

Acknowledgments The authors would like to acknowledge technical help by Prof. Andrew Mason andMr. Yuning Yang from Department of Electrical and Computer Engineering, Michigan State University,East Lansing, USA.

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A CMOS Micro-power and Area Efficient Neural Recording and Stimulation Front-End for Biomedical Applications