A Reconfigurable 10MS/s to 100MS/s, 0.5V to 1.2V,

0.98mm2, 10b Low-Power 0.13um CMOS Pipeline ADC

ABSTRACT

This work describes a reconfigurable 10MS/s to 100MS/s, 0.5V to 1.2V, 0.98mm2, 10b low-power

0.13um CMOS two-step pipeline ADC. The SHA employs gate-bootstrapped sampling switches and

a two-stage amplifier based on a low-threshold NMOS differential input stage to obtain 10b accuracy

even at a 0.5V supply. A signal-isolated all directionally symmetric layout reduces the MDAC

capacitor mismatch while the flash ADCs employ a switched-bias power-reduction technique to

reduce the power consumption of comparators. The CMOS on-chip I/V references operate at a

supply ranging from 0.5V to 1.2V with optional off-chip voltage references. The prototype ADC in a

0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB,

respectively. The ADC with an active die area of 0.98mm2 shows the maximum SNDR and SFDR of

52dB and 65dB, respectively, and a power consumption of 22.4mW at a typical condition, 0.8V and

70MS/s.

I. INTRODUCTION

As recently developed very large-scale integration (VLSI) technologies enable a number of

transistors to be integrated on a single chip, the system-on-a-chip (SoC) trend is expected to be a

desirable future solution for a variety of high-performance system applications. The SoC reduces the

total manufacturing cost, improves the system performance, and minimizes the chip size. However,

advanced deep sub-micron process technologies primarily for high-density high-speed digital circuits

have continuously demanded low power supplies below 1V. The reduced power supplies increase

the on-resistance of analog switches and decrease the signal bandwidth and swing margin of essential

analog circuits, especially, for the mixed-signal SoC. The typical mixed-signal SoC interface needs a

wide specification of analog signal processing circuits such as analog-to-digital converters (ADCs)

and employs considerably different levels of power supply depending on applications even with the

same process technology. For example, the ADCs for high-definition portable video applications and

high-quality communication systems such as wireless local area network (WLAN) based on IEEE

802.11 require, at least, a resolution of 10b, a sampling rate of several tens of MS/s, a small chip area,

and a low-power consumption while operating at a wide range of power supply.

Of numerous conventional ADC architectures, the pipeline architecture has been widely employed

to meet the required flexible specifications. In the multi-bit-per-stage pipeline ADCs, the more bits

are decided in the front-end stage, the less noise and device mismatch errors from the back-end stages

are input-referred. The power consumption and chip area of the ADCs can be also reduced since the

fewer number of inter-stage amplifiers are used. However, the increased closed-loop gain and the

large load capacitance of inter-stage amplifiers tend to limit the maximum conversion speed of the

ADCs. The comparator offsets may also affect the accuracy in the sub-ranging flash ADCs since

more bits need to be decided in each pipeline stage. On the other hand, the single-bit-per-stage or the

multi-bit-per-stage pipeline ADCs to decide fewer bits in each stage can process analog signals at a

higher speed than the multi-bit-per-stage ADCs to decide more bits in each stage due to the reduced

load capacitance and closed-loop gain of inter-stage amplifiers. However, since the single-bit-per-

stage architecture requires more pipeline stages, more power consumption, and larger chip area, the

increased input-referred noise and device mismatch from the back-end pipeline stages can degrade the

ADC static and dynamic performances considerably.

The recently reported 10b CMOS pipeline ADCs with a sampling rate exceeding tens of MS/s and

the proposed 10b ADC are compared in Fig. 1 [1]-[21]. As shown in Fig. 1, most of the ADCs are

based on the multi-bit-per-stage pipeline architecture with more than three stages. The proposed

ADC employs a two-step pipeline architecture to optimize its power and chip area, considering the

above-mentioned advantages and disadvantages. Above all, as far as the authors know, the proposed

ADC is the unique one operating at a 0.5V supply voltage when compared with the recently reported

ADCs showing the similar specifications. The prototype ADC demonstrates nearly the world-highest

power efficiency of 0.3mW/MHz at a power supply ranging from 0.5V to 0.8V.

Speed [ MHz ]

Pow

er C

onsu

mpt

ion

[ mW

]

1001

2

0.5 mW/MHz

ISCAS01 [16]

VLSI04 [12]

ISSCC03 [15] CICC03 [19]

200

100

ISSCC05 [20]

This WorkThis Work(with 0.5V to 0.8V supply (with 0.5V to 0.8V supply

: 0.3mW/MHz): 0.3mW/MHz)

ESSCIRC02 [3]

JSSC03 [7]

ISCAS00 [4]

ISSCC04 [14]

ESSCIRC05 [21]

: 2.5b/stage: 1.5b/stage

: 3b-3b-3b-4b: 4b-3b-3b-3b: 2b-3b-3b-3b-3b: 3b-3b-3b-3b-2b

ISSCC02 [8]ISSCC06 [11]

ISSCC06 [10]

ISSCC05 [1]

ESSCIRC05 [9]

ESSCIRC06 [5]

: 5b-6b

CICC06 [6]

JSSC99 [2]

CICC06 [13]CICC05 [18]

VLSI06 [17]

Speed [ MHz ]

Pow

er C

onsu

mpt

ion

[ mW

]

1001

2

0.5 mW/MHz

ISCAS01 [16]

VLSI04 [12]

ISSCC03 [15] CICC03 [19]

200

100

ISSCC05 [20]

This WorkThis Work(with 0.5V to 0.8V supply (with 0.5V to 0.8V supply

: 0.3mW/MHz): 0.3mW/MHz)

ESSCIRC02 [3]

JSSC03 [7]

ISCAS00 [4]

ISSCC04 [14]

ESSCIRC05 [21]

: 2.5b/stage: 1.5b/stage

: 3b-3b-3b-4b: 4b-3b-3b-3b: 2b-3b-3b-3b-3b: 3b-3b-3b-3b-2b

ISSCC02 [8]ISSCC06 [11]

ISSCC06 [10]

ISSCC05 [1]

ESSCIRC05 [9]

ESSCIRC06 [5]

: 5b-6b

CICC06 [6]

JSSC99 [2]

CICC06 [13]CICC05 [18]

VLSI06 [17]

Fig. 1. Power and sampling speed of recently reported 10b CMOS ADCs.

In this work, the proposed reconfigurable 10b ADC employs (1) a two-step pipeline architecture to

optimize conversion speed, power consumption, and chip area, (2) MOS transistors with a low-

threshold voltage of 0.35V in gate-bootstrapped input sampling switches and differential input stages

of the sample-and-hold amplifier (SHA) based on a two-stage amplifier to obtain high static and

dynamic performances at 0.5V supply level, (3) a signal-isolated all directionally symmetric layout

technique to minimize the capacitor and device mismatch in the multiplying D/A converter (MDAC),

(4) a switched-bias power-reduction technique to reduce the power consumption of comparators in the

5b and 6b sub-ranging flash ADCs, and (5) the on-chip full CMOS current and voltage (I/V)

references to operate at a supply voltage ranging from 0.5V to 1.2V with optional off-chip voltage

references. The proposed ADC architecture is discussed in Section II. Section III briefly describes

circuit implementation and layout techniques. The measured results of the prototype ADC are

summarized in Section IV.

II. PROPOSED ADC ARCHITECTURE

The proposed 10b CMOS ADC as illustrated in Fig. 2 consists of an input SHA, a 5b MDAC, 5b

and 6b flash ADCs, on-chip I/V references, digital circuits such as digital correction logic (DCL),

decimator, and clock generator. The non-overlapping Q1 and Q2 clock phases are internally

generated.

Q2P

Q1PQ1

Q2DIGITAL CORRECTION LOGIC& DECIMATOR ( 1/1, 1/2, 1/4 fs )

MDAC

I/V REFERENCE WITH OPTIONAL OFF-

CHIP C FILTERS

TIMING GENERATOR

FLASHADC1

5-b

5-b

SHAAIN

FLASHADC2

6-b

10-b DOUT

Q2P

Q1PQ1

Q2Q2P

Q1PQ1

Q2DIGITAL CORRECTION LOGIC& DECIMATOR ( 1/1, 1/2, 1/4 fs )

MDAC

I/V REFERENCE WITH OPTIONAL OFF-

CHIP C FILTERS

TIMING GENERATOR

FLASHADC1

5-b

5-b

SHAAIN

FLASHADC2

6-b

10-b DOUT

Fig. 2. Proposed reconfigurable 10b ADC.

Nonlinear errors such as offsets and clock feed-through errors between pipeline stages are digitally

corrected in the DCL by overlapping 1b from 11b raw codes to obtain 10b outputs. The on-chip

decimator samples the 10b outputs of the prototype ADC at a full, a half, or a quarter conversion speed

accurately to evaluate the ADC dynamic performance by minimizing the glitch and transient noise

coming from the performance evaluation board.

III. CIRCUIT IMPLEMENTATION

1. Proposed SHA with low-threshold gate-bootstrapped sampling switches

The SHA operation at a low supply voltage is commonly limited by high on-resistance of input

sampling switches due to the decreased overdrive voltage (Vgs-Vth). The wideband low-distortion

SHA requires input sampling switches with a low parasitic capacitance as well as a low and constant

on-resistance. Conventional CMOS switches hardly meet the requirements of a resolution of 10b and

a conversion speed of tens of MS/s at a low supply voltage below 1V due to the signal-dependent

resistance variations and low gate-driving voltages of sampling switches. The proposed input SHA

as illustrated in Fig. 3 employs the gate-bootstrapping technique to minimize the nonlinear distortion

of sampled inputs due to the on-resistance variations of switches by keeping the gate-source voltage of

input sampling switches constant [2]. Moreover, the input sampling switches adopt NMOS devices

with a low-threshold voltage to implement a low parasitic capacitance and to properly handle the

Nyquist input frequency even at a 0.5V supply voltage. The SHA sampling capacitance is 1.2pF

considering the required 10b accuracy and kT/C noise at a 0.8Vp-p full-scale input.

Q2BIN+

IN-

T2

OUT+

Q1 Q1B

Q2PB

Q1

MN4

Q1B

MP4 OUT-

AMP1

MG1

GT

MN1

MN3

MP3

Q2PB

C1

MG2

GC

MN2

Q2PB

C2

ATAC

BIAS

BIAS

ACCACT

GATE-BOOTSTRAPPING

Q2 : SAMPLING PHASEQ1 : HOLDING PHASE

Q1

Q2

Q1P

MP1

Q2

Q2

MS1

MS2

MP2 AMP2

C3

C4

T1

MT

GATE-BOOTSTRAPPING “FOLDED” “UNFOLDED”

Q2BIN+

IN-

T2

OUT+

Q1 Q1B

Q2PB

Q1

MN4

Q1B

MP4 OUT-

AMP1

MG1

GT

MN1

MN3

MP3

Q2PB

C1

MG2

GC

MN2

Q2PB

C2

ATAC

BIAS

BIAS

ACCACT

GATE-BOOTSTRAPPING

Q2 : SAMPLING PHASEQ1 : HOLDING PHASE

Q1

Q2

Q1P

MP1

Q2

Q2

MS1

MS2

MP2 AMP2

C3

C4

T1

MT

GATE-BOOTSTRAPPING “FOLDED” “UNFOLDED”

Fig. 3. SHA with gate-bootstrapped sampling switches.

2. Low-voltage amplifier for the SHA and MDAC

The proposed ADC requires low-voltage amplifiers as well as input sampling switches to operate

reliably even at a 0.5V supply voltage. The SHA and MDAC employ a two-stage amplifier to

achieve the sufficient DC gain and output swing margin for 10b accuracy as shown in Fig. 3. The

folded-cascode architecture is employed in the first stage amplifier primarily to achieve a high DC

gain while the unfolded-cascode architecture is needed in the second stage amplifier to obtain a high

output swing margin at a low supply voltage. Particularly, in the input stage of amplifiers, NMOS

transistors with a low-threshold voltage are used simultaneously to achieve a low parasitic capacitance,

a high signal swing margin, and a high trans-conductance for the required bandwidth and sampling

rate at a resolution of 10b and a 0.5V supply.

3. All directionally symmetric highly linear MDAC capacitors

The capacitor mismatch in the MDAC is very critical to the ADC static and dynamic performances.

The capacitor mismatch is caused by random errors and systematic errors. Random errors are caused

by process variations such as inaccurate etching and oxide thickness variations while systematic errors

are caused by different parasitic capacitances between capacitors and adjacent signal lines. Many

inventive calibration techniques have overcome the device or capacitor mismatch problems of the

ADCs for a high resolution exceeding 10b. However, most of calibration techniques with

complicated algorithms tend to increase chip area, power consumption, and engineering cost. As

deep sub-micron technologies have been continuously developed, random errors have been decreased

as well. Systematic errors can be also reduced only by layout techniques without additional

calibration circuits [22], [23]. The MDAC capacitor layout proposed in this work for high matching

is shown in Fig. 4.

: Stacked Metals from MET1 to MET4

: Stacked Metals of MET1, 2, 4

: MIM Capacitor Top Plate

: Stacked Metals of MET1, 3, 4

MET1VIA1

MET2

MET3VIA2

MET4VIA3

: Stacked Metals from MET1 to MET4

: Stacked Metals of MET1, 2, 4

: MIM Capacitor Top Plate

: Stacked Metals of MET1, 3, 4

: Stacked Metals from MET1 to MET4

: Stacked Metals of MET1, 2, 4

: MIM Capacitor Top Plate

: Stacked Metals of MET1, 3, 4

MET1VIA1

MET2

MET3VIA2

MET4VIA3

MET1VIA1

MET2

MET3VIA2

MET4VIA3

Fig. 4. Signal-isolated all directionally symmetric high-matching capacitor layout.

The proposed ADC uses only 4 metal lines for low cost in a 1P6M CMOS technology. The

proposed MDAC capacitors in Fig. 4 are based on a metal-insulator-metal (MIM) structure. All the

symmetric unit capacitors are enclosed by all other metals except the metals for routing the top and

bottom plates of capacitors. Each unit capacitor has the identical environment to all directions and

achieves high capacitor matching accuracy. In the previously published layout technique [23], both

unit capacitors and bottom-plate signal lines are isolated with all the employed metal lines. This

method makes capacitors to be surrounded physically in the same environment. However, some

signal lines passing through neighboring capacitors and unit capacitors may have functionally different

parasitic capacitances each other.

On the other hand, the proposed signal-isolated all directionally symmetric layout technique in Fig.

4 integrates additional metal lines between signal lines connecting the bottom plates of capacitors,

which minimizes capacitor mismatch physically and functionally by isolating each unit capacitor from

all the neighboring signal lines. The conventional dummy capacitors surrounding the whole unit-

capacitor zone further reduce mismatch between unit capacitors caused by process variations. The

proposed 5b MDAC employs a merged-capacitor switching technique to reduce the number of

required unit capacitors from 32 to 16 for low power, high density, and low noise coupling [24]. The

unit capacitor size of the MDAC is designed to be 100fF, considering the kT/C noise and the desired

10b capacitor matching.

4. Switched-bias power-reduction technique for two flash ADCs

The proposed ADC needs two sub-ranging flash ADCs, FLASH1 and FLASH2, generating coarse

5b and fine 6b digital codes, respectively. The comparators in the FLASH1 and FLASH2 are

composed of a two-stage pre-amplifier with an open-loop offset sampling network and a latch for the

required sampling speed and accuracy at a 0.5V to 1.2V supply range with a 0.8V differential

reference voltage, as shown in Fig. 5.

VDD

100%Ⅰreduced

MP1 MP2 MP3

CK

MN2

IREF

VSS

OUT

+

BIAS2

M13

VDD

IN IN

M1 M2 M3 M4

M5 M6

M7 M8

+

MN1

M9 M10 M11 M12

M14

M15 M16

XC3

XC4

MS11

MS12BIASBIAS1

BIAS

CKPB

CKPB

VDD

100%Ⅰreduced

MP1 MP2 MP3

CK

MN2

IREF

VSS

OUT

+

BIAS2

M13

VDD

IN IN

M1 M2 M3 M4

M5 M6

M7 M8

+

MN1

M9 M10 M11 M12

M14

M15 M16

XC3

XC4

MS11

MS12BIASBIAS1

BIAS

CKPB

CKPB

Fig. 5. Pre-amplifier in the FLASH1 and FLASH2 comparators.

The flash ADCs employ a switched-bias power-reduction technique to minimize the power

consumption of pre-amplifiers [6]. During the input and offset sampling mode, the second-stage pre-

amplifier consumes unnecessary power. With the controlled bias voltage of BIAS2 in Fig. 5, the

second-stage pre-amplifier bias current is completely turned off. During the next amplifying mode,

the pre-amplifier bias current is completely resumed. As a result, the proposed flash ADCs consume

less power by 20% than those without using the power-reduction technique.

5. Full CMOS on-chip current and voltage references

The ADC proposed in this work implements full CMOS current and voltage references on a chip

properly to operate at a low supply voltage ranging from 0.5V to 1.2V with optional off-chip voltage

references, as shown in Fig. 6. The typical band-gap voltage reference is difficult to operate at sub-

1V supplies due to the band-gap voltage limitation of 1.25V [25].

IREF VREF LEVEL SHIFTER VREF DRIVER

T1AMPT

AMPC

MPB

Cc1 Rc1

Cc2 Rc2

T2 MNB

VDD

VSS

VDD

VSS

AMPRTR1

MR1

R1

R2

R3

C1

REFT

REFC

TR2

VREFINIREF

BIAS

AMP_BIAS

IR3

IVCN

POFF VDD VDD

EXTRFB

EXTRFC

EXTRFB

VSS

ON-CHIP FILTER

MNS

MPSMRS

Cf1

Cf2Rf2

Rf1

EXTRFBEXTRFREFTOP

REFBOTOptional external reference employed

EXTRFC

TO onTO on--chipchipADCADC

IREF VREF LEVEL SHIFTER VREF DRIVER

T1AMPT

AMPC

MPB

Cc1 Rc1

Cc2 Rc2

T2 MNB

VDD

VSS

VDD

VSS

AMPRTR1

MR1

R1

R2

R3

C1

REFT

REFC

TR2

VREFINIREF

BIAS

AMP_BIAS

IR3

IVCN

POFF VDD VDD

EXTRFB

EXTRFC

EXTRFB

VSS

ON-CHIP FILTER

MNS

MPSMRS

Cf1

Cf2Rf2

Rf1

EXTRFBEXTRFREFTOP

REFBOTOptional external reference employed

EXTRFC

TO onTO on--chipchipADCADC

Fig. 6. Full CMOS on-chip current and voltage references.

The external reference control code (EXTRF) in Fig. 6 decides to use either on-chip or off-chip

voltage references. With the EXTRF high, two reference output nodes are in a high impedance state,

which makes it possible to use off-chip references. It is noted that the ADC has a power-off (POFF)

mode for low-power potable applications. With the POFF set to high, the ADC power consumption

is reduced to 3uW. With the POFF set to low, the ADC returns to the normal active mode

approximately within 1us. The IREF block in Fig. 6 generates on-chip reference currents insensitive

to power-supply and temperature variations. The current mismatch within ±30% can be calibrated in

the digital domain by the 3b IVCN digital code [26].

Recently developed high-resolution CMOS ADCs based on a switched-capacitor technique have

supplied the required reference voltages to internal circuits through MOS switches. These reference

voltages tend to contain high transient glitches and high-frequency switching noise due to repeated

charging and discharging operations. Simple on-chip RC filters integrated with the references

considerably reduce the high-frequency switching noise at the reference voltage outputs and minimize

the settling time even at a maximum sampling rate, 100MS/s, without large conventional off-chip

decoupling capacitors of several uF level. As demonstrated in the simulation results of Fig. 7, the

REFTOP and REFBOT nodes with on-chip RC filters alone (Case I) and with both of on-chip RC

filters and 0.1uF off-chip decoupling capacitors (Case II) show almost the same signal settling

behavior and time.

Fig. 7. Simulated on-chip top and bottom reference voltages.

IV. PROTOTYPE ADC MEASUREMENTS

The prototype ADC is fabricated in a 0.13um n-well 1P6M CMOS process. The proposed ADC

has a limited number of external pins such as inputs, outputs, and power supplies primarily for the use

as one of core blocks of large integrated systems. The chip photograph of the prototype ADC is

shown in Fig. 8, where the blocks encircled by bold and dotted lines indicate on-chip PMOS and

NMOS decoupling capacitors, respectively. The total on-chip MOS capacitors of about 265pF for

two reference voltages and two power supplies effectively suppress the EMI problems and the random

noise coupling from different functional circuit blocks.

Fig. 8. Chip photograph of the prototype ADC (1.20mm × 0.82mm).

The prototype ADC occupies an active die area of 0.98mm2 (=1.20mm × 0.82mm) and dissipates

22.4mW at a typical operating condition, 0.8V and 70MS/s. As illustrated in Fig. 9, the measured

differential non-linearity (DNL) and integral non-linearity (INL) are within 0.35LSB and 0.49LSB,

respectively.

1.0

-1.0

1.0

CODE 1023

INL[

LSB

/10b

]

0

-1.0CODE

DN

L[ L

SB/1

0b ]

0 1023

0

0

0.5

- 0.5

0.5

- 0.5

1.0

-1.0

1.0

CODE 1023

INL[

LSB

/10b

]

0

-1.0CODE

DN

L[ L

SB/1

0b ]

0 1023

0

0

0.5

- 0.5

0.5

- 0.5

Fig. 9. Measured DNL and INL.

A typical signal spectrum of the prototype ADC measured with 70MS/s at a 1MHz input and a

0.8V supply voltage is plotted in Fig. 10.

- 120

- 80

- 40

0

0 Frequency [ MHz ]

[ dB

]

35

fin = 1MHz fs = 70MHz (1024 FFT)

- 120

- 80

- 40

0

0 Frequency [ MHz ]

[ dB

]

35

fin = 1MHz fs = 70MHz (1024 FFT)

Fig. 10. Signal spectrum measured with a 1MHz input signal at 70MS/s.

The signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) in Fig.

11(a) are measured with different sampling frequencies up to 70MS/s at a 1MHz input and a 0.8V

supply. The SNDR and SFDR are maintained over 56dB and 70dB, respectively up to 60MS/s.

With a maximum sampling frequency of 70MS/s at 0.8V, the measured SNDR and SFDR are 52dB

and 65dB, respectively. The SNDR and SFDR in Fig. 11(b) are measured with increasing input

frequencies at a maximum sampling frequency of 70MS/s and a 0.8V supply voltage. As shown in

Fig. 11(b), the prototype ADC maintains the constant SNDR and SFDR with input frequencies

increased to the Nyquist frequency.

(a)

(b)

Fig. 11. Measured SFDR and SNDR versus (a) fs and (b) fin.

The maximum sampling frequency and the corresponding power consumption of the proposed

ADC are measured at operating voltages from 0.5V to 1.8V, as illustrated in Fig. 12. The prototype

ADC demonstrates nearly the world-best power efficiency of 0.3mW/MHz at 0.5V to 0.8V supply

voltages. The measured performance of the prototype ADC is summarized in Table I. The

proposed ADC is compared with the recently reported 10b pipeline CMOS ADCs operating at sub-

1.2V supplies in Table II. The proposed prototype ADC is almost the unique version operating at a

0.5V supply voltage with a 10b resolution and tens of MS/s, demonstrating very high power efficiency

and linearity.

Supply Voltage [ V ]

00.5 0.8 1.0

20

40

60

Sam

plin

g Fr

eq. [

MH

z ]

0.70.6 1.2 1.4 1.6 1.8

80

100

120

22.4mW

3.0mW

5.4mW

11.9mW

37.0mW

45.6mW

53.2mW 65.6mW90.0mW

“Target”“Target”

“Typical”“Typical”

Supply Voltage [ V ]

00.5 0.8 1.0

20

40

60

Sam

plin

g Fr

eq. [

MH

z ]

0.70.6 1.2 1.4 1.6 1.8

80

100

120

22.4mW

3.0mW

5.4mW

11.9mW

37.0mW

45.6mW

53.2mW 65.6mW90.0mW

“Target”“Target”

“Typical”“Typical”

Fig. 12. Measured power dissipation versus supply and sampling frequency.

Table I. Performance summary of the prototype ADC.

Resolution 10bits

Power Supply 0.5V 1.2V∼ (Nominal 0.8V) Conversion Rate 10MS/s 100MS/s (∼ Nominal 70MS/s)

Process Samsung 0.13um CMOS (with MIM Capacitor)

Input Range / On-Chip Reference 0.8Vpp (Fixed, Off-chip ref. optional)

SNDR (@ 0.8V, 60MS/s) SNDR (@ 0.8V, 70MS/s)

56.0dB (@ fin= 1MHz) 51.7dB (@ fin= 1MHz)

SFDR (@ 0.8V, 60MS/s) SFDR (@ 0.8V, 70MS/s)

69.6dB (@ fin= 1MHz) 65.2dB (@ fin= 1MHz)

DNL / INL 0.35LSB / 0.49LSB

ADC Power 3.0mW (@ 0.5V / 10MS/s)

22.4mW (@ 0.8V / 70MS/s) 45.6mW (@ 1.2V / 100MS/s)

Active Die Area 0.98mm2 (= 1.20mm × 0.82mm)

Table II. Recently reported 10b CMOS ADCs operating below a 1.2V supply.

Reference Speed. (MS/s)

Supply (V)

Power (mW)

Area (mm2)

DNL (LSB)

INL (LSB)

This Work 10 ~ 100 0.5 ~ 1.2 3.0 ~ 45.6 0.98 0.35 0.49

ESSCIRC 06 [5] 20 1.2 5.0 0.26 0.80 1.70

CICC 06 [6] 25 1.2 4.8 0.80 0.42 0.91

ISSCC 06 [10] 50 1.2 15.0 0.20 0.17 0.16

CICC 06 [13] 80 1.2 47.0 1.92 0.93 2.21

VLSI 06 [17] 100 1.0 30.0 4.03 0.50 0.80

CICC 05 [18] 100 1.0 40.0 0.52 0.38 0.96

ESSCIRC 05 [21] 200 1.2 55.0 2.52 0.66 1.00

V. CONCLUSION

This work proposes a reconfigurable 10MS/s to 100MS/s, 0.5V to 1.2V, 0.98mm2, 10b low-power

0.13um CMOS two-step pipeline ADC for WLAN and high-quality image signal processing

applications. The ADC is based on the following circuit design techniques. First, the proposed 10b

ADC adopts a two-step pipeline architecture to optimize chip area and power consumption at a

sampling rate of 10MS/s to 100MS/s. Second, the SHA with a high signal-swing range employs

gate-bootstrapped MOS sampling switches and a two-stage amplifier based on folded- and unfolded-

cascode architectures with a low-threshold NMOS differential input stage to achieve high static and

dynamic performances even at 0.5V supply level. Third, the MDAC implements a signal-isolated all

directionally symmetric layout to minimize the capacitor mismatch. Fourth, the sub-ranging flash

ADCs are based on a switched-bias power-reduction technique to reduce the power consumption of

comparators. Finally, the full CMOS on-chip I/V references operate at a supply voltage ranging from

0.5V to 1.2V with optional off-chip voltage references.

The prototype ADC implemented in a 0.13um 1P6M CMOS technology demonstrates the

measured DNL and INL within 0.35LSB and 0.49LSB, respectively. The prototype ADC shows the

maximum SNDR and SFDR of 52dB and 65dB, respectively, a power consumption of 22.4mW at

0.8V and 70MS/s, and an active die area of 0.98mm2.

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