894 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: …eeic7.sogang.ac.kr › paper file › international journal... · 2009-05-28 · 894 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I:

894 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 5, MAY 2009

A 1.2-V 12-b 120-MS/s SHA-Free Dual-ChannelNyquist ADC Based on Midcode Calibration

Hee-Cheol Choi, Young-Ju Kim, Student Member, IEEE, Gil-Cho Ahn, Member, IEEE, andSeung-Hoon Lee, Member, IEEE

Abstract—This paper describes a 12-b 120-MS/s dual-channelpipeline analog-to-digital converter (ADC) for high-speed videosignal processing. A simple digital midcode calibration techniqueis proposed to eliminate an offset mismatch between two channels.The proposed sample-and-hold-amplifier-free architecture withcorrelated input sampling networks enables wideband signalsampling while effectively reducing a gain mismatch betweenchannels. The prototype ADC implemented in a 0.13- m CMOStechnology achieves a peak signal-to-noise-and-distortion ratioof 61.1 dB and a peak spurious-free dynamic range of 74.7 dBfor input frequencies up to 60 MHz at 120 MS/s. The measureddifferential and integral nonlinearities are within � �� LSB and� �� LSB, respectively. The ADC occupies an active die area of

� �� mm� and consumes 51.6 mW at a 1.2 V power supply.

Index Terms—Analog-to-digital converter (ADC), CMOS analogintegrated circuit, comparator offset, dual channel, input samplingnetwork, low power, midcode calibration, sample-and-hold ampli-fier (SHA) free, switched operational amplifier (op-amp).

I. INTRODUCTION

T HE demand for high-resolution and high-speedanalog-to-digital converters (ADCs) has been con-

tinuously increased for various applications such as CMOSimage sensors, communications, and video analog front-endapplications. In particular, some state-of-the-art digital TVs andcable applications require ADCs with a resolution of up to 12 band a sampling rate exceeding 110 MS/s [1]–[4]. Moreover,the required specifications concerning data conversion speedand resolution are becoming more and more strict in order toobtain higher display resolution and better image quality. Invideo applications, most signal formats are based on a multi-channel configuration. For example, component video signaland RGB PC outputs use three channels. Thus, multiple ADCsare essential in a system-on-a-chip (SoC) to process these videosignals, and the system cost can be reduced depending on theshrinking die size of the ADCs. On the other hand, the powerconsumption of the ADCs is no longer negligible in thoseSoC applications. The total power consumption of the chipalso affects both the reliability and the cost of the employedpackage. As a result, low power consumption and compactsize together with high resolution and high sampling rate have

Manuscript received September 23, 2008; revised December 23, 2008. Firstpublished February 13, 2009; current version published May 20, 2009. Thiswork was supported by the System IC 2010 Project of Korea Ministry of Knowl-edge Economy and the IDEC of KAIST, Korea. This paper was recommendedby Guest Editor A. Chan Carusone.

The authors are with the Department of Electronic Engineering, Sogang Uni-versity, Seoul 121-742, Korea (e-mail: [email protected]).

Digital Object Identifier 10.1109/TCSI.2009.2015200

Fig. 1. Block diagram of a time-interleaved ADC architecture.

been key design issues for the development of a single-chipintegrated system to process high-quality video signals.

Usually, the power consumption and chip size of conventionalADCs tend to be linearly proportional to the conversion speedwithin a specific sampling frequency range. Similarly, the powerconsumption of the ADCs increases with a required resolutionat a given sampling rate. Sometimes, for example, at a sam-pling rate exceeding hundreds of megahertz, the ADCs cannotincrease the conversion speed even though more power is in-vested. A couple of time-interleaved ADCs address such per-formance-limited issues as conversion speed, resolution, andpower consumption [5], [6]. The time-interleaved ADC archi-tecture shown in Fig. 1 is an example of one of the most ef-ficient ways to implement a high sampling rate with moderatepower consumption. The time-interleaved ADC consists ofADCs in parallel, a demultiplexer at the analog input, and a mul-tiplexer (MUX) at the digital output. Each ADC channel oper-ates at a sampling rate of [fs/M]. The transfer function of theADC in each channel needs to be identical while the clock skewis required to be matched for a highly linear signal samplingoperation.

The challenges in the design of high-resolution, time-inter-leaved ADCs come with a couple of constraints associated withstatic and dynamic errors. Static errors are caused by offsetand gain mismatches between channels, while dynamic errorsoriginate from mismatches at a sampling instant. Static errorslimit a signal-to-noise ratio (SNR), independently of inputfrequencies and sampling rates. On the other hand, dynamicerrors result in an input-frequency-dependent SNR degradation.Typically, dynamic errors with a low-frequency input signalare negligibly small in switched capacitor applications. How-ever, static errors always result in destructive problems. Mucheffort has been devoted to overcome the static mismatches.Channel offsets have been cancelled out by well-known analogdomain circuit techniques such as auto-zero offset cancellation,correlated double sampling [7], and chopper stabilization [8].

1549-8328/$25.00 © 2009 IEEE

Authorized licensed use limited to: Sogang University Loyola Library. Downloaded on May 27, 2009 at 23:43 from IEEE Xplore. Restrictions apply.

CHOI et al.: SHA-FREE DUAL-CHANNEL NYQUIST ADC BASED ON MIDCDE CALIBRATION 895

However, those techniques tend to require wideband analogcircuits, and they generate some critical noise issues as well asincrease the total power consumption, particularly in varioushigh-speed video signal applications. Another efficient way toeliminate static mismatches is to apply a calibration techniquein the digital domain [6], [9]–[11]. The calibration-relatedextra circuits increase the complexity, area, and power of theintegrated ADCs. However, the overhead of these circuits canbe scaled down significantly with the development of advancedCMOS technologies and various calibration algorithms.

This study proposes a low-power, dual-channel Nyquistpipeline ADC, which can operate at a sampling rate of120 MS/s with a 1.2-V supply voltage based on a 0.13- mCMOS process. The main focus of this study is on a staticerror reduction due to offset and gain mismatches of thetime-interleaved ADC, rather than a dynamic error reduction.The dual-channel ADC architecture with digital channel offsetcancellation is described in Section II. Low-power circuitdesign techniques for a gain mismatch reduction without cal-ibration are discussed in Section III. The implementation andmeasurement results of the prototype ADC are summarized inSection IV. Finally, conclusions are drawn in Section V.

II. ADC ARCHITECTURE AND CALIBRATION

A. ADC Architecture

One of the most popular schemes to increase a resolution ofpipelined ADCs is a calibration technique regardless of single-channel ADCs or time-interleaved multichannel ADCs. The cal-ibration technique is classified into foreground and backgroundcalibration, depending on the time when calibration is to be per-formed. Conventional foreground calibration techniques sufferfrom a disadvantage that ADCs need to hold operation and becalibrated repeatedly in the middle of operation due to time-de-pendent temperature and voltage variations. For high-resolutionADCs, it takes a long time to be calibrated, and some fore-ground calibration cannot be employed in a specific application.To overcome this shortcoming, background calibration tech-niques without an extra calibration phase have been proposed[12], [13].

However, the background calibration techniques also needa long initial calibration time to obtain a required accurateresolution while calibration logic requires a large area andpower consumption. This paper proposes a foreground mid-code calibration technique with a short calibration time and asmall number of digital logic gates for a small chip size andlow power consumption.

The proposed dual-channel 12-b 120-MS/s ADC is shownin Fig. 2. It consists of an analog demultiplexer at the input,two ADCs in parallel, a midcode calibration circuit, and a dig-ital multiplexer at the output. Each ADC channel operates at asampling rate of 60 MS/s with externally controlled oppositephase clocks, CLK and CLKB. The digital output multiplexerand midcode calibration logic circuits are implemented off chip.

The proposed digital midcode calibration technique com-bined with some circuit designs efficiently eliminates channeloffsets and gain mismatches between two channels with onlyvery limited digital circuitry in the integrated time-interleaved

Fig. 2. Block diagram of the proposed dual-channel ADC.

Fig. 3. Single-channel ADC architecture of Fig. 2.

ADCs [14]. The calibration time and complexity based on theproposed scheme are almost independent of the resolution andconversion speed of the ADC. The offset in each single-channelADC is also reduced by this technique. The single-channel12-b 60-MS/s ADC, as shown in Fig. 2, is detailed in Fig. 3.The ADC consists of five multiplying digital-to-analog con-verters (MDACs), six flash ADCs (FLASHs), an on-chipcurrent reference, and other supplementary circuits. A gainmismatch between channels is minimized by employing asampling-and-hold amplifier (SHA)-free architecture togetherwith a resistor-free FLASH scheme.

B. Calibration

The proposed dual-channel ADC, as shown in Fig. 2,employs off-chip midcode calibration logic, marked as MCCAL, and two clock phases, CLK and CLKB. Calibrationstarts with a control signal CAL switched to high at the input.During this calibration period, the positive and negative analoginputs of each channel are tied together, and external inputsare disconnected from the ADC. The offset error of eachchannel ADC is measured separately by averaging the dig-ital outputs 16 times. Each averaged and rounded off digitalcode is subtracted from the ideal midcode, 2048, and theresults are stored in memory.This foreground calibration procedure takes only 22 clockcycles, including the initial meaningless four clock cycles forthe pipeline delay. During normal conversion, each measuredand stored offset is subtracted from the raw digital outputsof each channel ADC, and the calibrated digital output fromeach channel is time-interleaved by the digital MUX blockat the output. Off-chip digital calibration logic for midcodecalibration can be implemented with a simple structure, which



Fig. 4. Functional description of a midcode digital calibration �� (a) before and (b) after calibration.

corrects only one code. It occupies less than 500 logic gates fora calibration range of 128 codes which eliminate a channeloffset voltage of mV level.

The digital midcode calibration concept is briefly describedin Fig. 4. Fig. 4(a) shows the measured patterns of the prototypeADC before calibration. The output of each channel is shiftedby and , respectively, and shows a dccomponent in the fast Fourier transform (FFT) spectrum. Withthe time-interleaving technique, the dc component is modulatedat the zero frequency, and a spurious tone appears at [fs/2]. Again mismatch between channels results in a spurious compo-nent at [fs/2-fin] in the FFT plot of the time-interleaved outputs,but it does not show up in each single-channel ADC. It signif-icantly degrades the SNR performance of the prototype ADC,and the effective resolution is limited up to around 8 b or less. Atiming mismatch can also cause a spurious tone at [fs/2-fin] inthe same way as a spurious component due to a gain mismatch.In this work, since this tone to be generated by a timing mis-match is minimized by carefully controlled external clocks, thetone at [fs/2-fin] is composed of a spurious component resultingfrom a gain mismatch. The normalized minimum magnitude ofeach noise tone can be summarized as [15].

(1)

(2)

The spurious tone due to a gain error of in (2) comesprimarily from the average gain difference between the twoADC channels. The proposed midcode calibration removesoffsets such as and . After calibration,as observed in Fig. 4(b), the dc component of each channeloutput and the spurious tone at [fs/2] of the time-interleavedoutputs are simultaneously reduced in the FFT plot.

The proposed midcode calibration technique needs the lin-early increased number of digital logic gates depending on theinterleaved number of ADC channels used for high speed oper-ation. The fact that the required calibration time remains con-stant even with the increased number of channels makes theproposed foreground calibration technique adequate for manyapplications.

III. ADC CIRCUIT DESIGN

A high unity-gain frequency required for analog circuits suchas operational amplifiers (op-amps) can be obtained using thingate oxide and short-channel active devices with a reduced para-sitic capacitance and a smaller device dimension resulting fromthe downscaling of CMOS technology. This offers low-powerconsumption as well as high-speed operation. However, thesemerits also come with demerits, which are not critical in theconventional design but should be overcome by other advancedcircuit techniques in the new era of deep-submicrometer tech-nology [16]. First of all, the variation of switch on-resistance de-pendent on signal levels significantly limits the linearity of sam-pled inputs in low-voltage applications, and restricts the accu-racy of circuits in high-speed operations. Second, noise perfor-mance is considerably degraded with a reduced voltage range.In other words, a reduced signal swing decreases the SNR due tothe noise power, independent of the power supply. Finally, offsetvoltages are increased due to the short channel length and smalldevice dimension. Offset reduction requires additional circuitdesign schemes such as calibration or offset cancellation usingan auto-zero function. In this study, a gate-bootstrapping tech-nique is employed to improve the high-speed input samplingperformance [17] while an op-amp with a high signal swing isused to address the noise problem. As discussed in Section II,the proposed calibration technique eliminates channel offsets.

As for the conventional pipeline ADCs, primary gain errorscome from the nonlinear op-amp in the input SHA as well as



Fig. 5. Simplified input sampling network based on MDAC1 and FLASH1.

the unmatched top and bottom reference voltages supplied toeach functional circuit block. This study proposes an SHA-freeinput sampling network to eliminate the major channel-gainmismatch error resulting from a mismatched SHA gain. Thegain mismatch can occur due to a reference voltage differencebetween channels. A resistor-free FLASH ADC architecture isproposed to remove the non-linear reference voltage mismatcheffect due to the parasitic resistance of interconnection metallines. An op-amp gain error of the MDAC1 may cause an othergain mismatch between channels as well as a linearity error of asingle channel ADC. However, the error can be maintained neg-ligibly small if each single-channel ADC is designed efficientlyto suppress the linearity error due to the first stage MDAC toless than 1 LSB, which is very common and essential for asingle-channel ADC design. The circuit design techniques toreduce a gain error without calibration, while maintaining a lowpower dissipation, are proposed and discussed in the followingsubsections.

A. Input Sampling Network

In the proposed SHA free architecture, as shown in Fig. 5,analog inputs are sampled directly at the MDAC1 and FLASH1.When a mismatch occurs between the input sampling time of thecapacitor array in the MDAC1 and that of the comparator arrayin the FLASH1, the maximum allowable input frequency forno-missing code performance is restricted. The input samplingnetwork proposed in Fig. 5 allows a precisely matched samplingtime for the MDAC1 and FLASH1 to obtain a high-frequencyinput sampling even without an SHA. The sampling time mis-match is minimized by synchronizing the sampling time of theswitches connected to the bottom plate of each capacitor in theMDAC1 and FLASH1 employing a bootstrapped clock ,thus making sampled inputs maintain a good linearity.

A sampling time error between the MDAC1 and FLASH1commonly leads to missing codes. Comparator offsets ex-ceeding the decision-error correction range of the FLASH1generate the same kind of missing codes. The maximum allow-able input frequency for no-missing code is derived as follows:

(3)

(4)

(5)

Fig. 6. Simulated conditions of input frequency, sampling time mismatch, andcomparator offsets for no-missing code based (a) on MDAC1 with no offset and(b) on MDAC1 with an offset voltage of 15 mV.

In (5), is the sampling time mismatch between the MDAC1and FLASH1. The is the tolerable offset voltage inthe ADC and is calculated as follows:

(6)

In (6), is the maximum allowable offset voltage withno sampling time mismatch. In the proposed SHA-free ADCarchitecture, the value of needs to be 62.5 mV toguarantee no-missing code. The and are theoffset voltages of the MDAC1 and FLASH1, respectively. Asshown in (5) and (6), a maximum achievable input samplingfrequency is limited by the offset errors of the MDAC1 andFLASH1 as well as the timing mismatches between the MDAC1and FLASH1. Thus, a maximum allowable input frequency withan MDAC1 offset voltage of and a FLASH1 offsetvoltage of is calculated as follows:

mV(7)

In Fig. 6, the required conditions of input frequency, timingmismatch, and offsets of the MDAC1 and FLASH1 are de-scribed to achieve no-missing code with a V input signalat a 12-b resolution. As shown in Fig. 6(a), input frequenciesfor no-missing code are corelated and analyzed with timingmismatch errors and FLASH1 offset voltages of 0–30 mVwhen the MDAC1 has no offset error. For example, the timingmismatch of the MDAC1 and FLASH1 should be limited to lessthan 0.33 ns in order to process a high-frequency input signalof 60 MHz, even if the MDAC1 and FLASH1 are ideal withoutany offset voltages. On the other hand, Fig. 6(b) shows the inputfrequencies related to tolerable sampling time mismatches andcomparator offsets with a given MDAC1 offset of 15 mV.The simulated results of Fig. 6(b) show that the samplingtime mismatch should be less than 0.09 ns with offset voltagemismatches of 15 and 30 mV in the MDAC1 and FLASH1,respectively, in order to properly handle a 60-MHz Nyquistinput signal in the proposed 12-b ADC.

B. Resistor-Free Comparator

The proposed ADC is composed of six pipeline stages, andeach stage is based on a 2.5-b/stage midrise coding technique,as illustrated in Fig. 7. The small triangles in Fig. 7 representcomparators. Three comparators between DREF and -DREF are



Fig. 7. Coding technique of the proposed ADC.

Fig. 8. FLASH architecture. (a) Capacitor-divided latched comparator. (b) Pro-posed 2.5-b FLASH scheme.

used for normal conversion, while the top and bottom compara-tors from stage 2 to stage 6 are needed for error correction.

Each FLASH is based on a capacitor-divided (C-DIV)comparator instead of a conventional resistor ladder-basedcomparator, as shown in Fig. 8(a). The schematic of the pro-posed C-DIV based FLASH circuit is illustrated in Fig. 8(b).With the proposed latched comparator, all the FLASHs arefree from having a resistor divider, which can cause a gainerror in the ADC due to a voltage drop of reference voltagesthrough interconnection line currents. Each input node in theproposed comparator of Fig. 8(a) and (b) employs two separatecapacitors, but the capacitors are connected only to the topand bottom reference voltages, and , selectively.All the FLASHs consist of the same C-DIV type comparators,and the bootstrapped clocks, and , are appliedonly to the first FLASH in order to deal with a sampling timemismatch.

Fig. 9. Two-stage switched op-amp for MDAC1.

C. Two-Stage Switched Op-Amp

As shown in Fig. 9, the MDAC1 employs a two-stage op-ampto achieve a high signal swing with the required high dc gain.Since op-amps are the most power-hungry analog circuits inthe pipeline ADC, a cascoded compensation technique [18] andswitched op-amp techniques [19] are adopted to minimize thepower dissipation of the op-amps. During the sampling phase,transistors M3, M4, and M7 operating as switches are turnedoff. At the same time, both differential outputs, and

, are set to a common-mode voltage of VCOM by tran-sistors M5 and M6. The gate of M9 is connected to VB5 throughM8 to achieve a fast settling of each node in the next ampli-fying phase while maintaining the power off status. Right be-fore the amplifying phase, M7 is turned on first, and M3 andM4 are turned on to amplify input signals at the beginning ofthe amplifying phase. This slight timing difference between M7and M3–M4 is needed to reduce the power consumption of theop-amp without degrading the settling time. It is noted that thedynamic common-mode feedback (CMFB) circuit proposed inthe second stage op-amp consists of only two capacitors andthree switches, as shown in the shadowed area of Fig. 9. Theproposed CMFB circuit requires half the components that theconventional switched-capacitor based CMFB circuit [20] does.The CMFB circuit reduces a chip size and power consumptionby lowering the output loading capacitance. The total powerconsumption and chip area of the ADC are reduced by approx-imately 30%, compared to conventional ADCs with a similarpipeline architecture, based on the proposed switched op-ampand the simplified CMFB circuit.

IV. ADC IMPLEMETATION AND MEASUREMENTS

The prototype ADC is fabricated in a 0.13- m CMOSprocess. Both of the dual channels are symmetrically laid outas illustrated in Fig. 10. Each individual ADC independentlyintegrates all of the functional circuit blocks and does notshare any circuit blocks to avoid any potential crosstalk noisebetween each channel. Dummy capacitors are laid out only inthe capacitor array of the MDAC1 to obtain good capacitormatching accuracy, which is very critical to maintain 12-b-levelADC linearity. The reduced number of dummy capacitorsand the resistor-free FLASHs minimize the area of passivecomponents occupying a relatively large portion of the entire



Fig. 10. Die micrograph of the proposed dual-channel ADC.

Fig. 11. Measured DNL and INL of each ADC channel. (a) A Channel.(b) B Channel.

Fig. 12. Measured DNL and INL of the proposed dual-channel ADC (a) beforecalibration and (b) after calibration.

ADC chip area. The active die area of the dual-channel ADC,excluding off-chip calibration logic, is mm .

Figs. 11 and 12 illustrate the measured static linearity per-formance of two separate ADC channels and the dual-channeltime-interleaved ADC, respectively. The proposed dual-channel

Fig. 13. Measured FFT spectrums of each ADC channel. �� MHz� � � �� MHz�. (a) A Channel. (b) B Channel.

Fig. 14. Measured FFT spectrums of the proposed dual-channel ADC �� MHz� � � �� MHz�. (a) Before calibration. (b) After calibration.

ADC shows better linearity than each separate single-channelADC, since the random linearity errors of each single-channelADC are also averaged out. The proposed offset calibration doesnot move toward any significant improvement of the linearity, asshown in Fig. 12.

The FFT spectrums of two single-channel ADCs and thedual-channel ADC are plotted in Figs. 13 and 14, respectively.The plots of Fig. 13 are measured with an 8192-point FFT, andthe plots of Fig. 14 are measured with a 16 384-point FFT. Theinput signal frequency is 4.5 MHz, while the sampling rate ofeach single channel is 10 MS/s to achieve a 20-MS/s samplingrate in the overall ADC. The spurious components of the dottedcircle at [fs/2-fin] in the left-hand side of Fig. 14(a) and (b) arecaused by a gain mismatch between channels in the time-in-terleaved ADC. The value of 84.5 dBc representing a gainmismatch is negligibly small at a resolution of 12 b and isalmost independent of calibration. On the other hand, theharmonic component at [fs/2] indicating an offset mismatchis 49.8 dBc before calibration, which limits the spurious-freedynamic range (SFDR). The measured channel offset of theprototype ADC corresponds to 13 LSBs at 12 b. The offsetspurious tone is improved to 80.9 dBc from 49.8 dBc afterthe proposed midcode calibration. The proposed midcodecalibration reduces the dc component as well as the harmoniccomponent at [fs/2] caused by an offset mismatch. Aftercalibration, as observed in Fig. 14, the dc component of thetime-interleaved outputs is reduced to 70.2 dBc from 56.4 dBc.

The signal-to-noise-and-distortion ratio (SNDR) and SFDRversus sampling frequencies for a 4.5-MHz input are plotted in



Fig. 15. Measured SNDR and SFDR.

Fig. 16. Measured FFT spectrums with Nyquist input (fs � ��, � �� MHz).

Fig. 17. FOM of recently reported 12-b ADCs with a sampling rate exceeding50 MS/s.

Fig. 15. The SNDR and SFDR maintain a reading of better than60 and 70 dB up to a sampling rate of 120 MS/s, respectively.

The dual-channel prototype ADC consumes 51.6 mW ata nominal condition of 120 MS/s and 1.2 V. The measureddifferential nonlinearity (DNL) and integral nonlinearity (INL)of the calibrated dual-channel ADC are within LSBand LSB, respectively. The measured SNDR and SFDRare 63.6 and 81.0 dB, respectively, with an input frequencyof 4.5 MHz and a sampling rate of 20 MS/s. At a samplingrate of 120 MS/s, the measured SNDR and SFDR are 61.1and 74.7 dBc, respectively, for a 59.9-MHz input frequency asshown in Fig. 16. It is measured with a 16 384-point FFT.

Fig. 17 illustrates a figure of merit (FOM) versus samplingrate of recently reported 12-b CMOS ADCs with a sampling

TABLE IPERFORMANCE SUMMARY OF PROTOTYPE ADC

rate exceeding 50 MS/s, where the FOM is defined asfollows:

(8)

The FOM of the proposed ADC is 0.46 pJ/conversion-step.The proposed ADC performance is summarized in Table I.

Off-chip digital calibration logic needs a logic gate count of 500for a calibration range of 128 codes, which requires a small ad-ditional chip area less than 0.01 mm and a power consumptionof 1 mW.

V. CONCLUSION

This study proposes a 12-b 120-MS/s dual-channel ADCbased on a midcode calibration scheme, which eliminatesan offset mismatch between channels. The ADC employsSHA-free as well as resistor-free architectures simultaneouslyto achieve both a reduced gain mismatch between channels anda small die area. The implemented 12-b Nyquist-rate 0.13- mCMOS ADC shows a power consumption of 51.6 mW and anactive die area of 0.56 mm at a 120-MHz sampling rate.

REFERENCES

[1] T. Ito, D. Kurose, T. Ueno, T. Yamaji, and T. Itakura, “55 mW 1.2 V12 bit 100-MSPS pipeline ADCs for wireless receivers,” in Proc. Eur.Solid-State Circuits Conf., Sep. 2006, pp. 540–543.

[2] C. Michalski, “A 12 b 105 Msample/s, 850 mW analog to digitalconverter,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2000, pp.208–211.

[3] T. N. Andersen et al., “A cost-efficient high-speed 12-bit pipeline ADCin 0.18-�m digital CMOS,” IEEE J. Solid-State Circuits, vol. 40, no.7, pp. 1506–1513, Jul. 2005.

[4] S. M. Yoo, T. H. Oh, H. Y. Lee, K. H. Moon, and J. W. Kim, “A 3.0 V12 b 120 Msample/s CMOS pipelined ADC,” in Proc. IEEE Int. Symp.Circuits Syst., May 2006, pp. 1023–1026.

[5] W. C. Black, Jr and D. A. Hodges, “Time interleaved converter arrays,”IEEE J. Solid-State Circuits, vol. SC-15, no. 6, pp. 1022–1029, Dec.1980.

[6] S. M. Jamal, D. Fu, N. C.-J. Chang, P. J. Hurst, and S. H. Lewis, “A10-b 120-Msample/s time-interleaved analog-to-digital converter withdigital background calibration,” IEEE J. Solid-State Circuits, vol. 37,no. 12, pp. 1618–1627, Dec. 2002.

[7] C. Enz and G. Temes, “Circuit techniques for reducing the effects ofopamp imperfections: Autozeroing, correlated double sampling andchopper stabilization,” Proc. IEEE, no. 11, pp. 1584–1614, Nov. 1996.

[8] C. C. Enz and E. A. Vittoz, “A CMOS chopper amplifier,” IEEE J.Solid-State Circuits, vol. SC-22, no. 3, pp. 335–341, Jun. 1987.

[9] C. R. Grace, P. J. Hurst, and S. H. Lewis, “A 12-bit 80-MSample/spipelined ADC with bootstrapped digital calibration,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1038–1046, May 2005.



[10] Z. M. Lee, C. Y. Wang, and J. T. Wu, “A CMOS 15-bit 125-MS/stime-interleaved ADC with digital background calibration,” IEEE J.Solid-State Circuits, vol. 42, no. 10, pp. 2149–2160, Oct. 2007.

[11] S. Huang and B. C. Levy, “Adaptive blind calibration of timing offset andgain mismatch for two-channel time-interleaved ADCs,” IEEE Trans.Circuits Syst. I, Reg. Papers, vol. 53, no. 6, pp. 1278–1288, Jun. 2006.

[12] J. Yuan, N. Farhat, and J. Van der Spiegel, “Background calibrationwith piecewise linearized error model for CMOS pipeline A/D con-verter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 2, pp.311–321, Feb. 2008.

[13] J. L. Fan, C. Y. Wang, and J. T. Wu, “A robust and fast digital back-ground calibration technique for pipelined ADCs,” IEEE Trans. Cir-cuits Syst. I, Reg. Papers, vol. 54, no. 6, pp. 1213–1223, Jun. 2007.

[14] H. C. Choi, Y. J. Kim, S. W. Lee, J. Y. Han, O. B. Kwon, Y. L. Kim, andS. H. Lee, “A 52 mW �� mm 1.2 V 12 b 120 MS/s SHA-free dual-channel Nyquist ADC based on midcode calibration,” Proc. ISCAS, pp.9–12, May 2008.

[15] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K.Kobayashi, “Explicit analysis of channel mismatch effects in time-in-terleaved ADC systems,” IEEE Trans. Circuits Syst. I, Fundam. TheoryAppl., vol. 48, no. 3, pp. 261–271, Mar. 2001.

[16] S. C. Lee, Y. D. Jeon, and J. Kim, “A 10-bit 205-MS/s ��mm 90-nmCMOS pipeline ADC for flat panel display applicxations,” IEEE J.Solid-State Circuits, vol. 42, no. 12, pp. 2688–2695, Dec. 2007.

[17] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipelineanalog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no.5, pp. 599–606, May 1999.

[18] B. Ahuja, “An improved frequency compensation technique for CMOSoperational amplifiers,” IEEE J. Solid-State Circuits, vol. SC-18, no. 6,pp. 629–633, Dec. 1983.

[19] H. C. Choi, J. H. Kim, S. M. Yoo, K. J. Lee, T. H. Oh, M. J. Seo, andJ. W. Kim, “A 15 mW �� mm 10 b 50 MS/s ADC with wide inputrange,” in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 226–227.

[20] R. Castello and P. Gray, “A high-performance micropower switched-capacitor filter,” IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp.1122–1132, Dec. 1985.

Hee-Cheol Choi was born in Seoul, Korea. He re-ceived the B.S., M.S., and Ph.D. degrees in electronicengineering from Sogang University, Seoul, Korea, in1994, 1996, and 2009, respectively.

From 1996 to 2006, he was a Senior Engineer withSamsung Electronics. He is currently a Senior En-gineer with Aptina Korea. His work focuses mainlyon sensor chip design, and his current interests arehigh-resolution low-power CMOS data convertersand analog front ends for video signal processing.

Young-Ju Kim (S’08) received the B.S. and M.S. de-grees in electronic engineering from Sogang Univer-sity, Seoul, Korea, in 2005 and 2007, where he is cur-rently working toward the Ph.D. degree.

His current interests are in the design of high-res-olution low-power CMOS data converters and veryhigh-speed mixed-mode integrated systems.

Mr. Kim was the recipient of the HumanTechThesis Contest Silver Award from Samsung Elec-tronics Corporation in 2007.

Gil-Cho Ahn (M’96) received the B.S. and M.S. de-grees in electronic engineering from Sogang Univer-sity, Seoul, Korea, in 1994 and 1996, respectively,and the Ph.D. degree in electrical engineering fromOregon State University, Corvallis, in 2005.

From 1996 to 2001, he was a Design Engineerwith Samsung Electronics, Kiheung, Korea, workingon mixed analog and digital integrated circuits.From 2005 to 2007, he was with Broadcom Cor-poration, Irvine, CA, working on AFE for digitalTV. Currently, he is an Assistant Professor with

the Department of Electronic Engineering, Sogang University. His researchinterests include high-speed, high-resolution data converters and low-voltage,low-power mixed-signal circuits design.

Dr. Ahn received the Analog Devices Outstanding Student Designer Awardin 2003.

Seung-Hoon Lee (M’91) received the B.S. and M.S.degrees ) with honors) in electronic engineering fromSeoul National University, Seoul, Korea, in 1984 and1986, respectively, and the Ph.D. degree in electricaland computer engineering from the University of Illi-nois, Urbana-Champaign, in 1991.

From 1990 to 1993, he was with Analog DevicesSemiconductor, Wilmington, MA, as a Senior DesignEngineer. Since 1993, he has been with the Depart-ment of Electronic Engineering, Sogang University,Seoul, Korea, where he is now a Professor. He has

been serving as the Chief Editor of the IEEK Journal of Semiconductor De-vices, Circuits, and Systems and a TPC member of many international and do-mestic conferences including the IEEE Symposium on VLSI Circuits. His cur-rent interest is in the design and testing of high-resolution high-speed CMOSdata converters, CMOS communication circuits, integrated sensors, and mixed-mode integrated systems.


Documents

894 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: …eeic7.sogang.ac.kr › paper file › international journal... · 2009-05-28 · 894 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: