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A 250M Hz clock for SOC systemsBoanLiu , ..Chen Ji i.

. . , . i 'liistitiite of Microelectronics Tsingliua U niversity , .. . ,Beijing P.R.C ' ' . I. BeijingP.R.C ' , ., . . .~

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I 1. . .. .A h . q d - T h i s pqIeq introduces a methoi to ' (PSRR) greater than SOdB while VCO Oiierating atimplement a phase-locket1 lool) (PLL) based on ring frequencies about , 1 G H i And it is in layout. T h e .oscillator. In order to reject the ,jitters, a .voltage system will be integrated in a'O.25-um 2-poly 5-metiilwhich is the mnst cnmmnn and do minant, souwe of,,jitter. The simulation result s h o w t h at t h e voltage Inder Ternis-Clock generator, PLL, voltageregulator cm achieve a power-supply rejection ratio

rep la r is appl ied tu reduce the ~io \~e r-su pp lyoise, digital CMOS technolo=. . .,. ,

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I . INTRODUCYIONIn SOC systems. both analog and digital systems existDigilal parls niay cause l l ie Yoltage supply variations.TI& iiiay affcct tlic ah lo g parts ' perfonnance,including PLL. To rcgolate the supply of 11c PLL isan effective inclliod lo niiiiimizc tlic jittcr. Previouswork h a s slio\vii that the PL L acliieves a PSRR greaier!hnn 40 dB while operating at frcqocncies exe cd in g 4GHz. The high lcycl of noise rcieclion cxcceds that ofearlier dcsigns by &iig il conibini~tion f both passiveand active filteiiiig of the PLL's analog supply

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voltage. The' PLL systeili has been iutegrated 'in a(I . 15 - I-I 111 single-poly 5-nictal digital CMOSteclinolopy. The iiicasured perfoniiancc indicates thepeak cycle-to-cycle jitter is 23 ps at 700 MHz ai id a2.8-GHz VCO freqiienc!- with a 500-mV stcp 011 th ercgulator's 3 .3 -V siipply)l . Doe to differenttechnology. there are sonic differcnces in designconsiderations.11. PLL DESIGNI n a 0.25-111112 p o l y 5iiielal digital CMO S technology.

' . . , . 'I. i ,.. . , .,.. . , . ..,0-7803-7889-X/03/$17.0002003 IEEE. 72

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the digital supply is 2.5V, and the U0 supply is 3.3V. Ablock diagram of thc clock is shown in Fig.1. All digitalparts. including those in PLL. are powered using a 2.5Vsupply. The regu lator is powered using a dedicated 3.3Vsupply that is shared at the boaid level by a portion ofthe SOC's IiO circuit blocks. The regulator filters thissupply and produces a constant nominally noise-freesupply of approximately 2.2 V and 2.7V. The se suppliesare used to power the PLL's noisesensitive charge pumpand voltage contnlled oscillator (VCO)[I].A . V C O D e s i g nThe VCO, slloivn in Fig.2. consists of a tluee-stagesingle-ended ring oscillator that is controlled using acumlit-numr topology[l]. For inverts: in order tomaximize the noise margins and obtain symniehicalchara cteristics . it is necessary to make the PMO S section( k, I k,, ) times wider than the NMOS section. Theinverters can be modeled as first-order RC nehvorks. Inswitches, the PMOS and NMOS transistors can beassumed to be in die saturation and linear regions.respectively[2]. In linea r regions.1 (1)

c - W L ( 2 )WL

R", = /lem- VG8-VTH)So the pro pagation delay is propo rtional to L 2 , so didthe period of the oscillator. Nes t are the steps todetermine the dimensions o f each transistor. First, afterscanning parameter 6 and the width and length of thetransistors in the oscillator. different frequencies are gotat different p< . w a n d L . n typical comer. This willhelp to deteniun e the dimem ions of M, M,nd M ,_~vluch onsmct a siinple amplifier. They shouldvre92

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' IL 1Fig.2 Voltage-controlled o scillator

work in the saturated region. Second. due to the effectsof ss comcr and ff comcr. it is not fcasiblc to sct thcminimum length for each transisto r in the oscillator. In sscomer, set the width of the transistor as small as possibleand the highest frequency is got. Third. in condition ff.keep the length of those transistors in the oscillator andmake the width wider, the lowest frequency in the ffcondition is got. Fourth, regulate the dimensions ofM,M 2 nd M , in order to milliin ize, l;e v aria tion inP;'when o scillator working.B.. , Shif ter DesignIn order to detect and check a period of the oscillator. thethreshold of the inverter in the shifter must be se tcarefully. In ss comer. when frequency reaches IGHZthe peak inay reach 1.8% wlule in ff condition, in thesame frequency. the peak is only 1.3V. so the propertlucsliold of the inverter should be 0.9V Moreinfomation about other parts' design, Please refer to[I].

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111. VOLTAGE REGULATOR DESIGNA block diagram of the voltage regulator is shown inFig. 3 . A reference. generated by a bandgap g enerator. isused to adjust the PLL's voltage by being amplified byan op era t io d ampl if ie r. There are two amplifiers in thedesign. One is to regulate a 2.2V voltage for the charge

pump. the shifter and the pre-slufter, and the other is toregulate a 2.7V voltage for the VCO. Mcsl andMcs2am transistors to provide big current for those parts,respectiwly. Ictrl and Ictrl2 are used to discharge thesuperfluous current so that tbe voltage of PLL is heldproperly. not'too high. In order to stabilize the supplyvoltage. Cdl and Cd2 areused[l].A . Voltage Regulator DesignFirst. in different com ers and un der different voltages. allparts.of the PLL are siioulated in ord er to get conditionson that PLL could work properly. Second. consider theamp lifier and the regu lator transistor. which c o n s e c t a namplifier system. They and the two feedback ksistok.fon n a negative feedback system. Cdl and Cd2 q e sedto provide current when PLL ne eds big cu rrent wlule :notreducing'the voltage of PLL. Third. due t o ' a voltagefeedback system.

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To achieve a gain error less than 1%. > 10000. In122

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tile Same tilne. fo r y n = o,,(t) the outputresponse can be exp ressed as

Fbiutli. from above, Cdl=CdZ=jjOpf: the dc gain of thefirst amplifier is set to SO&: its unih-gain is set toI O OMHZ .

Rl -tR. Tb;,,,,(t)=n(l+-)(I-exp-)o(t) .(I).

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B. Op am p des ign

GND &Fig.3 Voltage regulator block diagram

headroom, The schematic shown in Fig.4. consists oftwo stages, and gain boosting is employed[l][.l].b.3

Fig. 4 Master op ampFig. 5 Slave op amp with comm on mode feedbackEach op amp is implemented using the folded-cascode

bandwidth without consuming tlie excessive amount oftoPolog?. order to pro\'ide the lagestossible In additional al~lplifier,in order to generate stabilizedfeedback voltage, two torrent as cOlnlnOn node

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feedback iinpleincnted by hvo transistors are used.slionn in . Fig.51.i]15]. First. according to tlic differenttlircshold o r lransisiors in difkrent com e= and the . .point. Second. clioose transistors ,in nuniinnm length.check if rlie? meet tlic design requirements. Tlird.cliange the bias ciinrnt and check the designrequircments. Fonli. keep llie ratio (w L . regulate the\\ idtli and lcngtl~ r the transistors Fifth. check if thepon cr meets Ilie design requircmenls.

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IV . SIMULATION RESULTSSimulations show each op amp's DC gain exceed 8OdB

i n different camerr and its i inih gain are beyondIOOMHz. The noise rejection perfon nance of tlie voltageregulator is 5hdB in ty p corner. 5ldB in ff corner and59dB in ss corner, Jitter simulations were perfonliedwith n VCO rrcquency or IC Hz and an outpntCrequency of ZJOMHz. For the case of ideal Vregl andVreg2. the jitter is 4 . 2 7 ~ ~ .nd fo r the case of nominallyquiel sopply. the jitter is 4.i24ps. When a i0O-niv step isi:!jccled onto tlie re y la lo r' s 3 . 3 ~upply. the jitter is4.i72ps.

FUTURE WORKA bandgap gcnento r i s needed and the protohpe

\ \ i l l be iii layout. , . .R E F E R N E C E

[ I I Joseph M. Ingino. Viiicent R. van Kaenel. "A.4-GHzClock Syslcni for a High-Perronnance s::steni-on-a-CldpDcsign" IEEE JOURNAL OF SOLID-STATECIRCUITS. VOL. .X.NO . 11 . pp . 1693-1698.NOVEMBER 2tWl121 Ja n M. Rabacy. Digital Integrated Circuits(photocopy cdilion)_PRENTICE HALL. 1998.131 Bellzad R a m i . Design or Analog CM OS IntegratedCircuits. McGRAW-HALL INTERNATIONALEDITION. 2001 j141 K. Bult m d G. Ge ek n. :A fast-settling CMOS opainp fo r SC circu its with 'IO-dB DC gain." IEEE .I,Sdid-,Yrok! c' imti!.