A 0.2-11.7GHz, High Accuracy Injection-Locking Multi-Phase Generation with

Mixed Analog/Digital Calibration Loops in 28nm FDSOI CMOS

G. Anzalone, E. Monaco1, G. Albasini1, S. Erba1, A. Mazzanti

Dipartimento di Ingegneria Industriale e dell’Informazione, Università di Pavia – Italy1Studio di Microelettronica, STMicroelectronics, Pavia – Italy

Motivations

Increasing data center traffic is pushing data rate higher and higher.

Interconnected servers, switches and routers are the core of the Internet of Things society. 2

Clock generation in high speed links

New standards with data rate of 25Gb/s and beyond require:• Multiphase clocks • High phase accuracy• Wide tuning range• Low Power• Robustness against voltage and temperature variations

Clock generation is becoming more and more challenging. 3

Outline

• Multiphase generation with ILRO

• Proposed architecture

• Circuits design

• Experimental results

• Conclusions

4

Multiphase generation

5

Advantages of ILRO:• Ease of multiphase generation compared to poly-phase filters and frequency

dividers.• No discontinuity at the input/output as in DLL.

Weakness of ILRO:• Phase error when the input frequency is different from the free running value• Sensitivity to temperature and supply variations.

Injection Locked Ring Oscillator

(ILRO)

Phase error in ILRO

6

• The four output differential phases are equally spaced by:

• The phase shift between output phases is:

= +

Phase error in ILRO

7

• The four output differential phases are equally spaced by:

• The phase shift between output phases is:

= +

drifts when temperature and supply change, increasing the phase error ϕ . φ 9

0[°

]

8

Outline

• Multiphase generation with ILRO

• Proposed architecture

• Circuits design

• Experimental results

• Conclusions

8

Proposed architecture

9

An analog loop compensates for temperature and supply variations:• A phase detector providing a signal proportional to the quadrature phase error.• This signal ( ) shifts the free-run frequency to minimize the error.

Analog tuning range is relatively low to keep low KVCO and avoid false locking issues

Proposed architecture

10

To overcome the analog loop limits an additional digital loop is implemented:

• A window comparator monitors and drives an up/down register that modifies the frequency coarse code.

• When exits the interval , , a digital calibration step is delivered in order to bring it back within the wanted interval.

Outline

11

• Multiphase generation with ILRO

• Proposed architecture

• Circuits design

• Experimental results

• Conclusions

Circuit design: ILRO

12

•Three differential pairs compose four identical stages.

•Analog tuning performed by transistor , driven by .

•Tuning curve linearity improved by two resistor in series to .

•Unity / ratio: - good free-run phase noise suppression

- limited clock skew.C

lock

ske

w [U

I,%]

Circuit design: phase detector

13

• Current mode passive mixers limits the 1/f noise.

• The mixers differential output current is fed into a trans-impedance amplifier.

• The equivalent loop gain is given by:

G when

JSSC2013 Univ. of Padova

Low phase noise design

14

Both ILRO and phase detector have been carefully designed in order to achieve very good phase noise performances when the loop is active:

< -110dBc/Hz@10kHz

< -130dBc/Hz@1MHz

Outline

15

• Multiphase generation with ILRO

• Proposed architecture

• Circuits design

• Experimental results

• Conclusions

Experimental test-chip

16

• 28nm FDSOI CMOS process from STMicroelectronics.

• 1V VDD supply

• Active area: 220umX130um.

• Frequency range: 0.2 – 11.7GHz.

• Maximum power consumption: 15mW.

Phase error over VT variations

17The quadrature phase error is kept lower than 1.5°.

Phase noise measurement

18• Integrated phase noise from 10kHz to 1GHz result in 139fs of rms jitter.

Phas

e N

oise

[dB

c/H

z]

Comparison with state of the artVLSI2014

ISSCC 2015

CICC2011

JSSC 2009

JSSC 2009 This Work

ArchitectureQuadrature 8-phase generators

DLL ILRO Open Loop ILRO ILRO ILRO

Technology CMOS 14nm

CMOS FDSOI 28nm

CMOS 65nm

CMOS 90nm

CMOS 65nm

CMOS FDSOI 28nm

Frequency [GHz] 2 – 7.5 4 – 11 8 – 12 2 – 7 3 – 5.6 0.2 – 11.7

Power [mW] 4.4 @7GHz

2.77 @11GHz

14.8 @10GHz 14 5.88 –

11.7615

@11.7GHzPhase Error [°] NA 1.5 2.3 – 3.9 NA 2 <1.5

Background Calibration

Yes Yes No No No Yes

Jitter [fs]

98 @7GHz (10kHz –1GHz)

558 @8GHz (100kHz – 1GHz)

470 NA NA

139 @8GHz (10kHz –

1GHz)Power/GHz/#phases 0.16 0.06 0.19 0.25 0.26 0.16

Outline

20

• Multiphase generation with ILRO

• Proposed architecture

• Circuits design

• Experimental results

• Conclusions

Conclusions

21

• Injection locking of ring oscillators (ILRO) allows accurate multi-phase generation, but only if input signal frequency matches the free-run frequency.

• Proposed analog and digital calibration techniques enable high phase accuracy over ultra wide tuning range and improve robustness to supply and temperature variations.

• A test chip in 28nm FDSOI CMOS demonstrated 0.2 to 11.7GHz with <1.5° phase error over +/-20% supply and -40° / 120°temperature variations.

• The ILRO meets the performance requirements of 1-to-45Gb/s quarter-rate multi-standard I/O transceivers with a state-of the art power efficiency.

22

Chip architecture and Measurement Setup

23In order to measure the effective phase error at the ILRO outputs, a secondary path has been inserted to bypass the oscillator and de-embed the surrounding stages.