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Voltage References for Ultra-Low Supply Voltages

P. Kinget, C. Vezyrtzis, E. Chiang, B. Hung* and T.L. Li*

Dept. of Electrical EngineeringColumbia University

New York, NY 10027, USA

*United Microelectronics, Taiwan, R.O.C.

Abstract —The majority of integrated voltage references have, so

far, been limited to a minimum supply voltage above 0.7-V often

due to the voltage headroom required for the forward-biased

operation of a PN-junction. This paper reviews design techniques

for low voltage reference design and explores the feasibility of

designing a voltage reference with a supply voltage below 0.7-V

in a standard CMOS process. Two ultra-low-voltage solutions are

explored in detail, a reference circuit based on CMOS compatible

Schottky diodes and a MOS-only reference circuit.

I. I NTRODUCTION

Voltage references are indispensible building blocks ofmany analog and mixed-signal system-on-a-chip integratedcircuits. They provide references for on-chip powermanagement blocks, for signal conditioning and signalmeasurement, or for building blocks such as ADCs and DACsand further make possible the appropriate biasing of analogcircuits so that they become much less unaffected by process,temperature and voltage (PVT) variations. Parts of referencecircuits can further often be configured to serve as on-chip dietemperature monitors, e.g. on large digital microprocessors.

The continued scaling of transistor dimensions in CMOStechnologies in combination with the need to reduce powerdensity in large digital ICs is driving down the supply voltagefor nanoscale CMOS technologies. Supply voltages well

below 1V and even down to 0.5V for low power applicationsare projected in the ITRS roadmap [1]. The most energyefficient operation of digital circuits and systems occurs in thesupply voltage range of 0.3V to 0.5V in deeply scaledtechnologies [2][3]. Other applications such as self-poweredsensor nodes to enable ambient intelligence also require ultra-low voltage mixed-signal ICs [4]. Recent research hasdemonstrated the feasibility of designing analog and RFcircuits that can operate with ultra-low supply voltages down to0.5V; this includes basic building blocks, analog filters, analog-to-digital converters, and even fully integrated RF receivers(see [5] and its references). In this paper, the realization of

voltage references operating down to 0.5V is investigated. Thewidely used bandgap voltage reference [6] configurations withPN diodes cannot be operated with such low supply voltages[7]. We explore several alternatives that are available in anystandard CMOS technology for the design of a voltagereference. They resemble the technique used in standard

bandgap designs to create a temperature independent quantity,namely the addition of two quantities, one of whichexperiences a positive temperature dependence and the other a

negative, which results in a temperature independent reference.

II. SUPPLY VOLTAGE R EQUIREMENTS FOR CMOS VOLTAGE

R EFERENCE S

The bandgap voltage reference [6] has been the mostestablished on-chip voltage reference circuit for many years. Ituses the complementary-to-absolute-temperature (CTAT)characteristic of the forward voltage drop across a PN junctionand linearly combines it with the proportional-to-absolute-temperature (PTAT) characteristic of the voltage difference

between two PN junctions with equal currents, but differentcurrent densities, to obtain a temperature independent outputvoltage. When these voltages are combined for a zerotemperature coefficient, the resulting output reference voltageis around 1.205V, which is the bandgap voltage for Silicon. In

bipolar ICs the PN junctions are typically formed using bipolartransistors. In CMOS processes, parasitic vertical bipolar PNPdevices are generally used. These reference circuits typicallyrequire a supply voltage larger that 1.4V to properly function

(see e.g., [7]).

Instead of linearly summing voltage drops, a CTATcurrent , derived using a forward-biased PN junction, and aPTAT current can be linearly combined, and converted backinto a temperature-independent output voltage with arbitrary

value using the circuit topology presented in [8]. This topologyhas a minimum supply voltage equal to the PN-diode turn onvoltage (about 0.7V) plus a saturation voltage across a currentsource (about 0.2V) and can thus be operated below 1V, downto about 0.85V or 0.9V [9][10][11].

CMOS-only voltage references can operate with lowersupply voltages and are not bound by the limitations due to thePN diode turn on voltage. Most designs exploit the negativetemperature dependence of the threshold voltage of MOSdevices (see e.g. [12]) and combine it with a PTATcharacteristic which can be obtained with MOS devices inweak inversion; high performance references operating downto 0.85V VDD have been demonstrated [13]. Usingenhancement and depletion mode devices in a fully depleted

MOS/SIMOX process, a reference operating from a supplydown to 0.6V was demonstrated in [14]. However, such design

is not compatible with standard digital CMOS technologies.

Specialized techniques for the realization of high precisionreference voltages include floating-gate designs [15]; theyrequire special devices and each reference needs to be

programmed after fabrication. Additionally, increasing gateleakage effects make such structures less compatible with

deeply-scaled CMOS processes.

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In this paper we first explore the replacement of the PNdiode in a low voltage bandgap structure with a standard-CMOS-compatible Schottky diode in Section III. We theninvestigate in Section IV the use of the CTAT characteristic ofthe forward drop across a diode-connected nMOS device withits body shorted to its gate, and thus with a forward-biased

body-source junction and reduced threshold voltage VT. For both designs a proof-of-principle IC prototype is presentedwith experimental data. Section V compares the results of

various low voltage approaches.

(a)

(b)

Figure 1 Layout (a) of 4 Schottky diode unit cells; (b) cross-section of a

Schottky diode-unit in a standard CMOS process

III. SCHOTTKY DIODES A ND THEIR USE I N A VOLTAGE

R EFERENCE

A. CMOS-Compatible Schottky Diodes

Schottky diodes can be realized in a standard CMOS process, by directly contacting an N-WELL region without an N+ implant. Figure 1 shows the layout and a cross section ofthe Schottky diodes laid out in a standard 90nm CMOStechnology from UMC. In modern CMOS processes silicidesare used at the Silicon-Metal interface and the Schottky barrierdiode is formed where the silicide contacting the metal is incontact with the N-WELL; the N-WELL is then contacted withan ohmic contact. The metal is the diode anode and the well isthe cathode. The current through the diode, I D, is determined by

thermionic emission across the barrier:

I D = AR*T

2exp

"# B

nkT / q

$

% &

'

( )

*

+ ,

-

. / 0 exp

V D

nkT / q

$

% &

'

( ) "1

*

+ ,

-

. / (1)

where V D is the voltage across the diode, kT/q is thethermal voltage, n is the diode ideality factor and is close to 1;!B is the Schottky barrier height, A is the area of the diode, T is

the absolute temperature and R* is the effective Richardson

constant [16]. This I-V dependence is very similar to the PN-

diode I-V relationship or the IC-VBE dependence for a bipolartransistor.

The difference of the forward voltage of two Schottkydiodes operated with identical currents but different currentdensities can be used to generate a PTAT voltage. Thedependence of the forward voltage drop to temperature for a

fixed or temperature dependent current, is also very similar tothe results obtained for a PN diode. (Note that the R* term isonly very weakly temperature dependent.) For the Schottkydiode, the extrapolated forward voltage at zero Kelvin is equalto the Schottky barrier !B. It depends on the work function of

the metal and semiconductor used and is typically in the order

of 0.2 to 0.6V.

These properties make the Schottky diode an excellentreplacement for the traditional PN-junction diode for voltagereferences operating with ultra-low supply voltages. AlthoughSchottky diodes can be readily designed in standard CMOS

processes, they are typically not included in the standarddesignkit or simulation models. For the purpose ofdemonstrating an ultra-low VDD reference, we characterized a

number of diode test structures provided by the foundry. Wefurther built a custom verilog-A based model to incorporate thediodes in the circuit design flow. I-V characteristics weremeasured over temperature to extract the temperaturecoefficient.

Figure 2 Measured I-V characteristics for various temperatures of a 32 unitSchottky diode with the layout of Fig. 1.

Figure 2 shows the measured I-V characteristics for varioustemperatures for a 32-unit diode test structure. The turn-onvoltage of the Schottky diode is between 0.2 and 0.3V, whichis significantly lower that the 0.6 to 0.7V typically needed to

turn on a PN junction diode. The forward voltage across theSchottky diode had a measured temperature coefficient of-0.4mV/

oC (from 10 to 100

oC). The I-V characteristics also

show a parasitic resistance in series with the diode, which iscaused by the series resistance due to the NWELL used tocontact the structure. A parasitic resistance of approximately100 Ohms/unit-diode was extracted from the I-Vcharacteristics.

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B. Voltage Reference Using Schottky Diodes

Schottky diodes have been used in the design of voltage

reference operating from a 2.5-V supply voltage in [17]. Here,we demonstrate that they enable the realization of ultra-lowVDD references when used in the current-summing based

bandgap topology from [8]. The schematic of the designedreference is shown in Figure 3. The reference circuit consistsof two almost identical branches; one branch contains a singleSchottky diode unit and the other branch has N diode units in

parallel (N=6 in this design). An operational transconductanceamplifier (OTA) is used to force the voltages across resistorsR2a and R2b to be equal, with a nominal value of 250mV,which drops with a rate of 0.4mV/oC for increasingtemperature. The difference of the forward-bias voltage of thediodes is dropped across resistor R1, creating the PTATcurrent, while the current through R2a and R2b is a CTAT

current. The nominal value of the voltage across the resistorR1 increases with a rate of 0.22mV/oC. Resistors R1 and R2a

(which is equal to R2b) are sized as 1k ! and 2.13k ! respectively, in order to obtain a zero temperature dependence.The sum of the PTAT and CTAT current is mirrored intoresistor R3 to create the reference voltage. Devices Ms1-Ms2and Ps1 form a startup circuit, which ensures that the circuit

can not stay in the zero-current state.

An ultra-low voltage OTA is required in this circuit andwas designed as a two stage Miller compensated amplifier. Itsschematic is included in Figure 3. It employs a differentialinput pair, consisting of transistors M1 and M2, operating inweak inversion so that sufficient headroom remains availablefor the current source M4 while the input common mode level

is about 250mV. The amplifier is self-biased from the supply(using the resistor Rb and transistor M3) and consumes 100uA

of current, providing a DC gain of 40dB.

Figure 4 Die Microphotograph (right) and corresponding layouts (left) ofthe Schottky and MOS-only reference circuits.

C. Experimental Results

The layout and die photograph of the experimental prototype in a standard 90nm CMOS technology is shown inFigure 4. The circuit is very compact and occupies only0.019um

2. The circuit samples were measured using wafer

probing. Figure 5 shows the measured reference output voltagew.r.t. the supply voltage VDD; the reference is functional withsupply voltages down to 0.5V. For the nominal VDD of 0.6V

the supply sensitivity is 3mV/100mV.

Figure 3 Schematic of the Schottky-diode-based reference.

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Figure 5 Measured Schottky reference supply voltage dependence

Figure 6 Measured Schottky reference temperature dependence between 10

and 100oC while operating from different supply voltages.

Measurements over temperature, plotted in Figure 6, show

that the output voltage reference ranges from 250mV to256mV when measured from 10 to 100

oC with a supply

voltage VDD of 0.6V, which results in an effective temperaturecoefficient of 0.07mV/

oC or 263ppm/

oC. At the same VDD, the

reference voltage range was 251 ± 4mV for 18 samples. No

trimming was performed for any of the measurements. The performance of the reference circuit for supply voltages of0.55V, 0.6V and 0.65V is summarized in Table 1. This proof-

of-principle circuit consumes 375uW at room temperature.For this design, limited diode data and models were availablerestricting the choice of bias points. As more characterization

data and better device models become available to the

designers, significant power savings can be expected. Also the power consumption of the OTA can be significantly reduced.

IV. VOLTAGE R EFERENCE UTILIZING O NLY MOS DEVICES

Several MOS-only references have been demonstratedoperating below 1V down to 0.85V [12][13]. They typicallyrely on the negative temperature coefficient of the thresholdvoltage to obtain a CTAT characteristic and use the gate-sourcevoltage difference of weakly inverted MOS devices withdifferent current densities for the PTAT characteristic [18]. Toobtain low voltage operation, threshold reduction techniquessuch as forward body biasing is often applied. E.g. in [13] the

body of a weakly inverted PMOS transistor is connected to thegate and used as the basis for a high precision, 0.85-V VDD reference. Next we explore an ultra-low voltage, MOS-only

design with an NMOS device with a forward-biased body-source connection using the commonly available deep n-wellimplants used in standard CMOS technologies.. Note thatultra-low supply voltages (<0.7V), the risk of latchup due to

forward biasing is generally not present.

A. CMOS PTAT

The replacement of the PTAT cell in the voltage referencecan be achieved by replacing the PN diodes with MOS devicesoperating in the weak inversion region, exploring the I-VGS

Figure 7 Schematic of the MOS-only reference .

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characteristic behavior of weak inversion operation. In thisdesign we used the topology shown in Figure 8 (b) [19] whichgreatly reduces the effect of OTA offset voltages compared tothe conventional topology (Figure 8 (b)). The PTAT voltage iscreated as the difference between the VGS voltages oftransistors M1 and M2, creating a PTAT current of nominalvalue 150uA in this design. M1 and M2 are deep-n-welldevices with source and body shorted. This circuit isincorporated in the MOS-only reference shown in Figure 7.

Figure 8 The conventional circuit (a) to create a PTAT voltage across

resistor R with weakly inverted MOS devices is more sensitive than the circuit

in (b) .

B. CMOS Ultra-Low Voltage CTAT

The CTAT part of the reference in Figure 7 is created as thedrain-to-source voltage of an NMOS device, M7, operating inthe weak inversion region, whose gate and body are tied to thedrain. The body-source junction is forward biased effectivelylowering the threshold voltage of the device. Thisconfiguration is called a dynamic-threshold MOS in [13]. Due

to the CTAT dependence of the threshold voltage, the V GS hasa CTAT characteristic when the device is biased in weakinversion with a PTAT current. The temperature coefficient ofthis CTAT voltage will increase with increasing currentthrough the device, as well as with an increased body effect

coefficient and transistor W/L ratio.

C. CMOS-only Ultra-Low V DD Reference

The complete schematic of the designed voltage referenceis presented in Figure 7. The PTAT current, generated bydevices M1 and M2 and resistors R1 and R2, is mirrored toresistor R5 and transistor M7, which create the PTAT andCTAT parts of the voltage reference respectively. TransistorsM3-M6, along with M8-M10 and P1-P2, form a low-voltagecascade current mirror, to accurately copy the PTAT current.

Transistors M11-M12 form the startup circuit of the reference,ensuring that the transistors M1 and M2 do not operate in zero-current state. Capacitor CC is used for compensation. In this

proof-of-principle design, the same OTAs as for the Schottkyreference (Figure 3) have been reused.

D. Experimental Results

A circuit prototype was realized in a standard 90nmCMOS technology. The layout and die photo are shown in

Figure 4; the circuit occupies only 0.07um2.

Figure 9 Measured reference voltage VREF w.r.t. supply voltage VDD

Measurements of the MOS-only reference circuit showedits functionality for supply voltages as low as 0.5V. Thereference voltage supply dependence is shown in Figure 9.The reference voltage’s temperature dependence, shown in

Figure 10, is from 241.5 to 245mV when measured from 5 to100o

C, which corresponds toan effective temperaturecoefficient of 0.04mV/

oC or 160ppm/

oC, at a VDD of 0.6-V.

The nominal output voltage is 256 ± 4mV for 16 measuredsamples. No trimming was performed on any of the circuits.The total consumed power of this proof-of-principle prototype

was 547uW at room temperature.

Figure 10 MOS-only reference temperature dependence

V. DISCUSSION AND CONCLUSIONS

Table 1 reviews the different performance characteristicsof sub-1V reference circuits, both bandgap based as well as

MOS-only based designs. As outlined in the paper several

design techniques exist to design references that can operatewith a supply voltage significantly below the Si bandgap

voltage. In this paper we presented two solutions to furtherreduce the supply voltage for reference circuits to well below

0.7V and demonstrate functionality down to 0.5V.Lower reference voltage designs intrinsically have a poorer

relative temperature dependence performance (in ppm/oC)

than higher reference voltage designs. Still, at this point the

performance of the (untrimmed) ultra-low voltage designscannot match the performance of designs based on more

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established design techniques and well characterized and

modeled components. Schottky diodes offer a promisingalternative to design ultra-low voltage references. Anattractive feature of a Schottky based reference is that the

reference voltage can be traced back to a physical parameters,the Schottky barrier, which is primarily dependent on material

properties. MOS-only reference designs also offer interestingopportunities, in particular in combination with forward body

biasing. Although MOS based designs are often more prone

to process variations, experimental data in [13] suggests a better matching behavior for such MOS configuration whichcan be safely used in an ultra-low voltage context.

The performance of ultra-low voltage references can beexpected to significantly improve as more reliable circuitmodels and device characterization data becomes available to

the designer, and as design techniques are further developedand mature driven by the growing need for ultra-low voltagesystem-on-a-chip ICs.

VI. ACKNOWLEDGMENTS

The authors thank United Microelectronic Corp. (UMC)for chip fabrication and Y. Baeyens and Y.K. Chen of BellLaboratories for temperature-sweep measurement support.

VII. R EFERENCES

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[3] S. Hanson et al., “Ultralow-voltage minimum-energy CMOS,” IBM Journal of Research and Development , vol. 50, no. 4/5, pp. 469-489,July/Sept. 2006.

[4] J. Rabaey et al., "Ultra-low-power design, the roadmap to disappearingelectronics and ambient intelligence," IEEE Circuits and Devices Magazine, vol.22, no.4, pp. 23-29, July-Aug. 2006

[5] P. Kinget, "Designing analog and RF circuits for ultra-low supplyvoltages," Proceedings of the 33rd European Solid State CircuitsConference (ESSCIRC), pp.58-67, Sept. 2007.

[6] R.J. Widlar, “New Developments in IC Voltage Regulators,” IEEE J. ofSolid-State Circuits, vol. SC-16, pp. 2-7, Feb. 1971.

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[8] H. Banba et al. “A CMOS Bandgap Reference Circuit with Sub-1VOperation,” IEEE J. Solid-State Circuits, vol. 34, pp. 670-674, May1999.

[9] K.N. Leung et al., “A Sub-1-V 15-ppm/oC Bandgap Voltage ReferenceWithout Requiring Low Threshold Voltage Device,” IEEE J. Solid-StateCircuits, vol. 37, pp. 526-530, April 2002.

[10] A. Boni, “Op-Amps and Startup Circuits for CMOS BandgapReferecnces With Near 1-V Supply,” IEEE J. Solid-State Circuits, vol.37, pp. 1339-1342, October 2002.

[11] J. Doyle et al., “A CMOS Subbandgap Reference Circuit with 1-VPower Supply Voltage,” IEEE J. of Solid-State Circuits, vol. 39, no. 1, pp. 252-255, Jan. 2004

[12] G. Giustolisi et. al., “A Low-Voltage Low-Power Voltage ReferenceBased on Subthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol.38, pp. 151-154, Jan. 2003.

[13]

A. Annema, "Low-power bandgap references featuring DTMOSTs," IEEE J. of Solid-State Circuits, vol. 34, no. 7, pp. 949-955, Jul 1999.

[14] M. Ugajin et. al., “A 0.6-V voltage reference circuit based on "-VTHarchitecture in CMOS/SIMOX,” Symp. VLSI Circuits Dig ., pp. 141 -142, June 2001.

[15] B. K. Ahuja et al., “A 0.5uA Precision CMOS Floating-Gate AnalogReference,” IEEE International Solid State Circuits Conference, 2005, pp. 286-288.

[16] K. N. Ng, “Complete Guide to Semiconductor Devices,” McGraw Hill,Inc. 1995.

[17] D. Butler et. Al., “Low-Voltage Bandgap Reference Utilizing SchottkyDiodes”, Midwest Symposium on Circuits and Systems, vol. 2, pp. 1794-1797, Aug. 2005.

[18] Y. Tsividis, R. Ulmer, “A CMOS voltage reference," IEEE J. of Solid-State Circuits, vol.13, no.6, pp. 774-778, Dec 1978.

[19] F. Serra-Graels, J. L. Huertas, “Sub-1V CMOS Proportional-to-AbsoluteTemperature References,” IEEE J. of Solid-State Circuits, vol. 38, no. 1,

Jan. 2003

TABLE I. PERFORMANCE COMPARISON FOR SUB-1V VDD VOLTAGE R EFERENCES

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