Power Aware Design Verification

Vidya PrabhuPriyabrata Kundu

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Agenda

• Low Power – need and techniques• Common Power Definition Format• Verification Success Stories• Power Aware Coverage• Limitations and challenges

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Low Power and Challenges Ahead

Power density is increasing at an alarming rate, approaching that of the hottest man-made objects on the planet!! [1]

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Power Reduction Techniques

• Clock Gating• Multi-supply voltage

- needs level shifters

• Power Shut-Off (PSO)- needs Isolation cells- needs state retention registers

• Multi threshold voltage• Dynamic Voltage & Frequency Scaling (DVFS)

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Power Reduction Techniques (contd..)

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Need for Common Format

• Multiple power domains, power modes and power sequencing are used for more than a decade

• No standard language to define power intent– Inconsistent low-power inputs at different stages of design cycle– Not efficient – same inputs repeated in different formats– Information can get lost/altered during this translation

• No method to verify power functionality without changing RTL, particularly power-shutoff

• A single file to capture all low power intent, enables consistency across all phases of design, verification and implementation.

• Two low power specifications.– Common Power Format (CPF)– Unified Power Format (UPF)

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Advantage of CPF

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• No RTL changes are required for a CPF-based flow• The power intent is captured in the CPF

– Maintain integrity of RTL design files– Design reuse

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Verification Case Study 1

• Clock multiplexing Issue – clock_control.v module supposed to output low frequency ckref in

SLEEP mode and high frequency ckfunc when not in SLEEP mode.– powered by on-chip regulator REG1– powered down in SLEEP mode

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Verification Case Study 1 (contd..)

Simulation without CPF – ckout switches from high freq to low freq

Simulation with CPF – ckout switches to X when REG1 powers down

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Verification Case Study 1 (contd..)

• BUG FIX- Logic moved to another module which is ON during SLEEP

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Verification Case Study 1 (contd..)

Simulation with CPF -

BUG FIX: ckout correctly switches from high frequency to low frequency

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Simulation with CPF – ckout switches to X when REG1 powers down

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Verification Case Study 2

• Initial Powerup Issue:- On-chip regulator REG1 powers up before REG2- Logic 2 powered by REG2. - In the duration that REG1 is powered up and REG2 is powered

down, Logic 2 outputs X to clock_control which is ON. Purpose of Isolation cell defeated.

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Verification Case Study 2 (contd..)

Simulation with CPF – ckout_LS is X till REG2 powers up, causing sync_out (signal inside clock_control) to go X

• BUG FIX: - Logic 2 power supply changed from REG2 to REG1

Simulation with CPF after bug fixed–ckout_LS is X only till REG1 powers up

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Power Aware Coverage

• Determining how much of power information specified in CPF, has been exercised during verification.- Have all shut-off conditions been exercised for all power domains?- Have all isolation cells been exercised?

• An executable verification plan for power coverage is automatically created from CPF.

• The covergroups needed to collect and capture metrics for low-power simulations are also automatically created.

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Example coverage report:

Power Aware Coverage (contd..)

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Challenges : Mixed Signal Simulation

• Problem statement:� Mixed signal design using Verilog AMS models� CPF does not allow Verilog AMS modules to be turned off.

- ignores power specification on analog instances. - Analog instances must be assigned to a power domain which is always-on

• Workaround:� Incorporate power signals in the AMS models. � AMS model should reflect the correct behaviour of power loss. Depending on

the implementation of AMS model, output is corrupted or zeroed.� Power signals not connected by design, testbench drives power signals of

AMS models by out-of-module reference.

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Simulation result – Output “Out” is zeroed when regulator output Vreg1_out is low.

EXAMPLE WORKAROUND AMS MODEL CODE:module ams_model (vin1, vin2, Out);input electrical vin1;input real vin2;output electrical Out;wire Vdd;real power_ok;

always @( Vdd) beginif ( Vdd == 1) power_ok=1.0;

else power_ok = 0.0;endanalog

Out = (V(vin1) + vin2) * power_ok;endmodule

Challenges : Mixed Signal Simulation (contd..)

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EXAMPLE WORKAROUND TESTBENCH CODE:always @(`TOP.Vdd or <other power supplies)

beginforce `AMS_MODEL.Vdd = `TOP.Vdd;………………………………………………………………………………<force all AMS model power supplies>………………………………………………………………………………end

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Challenges : Memory Models

• Problem statement:- “Initial” blocks are executed once during the simulation at time 0.- Without CPF, power is assumed to be stable at time 0.- With CPF, all power supplies are OFF at time 0, causing Xs to be driven into all memory elements. When power supply turns ON, the initial blocks are not executed.

Example: Memory model MEM_ELEMENT.v: initial

begin

for (i=0; i< words ; i=i+1)

mem_fault_array_XOR[i]=0;

if (<condition>)

begin

mem_fault_array_XOR[1] = 1'b1 << (bits - 1);

end

end

Q_local_tmp = mem_core_array[Alatched]^mem_fault_ar ray_XOR[Alatched];

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Challenges : Memory Models (contd..)

Simulation without CPF – Q_local_tmp is initialized and ADC sampling happens correctly

Simulation with CPF – Q_local_tmp is X throughout the simulation, affects ADC sampling

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• Workaround:The memory elements had to be driven with initial values from testbench after

power supplies are turned ON.

Example workaround testbench code: `define MEM_MODEL `TOP .….< full_hierarchy_path>.….MEM_ELEMENT

always @(posedge `REG1.vreg1_wire)

begin

for (`MEM_MODEL.i=0; `MEM_MODEL.i< `MEM_MODEL.words ; `MEM_MODEL.i=`MEM_MODEL.i+1)

`MEM_MODEL.mem_fault_array_XOR[`MEM_MODEL.i]=0;

if (<condition>)

begin

`MEM_MODEL.mem_fault_array_XOR[1] = 1'b1 << (`MEM_M ODEL.bits - 1);

end

end

Challenges : Memory Models (contd..)

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Challenges : Memory Models (contd..)

• This is solved in CPF ver 1.0e. - supports “initial” block replay when power is restored

• CPF Command:set_sim_control -target * -action power_up_replay - modules {

……………………………………

MEM_ELEMENT \

……………………………………

}

Simulation result : Q_local_tmp is initialized after regulator powers up. ADC sampling happens correctly.

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Challenges: Managing Two Power Definition Formats

• Problem statement : Managing two different power formats when adopting tools from different vendors at different stages of the design flow.

• Solution: Conformal LP provides automatic translation from one format to another – UPF to CPF and vice versa.

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UPF commands Translated CPF commands

create_power_domain PD1 \-include_scope

create_power_domain -name PD1 \-default

create_power_domain PD2 –elements {and1}

set_domain_supply_net PD2 \-primary_power_net vdd1 \-primary_ground_net VSS

create_power_switch clks_ls_SW \-domain PD1 \-output_supply_port {VDDO vdd1} \-input_supply_port {VDDI VDD} \-control_port {SLEEP pse_en} \-on_state {on_state VDD {pse_en==1}} \-off_state {off_state {pse_en==0}}

create_power_domain -name PD2 \-shutoff_condition {!pse_en==1} \-instances { and1 }

update_power_domain -name PD2 \-internal_power_net vdd1 \-internal_ground_net VSS

create_power_switch_rule –name \clks_ls_SW -domain PD2 \-external_power_net VDD

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Conclusion

• Consistency in low power information throughout the design cycle

• Possible to verify power intent and find bugs early on in the design cycle, which was previously not possible.

• Power aware coverage provides a metric that describe how well the power intent has been tested.

• Managing two different power specification formats is easier with automatic translation using Conformal LP.

• Verifying power specification in mixed signal designs is challenging.

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Acknowledgements and References

• Acknowledgements:I would like to acknowledge the support provided by�Sherre Staves and LSI team�Lokesh Babu Pundreeka, Cadence, Bangalore�Maruthi Srinivas Narasimhan, Cadence, Bangalore

• References:[1]Power Forward, “A Practical Guide to Low Power Design – User Experience

with CPF. [Online]. Available: http://www.powerforward.org/media/p/65.aspx

[2]Si2 CPF 1.0 Tutorial 12-06-2007. [Online]. Available: http://www.si2.org/openeda.si2.org/cpf_tutorial_20071206/

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Thank youQuestions?

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