3DIC and the Hybrid Memory Cube - SEMI.ORG Global Summit 3DIC... · 3DIC and the Hybrid Memory Cube ... Link Controller Interface RX TX Host TX RX HMC 16 Lanes 16 Lanes ... HMC 3DIC

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1 ©2012 Micron Technology, Inc. |

Dean Klein

Micron Technology, Inc.

3DIC and the Hybrid Memory Cube

September 4, 2013


The Need: Break Down the Memory Wall

September 4, 2013

2 Channel

3 Channel

4 Channel


Reducing System Cost

September 4, 2013

2 Channel

3 Channel

4 Channel

Socket 423

LGA2011


Managing System Complexity

September 4, 2013

DDR

85 page specification 1 page of AC timing params 3 speed bins Standardization Time: < 3 yrs years


Managing System Complexity

September 4, 2013

DDR

85 page specification 1 page of AC timing params 3 speed bins Standardization Time: < 3 yrs years

DDR4 214 page specification 9 pages of AC timing params 12 speed bins for BOL (to 2400) Standardized Time: >6 years and going

6 | ©2012 Micron Technology, Inc. |

Hybrid Memory Cube (HMC)

September 4, 2013

Fast process logic and advanced DRAM design in one optimized package

▶ Power Efficient

▶ Smaller Footprint

▶ Increased Bandwidth

▶ Reduced Latency

▶ Lower TCO


Enabling Technologies

September 4, 2013

Memory Vaults Versus DRAM Arrays • Significantly improved bandwidth, quality and

reliability versus traditional DRAM technologies

Logic Base Controller • Reduced memory complexity and significantly

increased performance • Allows memory to scale with CPU performance

Abstracted Memory Management

Through-Silicon Via (TSV) Assembly

Innovative Design & Process Flow • Incorporation of thousands of TSV sites per die

reduces signal lengths and reduces power • Enables memory scalability through parallelism

Sophisticated Package Assembly • Higher component density and significantly

improved signal integrity


HMC Architecture

DRAM

Start with a clean slate

September 4, 2013


HMC Architecture

DRAM

Re-partition the DRAM and strip away the

common logic

September 4, 2013


DRAM

Stack multiple DRAMs

HMC Architecture

September 4, 2013


DRAM

Vault

3DI & TSV Technology

DRAM0

DRAM1

DRAM2

DRAM3

DRAM4

DRAM5

DRAM6

DRAM7

Logic Chip

Re-insert common logic on to the Logic Base die

HMC Architecture

Logic Base

September 4, 2013


HMC Architecture

Vaults are managed to maximize overall device availability

• Optimized management of energy and refresh

• Self test, error detection, correction, and repair in the logic base layer

3DI & TSV Technology

DRAM0

DRAM1

DRAM2

DRAM3

DRAM4

DRAM5

DRAM6

DRAM7

Logic Chip

Logic Base • Multiple high-speed local buses for data movement • Advanced memory controller functions • DRAM control at memory rather than

distant host controller • Reduced memory controller complexity

and increased efficiency

DRAM

Logic Base

Vault

Memory Control

Vault Control

DRAM Sequencer

Crossbar Switch

Write Buffer

Read Buffer

Refresh Controller R

equest

Write

Data

Read D

ata

DRAM Repair

TSV Repair

Detail of memory interface

September 4, 2013

Vault Control Vault Control Vault Control

Memory Control

Crossbar Switch

Link Interface Controller


Processor Links



Logic Base


HMC Architecture Link Controller Interface

RX

TX

Host

TX

RX

HMC

16 Lanes

16 Lanes

8 or 16 Transmit Lanes

8 or 16 Receive Lanes

September 4, 2013

Example:

HMC-SR Options: 10 Gpbs, 12.5 Gbps or 15 Gbps


Host Processor Memory Management

September 4, 2013

HOST

DRAM Layer

DRAM Layer

DRAM Layer

DRAM Layer

TSV

TSV

TSV

TSV

TSV

TSV

TSV

TSV

Re-drive Layer

Si Interposer

Manufacturing Test • Burn-in • At-speed Functional

Manage field maintenance and self test

Manage all present and future DRAM scaling and process variation issues

Manage 100+ different DRAM timing parameters

Non-managed DRAM (WIO, HBM, etc.)


Host Processor Memory Management

September 4, 2013

HOST

DRAM Layer

DRAM Layer

DRAM Layer

DRAM Layer

TSV

TSV

TSV

TSV

TSV

TSV

TSV

TSV

Re-drive Layer

Si Interposer

Manufacturing Test • Burn-in • At-speed Functional

Manage field maintenance and self test

Manage all present and future DRAM scaling and process variation issues

Manage 100+ different DRAM timing parameters

Simple memory requests and responses. No

DRAM timing to manage

Functions moved to HMC for management

Non-managed DRAM (WIO, HBM, etc.)

16 | ©2012 Micron Technology, Inc. | September 4, 2013

The Package

Standard BGA Packaging Solutions: Cost Effective Packaging using existing Ecosystems

Up to 1.28 Tbps Memory Bandwidth!


HMC Near Memory

▶ All links between host CPU and HMC logic layer

September 4, 2013

▶ Maximum bandwidth per GB capacity

HPC/Server – CPU/GPU

Graphics

Networking systems

Test equipment


HMC “Far” Memory

• Far memory

▶ Some HMC links connect to host, some to other cubes

▶ Scalable to meet system requirements

▶ Can be in module form or soldered-down

• Future interfaces may include

▶ Higher speed electrical (SERDES)

▶ Optical

▶ Whatever the most appropriate interface for the job!

September 4, 2013


HMC Reliability

▶ Built-In RAS features at a high level...

Logic / Interface

DRAM Array

Logic / Interface

DRAM Array

Logic / Interface

DRAM Array

Logic / Interface

DRAM Array

Host

Vault Data ECC protected

Address / Command Parity for Array

transactions

CRC Protection on Link Interface

Link Retry

Logic Stability (DRAM controls in logic)

Reliable handshake (packet integrity verified before memory access)

September 4, 2013


RAS Feature System Comparison FEATURE DRAM RDIMM HMC

Extensive Test Flow

Data ECC

Address/Command Parity

Mirroring (back-up memory)

Sparing (Chipkill)

Lockstep (redundancy w/better ECC)

CRC Coding

Self Repair

BIST

Error Status and Debug Registers

DIMM Isolation (flags faulty DIMM)

Memory Scrubbing

Supported Redundant or not needed

September 4, 2013


Technology Comparison (Extreme Performance)

September 4, 2013

• What does it take to support 1.28TB/s of performance?

• Comparison of HMC to DDR3L-1600 and DDR4-3200

Active Signals DDR3 requires ~14,300 DDR4 requires ~7,400 HMC only needs ~2,160, HMC is ~85% less than DDR3

$ $ $ $ $ $ $ $

$ $ $ $ $ $ $ $

$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $

Operating Power (including CPU’s) DDR3 system requires ~2.25KW DDR4 system requires ~1.23KW HMC system only needs ~350W, HMC is ~72% less than DDR4

Board Space DDR3 requires ~165,000 sq mm DDR4 requires ~82,500 sq mm HMC only needs ~8,712 sq mm, HMC is ~90% less than DDR4

Assumptions: 1DPC, (SR x4) RDIMMs, 6.2W/channel for DDR3 @ 12.8GB/s, 8.4W/channel for DDR4 @ 25.6GB/s 5W per Link for HMC @ 160GB/s, 143 pins/channel for DDR3, 148 pins for DDR4 , 270 per HMC, RDIMM area equals 10mm pitch x 165mm long, HMC w/keep outs equal 1089 sq mm, CPU for RDIMMS = 65W, CPU for HMC = 95W, each CPU supports up to 4 channels.


Technology Comparison (Single Link)

September 4, 2013

• What does it take to support 60GB/s of performance?

• Comparison of HMC to DDR3L-1600 and DDR4-3200

Assumptions: Same as previous example of 1.28TB/s Bandwidth

Channels DDR3 requires 5 channels DDR4 requires 3 channels HMC only needs 1 Link

Active Pins DDR3 requires 670 pins DDR4 requires 345 pins HMC only needs 72 pins

Board Area DDR3 requires ~7,734 sq mm DDR4 requires ~3,843 sq mm HMC only needs ~1,089 sq mm

BW/pin DDR3 ~90MB/pin DDR4 ~174MB/pin HMC ~833MB/pin

DDR3 DDR4

DDR3 DDR4

DDR3 DDR4

DDR4

HMC


Packet Buffer Memory Subsystem Comparison

▶ Packet Buffer Requirements & Assumptions

4 100GbE ports per Network Processor / Traffic Manager

Packet buffering on ingress or egress

Maintain 800Gbps effective bandwidth across all packet sizes at each packet buffer

September 4, 2013

100GbE

100GbE

100GbE

100GbE

Ingress or Egress Packet Buffer

Stats Table

Lookups

Network Processor / Traffic Manager

Queue Mgmt

Sw

itch

Fabric


400Gbps Packet Buffer Comparison

September 4, 2013

Network Processor

Network Processor

Parameter DDR4-2400 x16 4 HMC-15G-SR Links

# of Memory Devices

48 1

Total # of Pins

1848 276

Power: Host PHY+ Memory

56W 33W

Memory Surface Area

6048mm2 961mm2

Host PHY Silicon Surface Area1

1.75x 1x

84% smaller memory footprint

75% smaller host PHY

85% fewer pins

41% lower power

HMC System Level Savings

All devices drawn to scale

1. Relative sizes represented


Broad Adoption & Momentum

Accel, Ltd Fujitsu Limited Luxtera Inc. Pico Computing

ADATA Technology Co., LTD Galaxy Computer System Co., Ltd. Marvell Renesas Electronics Corporation

AIRBUS GDA Technologies Mattozetta Technologies Science & Technology Innovations

Altior GLOBALFOUNDRIES Maxeler Technologies Ltd. SEAKR Engineering

APIC Corporation GraphStream Incorporated MediaTek ST Microelectronics

Arira Design HGST, a Western Digital Company Memoir Systems Inc. Suitcase TV Ltd

Arnold&Richter Cine Technik HiSilicon Technologies Co., Ltd Mentor Graphics Tabula

Atria Logic, Inc. HOY Technologies Miranda Tech-Trek

BroadPak Huawei Technologies Mobiveil, Inc. Teradyne, Inc

Cadence Design Systems, Inc. Infinera Corporation Montage Technology, Inc. The Regents of the University of California

Convey Computer Corporation Information Sciences Institute USC Napatech A/S Tilera Corporation

Cray Inc. Inphi National Instruments Tongji University

DAVE Srl ISI/Nallatech NEC corpration T-Platforms

Design Magnitude Inc. Israel Institute of Technology Netronome TU Kaiserslautern

Dream Chip Technologies GmbH Juniper Networks New Global Technology UC, Irvine

Engineering Physics Center of MSU Kool Chip Northwest Logic UMC

eSilicon Corporation Korea Advanced Institute of Science Obsidian Research University of Heidelberg ZITI

Exablade Corporation Lawrence Livermore National Laboratory OmniPhy University of Rochester

Ezchip Semiconductor LeCroy Corporation Oregon Synthesis Winbond Electronics Corporation

FormFactor Inc. LogicLink Design, Inc. Perfcraft Woodward McCoach, Inc.

ZTE Corporation

Over 110 Adopters to date!

http://www.hybridmemorycube.org 1.0 Specification released April 2013

September 4, 2013

Over 120 Adopters!

http://www.altera.com/

http://www.ibm.com/us/en/

http://www.open-silicon.com/

http://www.samsung.com/us/

http://www.xilinx.com/

http://www.hybridmemorycube.org/


A Robust Ecosystem

OEM’s Enablers Tools

September 4, 2013


“…wicked fast” - gigaom.com

“…a complete paradigm shift” - extremetech.com

“…like adding a turbocharger to your computer” - datacenteracceleration.com

“…unprecedented levels of memory performance”

- Electronic News “…an entirely new category of memory” - Tom’s Hardware

Industry Validation

EE Times 40th Anniversary: “one of the top ten technologies expected to redefine the industry”


▶ Improved costs – at a system and TCO level

▶ When the need exists, the ecosystem develops.

▶ There are no competing technologies…

HMC 3DIC – The Bottom Line


▶ Improved costs – at a system and TCO level

▶ When the need exists, the ecosystem develops.

▶ There are no competing technologies… There are no universal solutions

HMC 3DIC – The Bottom Line

Documents

3DIC and the Hybrid Memory Cube - SEMI.ORG Global Summit 3DIC... · 3DIC and the Hybrid Memory Cube ... Link Controller Interface RX TX Host TX RX HMC 16 Lanes 16 Lanes ... HMC 3DIC