3D Silicon Integration

IBM Research © 2010 IBM Corporation

Dr John U. Knickerbocker

IBM - T.J. Watson Research, New York, USA

Microelectronics Users eXchange (MUX) – 10/21/2010 & 10/22/2010

3D Silicon Integration

Substrate

© 2010 IBM Corporation2 IBM Research

P.S. Andry, B. Dang, C. Jahnes, J. Maria, M. Mastro, R. J. Polastre,

K. Schleupen, E. S. Sprogis, C. K. Tsang, L. Turlapati, B.C. Webb, &

S.L. Wright

Acknowledgements


Outline

System Trends- Semiconductor Scaling & Technology Integration- 3D Benefits

3D Technology Challenges & Co-Design

3D Technology- Wafer Fabrication / Integration with TSV- Wafer finishing / Thinning- Assembly & Test

- D2D; D2W- W2W

- Test Vehicle Demonstrations / Characterization- Module and cooling- Reliability

3D Applications & Demonstrations - Application architecture (performance, power, …)- Test Vehicle Examples / Characterization

Summary


Outline




- D2D; D2W- W2W



Summary


Applications

Low Cost

Pocket Size / Small Form Factor

Increasing Function @ Same orSmaller Size

Lower Power

Local transaction processing

Wireless

High Bandwidth / High Data Rate

Security

High Volume / Time to Market

System Trends

Applications

Power Efficiency

Performance

- Multi-core

- Multi-thread

- High Bandwidth

- HeterogeneousIntegration

Cost

Security

Reliability

Consumer / Network Appliances / Sensors Computers / Servers / Cloud / HPC


Cycles / Instruction

ApplicationS/W

Development Tools

MiddlewareOperatingSystem

Hyper visor

Semiconductor*Package

Multi-coreProcessors Cache

Inter-connect

I/O

Compilers

System StructurePathlength

Frequency

Number ofComputingElements

1. System Stack

3. Frequency Scaling

2. Semiconductor ScalingLithography scaling

Frequency Plateau

Architecture / Performance Scaling

System Stack:Semiconductor Scaling & Technology Integration


System Stack:Semiconductor Scaling & Technology Integration

4. Power versus Gate LengthLeakage problem, Some help from High K Metal Gate

5. Semiconductor Scaling Moore’s Law / Dennard scaling rules / Atomic Limits

SPEC

int_

2000

_rat

e1

10

100

1000

1994 1996 1998 2000 2002 2004 2006 2008 2010

Historical GrowthTrend=45% per year

• Single thread performance growth slows significantly

• System throughput continues to grow

>4 Core

4 Core

1 Core

2 Core

Single-ThreadPerformance

SPEC

int_

2000

_rat

e1

10

100

1000

1994 1996 1998 2000 2002 2004 2006 2008 2010




>4 Core

4 Core

1 Core

2 Core

>4 Core>4 Core

4 Core4 Core

1 Core1 Core

2 Core2 Core



6. Multi-core / Multi-threadSubsystem drives need for 3D for Bandwidth& in some applicatilons, advanced optics


Hardware Technology Advancement

2005 2010 2015


S/C Technology – Partition / Multi-Thread

3D IC / Strata Level Integration


Current S/C & Pkg Technology (2D & 3D Wirebond)

Board

Substrate Substrate Substrate

3D IC, Optics & Pkg Integration

Board

Interconnect TSV Die Stack

Si Package

Cooling

Substrate

Optic

Optic

AdvantagesHigher Bandwidth / lower latency

Smaller size / form factor

Lower power I/O

Improved performance

Lower Cost

Challenges3D Technology

- Design / Design tools

- Industry Compatibility

& Standards

Power Delivery

Thermal / Cooling

Fine Pitch Wafer Test


Applications

Low Cost

Pocket Size / Small Form Factor

Increasing Function @ Same orSmaller Size

Lower Power

Local transactions

Wireless

High Bandwidth / High Data Rate

Security

High Volume / Time to Market

System Trends & 3D Technology Integration Benefits

Applications

Power Efficiency

Performance

- Multi-core

- Multi-thread

- High Bandwidth

- HeterogeneousIntegration

Cost

Security

Reliability

Consumer / Network Appliances / Sensors Computers / Servers / Cloud / HPC

Power – Efficiency

Scalability / Modularity

Heterogeneous Integration

Increasing BW / Function

Lower Cost

3DTechnology


3D CMOS Integration Industry

Elpida / NEC / Oki

FujikuraHitachi/RenesasIBMInfineon

Intel

NXPPhilipsQualcommQuimondaSamsungSanyoSeiko EpsonSony

Toshiba

Consortia / Universities

ASET

IZM / Fraunhofer

IMECMIT/Lincoln LabSEMATECH International

Tohoku Univ.RPI

Start-Up Companies

TezzaronZiptronix

Zycube

Ref. Umemoto, ECTC 2004

Ref. Hunter, ECTC 2004

Ref: http://www.zy-cube.com/

Ref: B.Black, CCD conference 2004

Ref: Y. Kurita, ECTC 2007


Outline




- D2D; D2W- W2W



Summary


3D Challenges 3D Readiness1. 3D Architecture. Circuits, Timing, EDA Tools, Modeling Data Library / Fabrication Rules

2. 3D Technology & Integration Elements Material, Structure, Processes

- Thinned Si

- Through – Silicon - Via (TSV)

- Silicon - Silicon Interconnection (SSI)

- Module Integration

- Assembly - Test (WLT for KGD)

- Power delivery - Cooling

3. Introduction of New Function or New Competitive Product Value Add

- Industry Infrastructure, 3D Standards - Miniaturization- 3D Products Volume Lower Costs - Function

Design / Architecture for lower costs (Perf., Power, Het. Integ.)

Power Efficiency, Performance - Standards

New Applications / Size / Function

3D-Technology Challenges & Readiness

Chip Stack

Substrate


Heterogeneous System Integration: …

System-On-Package SOP 2D/3D

System-On-Package SOP 2D/3D

System Integration3D Die Stack

System Integration3D Die Stack

System-On-ChipSOC

System-On-ChipSOC

Electrical I/O Interconnection

Power (Batteries) & Regulation

RF / Microwave

High Performance Logic

Memory / Cache

DRAMSensors

Optical I/O Interconnection

Clock Distribution Antenna

Display Packaging

Floor-planning

Clocking

Interconnection

Technology, …

High Performance LogicHigh Performance LogicHigh Performance Logic

Memory / CacheMemory / CacheMemory / Cache



RF / Micr

owav

eRF / Microwave

RF / Micr

owav

e

Amplifier

Amplifie

r

Amplifier


S/C

+

Pkg

Amplifier



3D Die Stack & Si Pkg Integration

3D Silicon Pkg Integration

Substrate

Circuits , Trench Capacitors

Cooling

Silicon Package

Cu Wiring

TSV

SSI

Base Substrate

TSV

SSI

Die Stack

Si Package


Heterogeneous Die Stack- 4 Memory- MC Processor

Advantages- Shortest wiring length- Small X-Y size- Lowest power - Lowest latency- High Bandwidth

Challenges- Highest Power Density

- Power Delivery / Grid - Cooling

- Heterogeneous die sizes- Circuit Area efficiency

Heterogeneous Si Pkg Integration- 4 Memory- MC Processor

Advantages- Modular Integration- Flexible die size integration- Lower Power density / delivery- Lower Heat Removal density / area- Ease to integrate Heterogeneous Die- Ckt area efficiency- Bandwidth

Challenges- Latency

Heterogeneous Integration Comparison : uProcessor + Memory Stack


3D Silicon Integration (Co-Design = System design specification & Process Integration )

Silicon (S/C), GaAs, SiGe, …CMOS, RF, Mw, mmW, Node, 32nm, 22nm, …Power, IntegrationCustom designvs commodityIntegration –

Transitor, Macro, Unit, Core

2D or 3D SOP

Si Pkg

Application

System Drivers- Cost- Power- Performance- Reliability

SystemSpecification

ProcessIntegration - 2D, 3D, Die, Pkg- Structure- Technologies- Process

SystemSpecification

- S/C Node- Total I/O; Pitch- Size, Power- Pkg / PWB

Balance

Architecture

Design

Build

Assembly

Test

Ship

TSV:First, Middle, Last

Assembly:C2C, C2W, W2W

Si-Si Interconnection:Solder, Cu, Oxide,

Package, Interconnect, & ModuleI/O DensityBandwidthData RateCoolingSize / Form factorPower efficiencyDisplayPower Delivery

2D or 3D SOC


Outline




- D2D; D2W- W2W



Summary


3D-Technology Research & Manufacturing Summary3D

Int

egra

tion

Research

Dev / Mfg / Products

Time

3D Stack& Si Pkg

3D Chip

Si Pkg

- Architecture / Design - Assembly (C2C, C2W, W2W)

- Design Tools / Circuits - IP Library & Models

- TSV Dia, Pitch / Si Thickness - Electrical, Mechanical, Thermal

- CMOS Wafer Integration & Finishing - Test & Reliability

- Stack Interconnection size, pitch: - Modeling Performance, Power, Cost

-- Architecture - Design / Structure / Size

-- Application Sizing - Wafers 200 mm / 300mm

- - Cost Sizing - Design Kits

- - Technology Qualifications - Technology Platforms

- - Product Qualifications




- Thinned Si












Chip Stack

Substrate


3D Technology Evaluation Platforms

Substrate

Technology NodeFine pitch TSVFine pitch interconnectionMulti-high die stacksI/O, Power,Technology node …

ProcessorProcessor

DRAM Strata

Processor

Fine pitch TSVFine pitch interconnectionMulti-high die stacksLarge X-Y SizeI/O, Power, …Form factor

AnalogTSVPitch interconnectionTechnology NodeForm factor


3D Technology and System Partitioning

System Evaluation / Options- Performance

- Power Efficiency / Total Power

- Cost

- System Partitioning, Sourcing, Compatibility

3D Technology Integrations- Die Stack / Si Pkg Integration

- F2F, F2B, Technology node, package, module considerations

- Die area efficiency vs TSV area

- TSV Pitch, Chip to Chip interconnection pitch, D2D, D2W, W2W

- Total power & local power density, IR drop, current limits

- power delivery, hot spots, cooling

- Module integration, cooling, yield



3D Die Stack & Si Pkg Integration

3D Silicon Pkg Integration

Substrate

Circuits , Trench Capacitors

Cooling

Silicon Package

Cu Wiring

TSV

SSI

Base Substrate

TSV

SSI

Die Stack

Si Package




- Thinned Si












Chip Stack

Substrate


Architecture - Design - Build - Characterization

Few Examples of 3D Test Vehicles- TV’s silicon through via development- TV’s high density wiring, signal integrity

& cross talk (Si Carrier or Package)- TV’s high I/O interconnection & chip stacking- TV’s active circuit die stacks (Funct., EDA, etc)- TV’s optical, thermal, module assessments - TV’s for reliability

TSV

18-bump chain.

SiSi

OE

CMOS IC

Organic Chip Package waveguide

SiliconThru-via

Substrate Decoupling Capacitors

CoolingChipChip

CoolerChip 1Chip 2

*ECTC 2008 – Doany et al.


Through-Silicon-Vias (TSV)

Substrate

Business

- TSV Cost

- Product adoption, risk, maturity

- Standards – Physical, Layout, Electrical

- Industry infrastructure, tools, design, process

Specifications

- Electrical - Resistance, Capacitance, Inductance, Models

- Current / Electro-migration / leakage / Variability

- RAS - Reliability, power, signal,

- Electrical, optical, thermal, fluidic

Bond, Assembly & Test

- Compatibility D2D, D2W, W2W

- Fine pitch Test / Burn-in


- Board / System Integration

Process

- Hole formation - Chemical etch, DRIE / Bosch

- TSV 1st, Middle, Last or Post Bond

- Passive / Active Si / CMOS / Bulk / SOI

- Adhesive / Liner. Insulator, Conductor

- Process chemicals, temperatures, yield, etc

- Stress, keep out zone, etc RAS – Reliability

- Physical, Electrical, Thermal, optical, ...

- DTC, EM, THB, HTB, …

- Contamination, corrosion, …

- Resistance drift, failure mechanisms

- Statistics, Modeling

Structure

- Size / Aspect ratio - Diameter, pitch, height

- Conductor – Cu, Doped Poly Si, W, other

- Dielectric – Yes / No, Oxide, Polymer, Glass

- Interconnection in Silicon / outside


1. TSV First

Deep Si RIE

Insulate / Temp Fill

FEOL

Etch & Metal Fill TSV

Build BEOL Wiring

Mechanical Handler attach

Thin Wafer

Backside process

Insulate & Via contact

2. TSV Middle

FEOL

Deep Si RIE

Insulate

TSV metallization

Build BEOL Wiring


Thin Wafer

Backside process


3, TSV Last (From Top)

Build FEOL Transistors

Build BEOL Wiring

Topside Deep Si RIE

Insulate Via

Metal Fill


Thin Wafer

Backside process


Foundry

Assembly / Pkg

4. TSV Last or TSV Post Bond


Build BEOL Wiring


Thin Wafer OR

W2W Bond / Thin

Backside Deep Si RIE

Insulate Via & Backside

Open to Pad

Metal Fill

Four Process Flow Examples for Through-Silicon-Vias (TSV)


1. TSV First

Deep Si RIE


FEOL


Build BEOL Wiring


Thin Wafer

Backside process


2. TSV Middle

FEOL

Deep Si RIE

Insulate

TSV metallization

Build BEOL Wiring


Thin Wafer

Backside process




Build BEOL Wiring

Topside Deep Si RIE

Insulate Via

Metal Fill


Thin Wafer

Backside process


Foundry

Assembly / Pkg



Build BEOL Wiring


Thin Wafer OR

W2W Bond / Thin



Open to Pad

Metal Fill



Design Rules against 3D Wafer Fabrication, Finishing & Assembly / Integration

Wafer Fabrication = TSV, circuits, wiring, decaps, …

Wafer handle attach

Wafer thinning

Backside wafer finishing

Under bump metallurgy

Wafer bumping

Wafer Finishing = wafer handle, wafer thinning, back side finishing, bumping

Assembly / Integration = Si carrier, die, die stacks, module, TIM, lid, test, SMT board Wafer test / dice, die assembly / stack

Si carrier assembly, substrate attach, handle release

TIM, Lid attach, Module test

SMT to board

Standard CMOS wafer fabrication processing

CMOS compatible TSV processing- DRIE- Insulation- Metallization

Design / Checking = Floor planning, Si layers, … 3D Design Rules / Technology Node w/ TSV’s

Modeling, Elect, Thermal, Mechanical, …

Floor planning, 3D layers, Clocking, Power / Gnd / Signal


TSV Processing Post FEOL (TSV Middle)


Through-Silicon-Vias (TSV)

25,920 vias probedyield = 100%

50-μm deep

25,920 vias probed

yield = 100%150-μm deep

Design / Structure / Fabrication

Electrical Yield &

Mechanical Modeling

Reliability

0.50 0.60 0.70 0.80 0.90 1.00 2 pt. via pair resistance (ohms)

0

500

1000

1500

2000

2500

3000

frequ

ency

0.50 0.60 0.70 0.80 0.90 1.00 2 pt. via pair resistance (ohms)

0

500

1000

1500

2000

2500

3000

frequ

ency


High Bandwidth Wiring & Link characterizationWiring - Signal & Ground Test Vehicle

TSV Characterization (Example) Micro-joint solder ( 25 um dia & 50 um pitch)- Inductance - DC resistance- DC resistance - DTC

- EMBEOL Characterization Decoupling Capacitors

- Signal integrity vs Distance & Data rate - 10 - 14 uF/cm2 demonstrated / with TSV- Far end X-talk: Design dependent

Chip To Chip & Chip Stack Link Characterization Modeling and Data Library- Signal integrity, Data rate, X-Talk, …. - Frequency & Time Domain


High Bandwidth Wiring & Link Characterization


Interconnection Metallurgies, Process & Chip Stacking

< 4 µm to > 150 µm< 4 µm to > 150 µm< 4 µm to > 150 µmDie or Wafer thickness

Overall yield,

Same chip size

Handling and bondingHandling and bondingCon

Volume MfgFlexible, use of KGDFlexible, use of KGDPro

Solder or Metal

Oxide bonding

Adhesive

Solder

Metal to Metal

Adhesive

Solder

Metal to Metal

Adhesive

Bonding technology

Wafer to waferChip to WaferChip to Chip

Demonstrations


Metal Bonding

C4 solder interconnect

Larger spacing between balls and higher joint gaps than low-volume solder interconnect>20,000 thermal cycles (stress-free Si-on-Si)

Attractive due to use of Cu in standard CMOS interconnect metallization.High thermal conductance and low electrical resistivity.Requires optimized Cu surface preparation, high bonding force and elevated temperature.

Copper direct interconnect

Relatively low temperature bonding (<300ºC)Form an intermetallic phase with a melting temperature much higher than low bonding temperature

Low-volume lead-free solder interconnect


3D- Integration Technologies


3D TSV’s

Silicon Chip 1

~10μm Si Chip 2

Wafer-Wafer bonding (Cu-Cu or Oxide-Oxide)

BEOL wiring

BEOL wiring

Packaging substrateSolderbump

Solderbump

Flip Chip packaging

100μm Deep TSV

~100μm thick Silicon Chip 1

Oxide

TSV

TSV

BEOL wiringAl pad

Packaging substrate

Silicon Chip 2

bump bump

bump bump

10μm Deep TSV

Solderbump

Solderbump

Flip Chip Assembly

50μm Deep TSV


Oxide

TSV

TSV

BEOL wiringAl pad

Packaging substrate

Silicon Chip 2

bump bump


3D Die Stacks & Modules

CMOS Compatible Process

Demonstrated Module Build & Assembly

> 9000 TSV

- 20mm die

Demonstrated Reliability

CMOS Process Compatible

Wafer Finishing Processes

Assembly processes

Full Module Reliability Stressing

ChipSi Interposer C-4

LTCC

Organic

Si Interposer

Chip

Reliability Stress TestingATC passed HTS passed DTC passedTHB passed


3D Si Packaging & Assembly

CMOS Flip chip

CMOS silicon carrierTSV array

Solder bump on underside of carrier

Laminate package solder bump

TSV

Cu M1

STISi

Cap

W stud contacts

Silicide

FET

Silicon substate

BEOL with Cu SiCOH-1X / FSG-2X wires + 3μm Cu and 4μm AlCu analog wiring

One or more Flip Chips

Laminate package

Al LM

solder bump solder bump

100μm

Flip chip


Multi-chip module using high bandwidth capable Si package

FPGA 1

FPGA 3 FPGA 4

FPGA 2

decap

chip chip Si Package w/ TSV

decap

Substrate

PWB


3D TSV’s

Silicon Chip 1

~10μm Si Chip 2


BEOL wiring

BEOL wiring


Solderbump

Flip Chip packaging

100μm Deep TSV


Oxide

TSV

TSV

BEOL wiringAl pad

Packaging substrate

Silicon Chip 2

bump bump

bump bump

10μm Deep TSV

Solderbump

Solderbump

Flip Chip Assembly

50μm Deep TSV


Oxide

TSV

TSV

BEOL wiringAl pad

Packaging substrate

Silicon Chip 2

bump bump


Fine Pitch Interconnection & Chip Stacking

Si

Si 50 Microns

Si

Si

PbSn

Pb-Free

25um on 50 um pitch

PbSn Solder bump 25um dia. PbSn @ 25um on 50um pitch

Si Chips on Si Pkg on Subst.

1st layer

2nd layer

3rd layer4th layer5th layer

6th layer

* ECTC 2007

***


Si carrier

Si

Si

Si

uC-4 Assembly


C-4 – TSV - uC-4 Power Distribution Modeling

Si Die or Si Pkg

Top Chip

Ceramic or Organic Substrate

Si


Reliability Characterization

Si Carrier / Microbump reliability stressing

TSV & Micro – C-4 stressing @ 50 um pitch ***

Microbump PbSn solder & Pb-free w/ 25 micron dia. *

Accelerated Test Sample / Condition Results

Electro-migration 100 mA @ 150C > 2000 Hr100 mA @ 125C > 2000 Hr

Deep Thermal Cycle -55 to +125C > 25,000 Cycles

Temp-Humidity-Bias 85C, 85%RH, 1.5V > 1000 Hr

High Temperature 150C > 2000 HrsStorage

***

*


3D TSV’s

Silicon Chip 1

~10μm Si Chip 2


BEOL wiring

BEOL wiring


Solderbump

Flip Chip packaging

100μm Deep TSV


Oxide

TSV

TSV

BEOL wiringAl pad

Packaging substrate

Silicon Chip 2

bump bump

bump bump

10μm Deep TSV

Solderbump

Solderbump

Flip Chip Assembly

50μm Deep TSV


Oxide

TSV

TSV

BEOL wiringAl pad

Packaging substrate

Silicon Chip 2

bump bump


3D- Wafer Integration Process Flow


1. TSV First

Deep Si RIE


FEOL


Build BEOL Wiring


Thin Wafer

Backside process


2. TSV Middle

FEOL

Deep Si RIE

Insulate

TSV metallization

Build BEOL Wiring


Thin Wafer

Backside process




Build BEOL Wiring

Topside Deep Si RIE

Insulate Via

Metal Fill


Thin Wafer

Backside process


Foundry

Assembly / Pkg



Build BEOL Wiring


Thin Wafer OR

W2W Bond / Thin



Open to Pad

Metal Fill



3D- Wafer to Wafer level Integration Technologies

3D Adhesive Bonding3D Cu to Cu Bonding 3D Oxide Bonding & Via


Test probe tips on 50 um pitch

Test

- Wafer Test / Self Test

- Known Good Die (KGD)

- Die on Die, Die onWafer or Wafer on Wafer

-Stacked Die test

3D- Wafer level test probes -


3D Cooling Test Vehicles Structures and Modeling

Chip 2Chip 1

Carrier

Cooler

CoolerChip 1Chip 2

Chip

Stack

Multi-chip Cooling Characteriztion

- 4 die on silicon package

Multi-die stack Cooling Characterization

- 2, 3, 4, …

Multi-die stack Thermal Modeling

- 2, 3, 4, 8, …


Cooling Integration Technology

• Microchannel cooling cross section diagram• > 400 - 500 watts / cm2 cooling• Single chip module or multi-chip module

Cooling

- Microchannel cooling

- Si Carrier & Chip stacksAdhesive

Ceramic substrate Chip TIM

Manifold blockInlet Outlet

Gasket MicrochannelcoolerAdhesive

Ceramic substrate Chip TIM

Manifold blockInlet Outlet

Gasket Microchannelcooler

3D Flow Diagram


Outline




- D2D; D2W- W2W



Summary




- Thinned Si












Chip Stack

Substrate


Architecture, Design & Trade-off Assessments

Substrate

Architecture & Design

Floorplan

Power Mapping / Distribution- Voltage, Current Analysis

Thermal Mapping / Distribution

Signal Mapping / Distribution- Signal Integrity, Noise, Timing, Clock

Component Compatibility / Link / Process, Structure, Thermal, Power

Design Verification / Checking

Application

Trade-off assessments

- performance, power, efficiency, cost, risk, reliability, schedule


Assembled 850 nm optical transceiver


Examples of Optical Transceiver Characterization Results

Eye Diagrams @ 12.5Gbps

Output power & Extinction Ratio

For 24 Tx channels & 24 Rx channels


Outline




- D2D; D2W- W2W

- Test Vehicle Demonstrations / Characterization- Module and Cooling- Reliability


Summary


SummaryOpportunity to Improve our Quality of Life

Sensors Data Management Efficiency / GreenPersonal Handheld Servers & Super Computers

Semiconductor Technology & 3D Subsystem Integration3D Integration & Optics Benefits3D Industry Infrastructure AdvancementsEarly Products - limited attributes of TSV & integrationFuture Product – significant opportunities

IBM 3D Technology AdvancementsDie Stack Integration platformsSilicon Package Integration platforms

System Application & DemonstrationsApplication Dependent on 3D Architecture & DesignEfficient Integration & Optimization over timeCost Benefits, Power Efficiency, Performance, Size, …3D Silicon Integration Demonstrations

Substrate

Si Pkg

SPEC

int_

2000

_rat

e

1

10

100

1000

1994 1996 1998 2000 2002 2004 2006 2008 2010




>4 Core

4 Core

1 Core

2 Core


SPEC

int_

2000

_rat

e

1

10

100

1000

1994 1996 1998 2000 2002 2004 2006 2008 2010




>4 Core

4 Core

1 Core

2 Core

>4 Core>4 Core

4 Core4 Core

1 Core1 Core

2 Core2 Core



Need for 3D

Documents

3D Silicon Integration