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3/3/99 1
Minutes from the fall 98 DAQ meetings:• TOF crate will always be running in the single event mode• Silicon crate may pipeline several (4?) events in the internal buffers
List of the VME modules required for implementation of the trigger control and event builder synchronization:• Event Number Generator, ENG, located in one (master) of the VME crates. It generates Event#&Type .• Interface to ENG, ING, located in all VME crates. It receives Event#&Type from the ENG.• Trigger Registers, TR, located in the Trigger VME crate. It latches current trigger conditions.• Enable Registers, ER, located in the Trigger VME crate. It enables/disables different trigger sources.• Programmable Prescalers, 1/n, located in the Trigger VME crate.
Using programmable logic devices like ispLSI from LATTICE it is possible to incorporate the functionality of the ENG, ING, TR, ER (and, possibly, 1/n) inside single module.Let’s call it PCD (Programmable Control and Data ports). Each crate will have several PCD modules configured in different ways. For example in the Trigger crate it will be one PCD configured as ING, and several PCDs - as ER/TR.
ispLSIispLSI The advantage of using ispLSI:• In-field programming• Definite delay• 3-year experience
CInControl Input Port
COutControl Input Port
DIOData In/Out Port
dECL dECL
dTTL
Functional diagram of the PCD
Hardware for PHOBOS Trigger Control
3/3/99 2
1/nCC
TR
ER
PP*PN(N)
TR
ER
TR
ER
RP*RN(N)
TR
ER
TR
ER
TOF LEDPulser
TR
ER
TR
ER
Si Cal Pulser
TR
ER
PedestalPulser
Sync Event
Calibration triggers
Physics triggers
CC
LVL0 TR strobe TOF COM
LVL0 at300 nsec
LVL0 BUSY
GDG
UDOSPP*PN(N)PRE (Pileup)
Follow (TR)
FO
FO
TR
ER TR
ER TR
ER TR
ER TR
ER TR
ER
1/n
TR
1/n
TR
1/n
TR
1/n
TR
1/n
TR
1/n
TR
LVL0
VERTEX
SUM
ZCAL
D80 nsec20 nsec
LVL1 TR strobe
Adjust for LVL1 timing ~1000 nsec
LVL1
GDG D
GDG
FAST CLEAR
Adjust for Si peakingpeaking time
GDG11
GDG10
GDG15
B1
LVL1BUSY
DStart LVL2
LVL2
L2Event counter
B2Busy MDBBusy Event Manager
ER = Enable Register (output), TR = Trigger Register (input), GDG = Gate and Delay Generator, FO = Fanout, 1/n = prescaler
L1
Phobos Trigger Logic
3/3/99 3
Event#&Type code is 16bit word. Bits 0:11 represent sequential event number, bits 12:16 event type.
Type Event Number15 12 11 0
All Phobos event types could be divided into 2 category:Normal Event when no special action required for any ROCs to handle the event.Special Event when special action required at least in one ROC. The typical event is the non zero-suppressed events in TOF.The additional information about enabled and actual trigger conditions could be obtained from the Trigger subevent. For example to identify that event was generated by TOF LED pulser, one need to check certain bit in the LVL0_TR word in the Trigger subevent.
CIn
Busy ROC0Busy ROC1Busy ROC2
TOF LED
SyncBusy Event Gen
DIO EvType4bit
Ev# 12bit
L1
Event#&Type
COut
Strobe EOD
18dTTL
16dECL
16dECL
ispLSIispLSI
Special
Events
PCD as the Event Number Generator
3/3/99 4
Event Types---------------------------------------------------------------------------------------# code Description---------------------------------------------------------------------------------------
Special triggers1 1000 TOF Pedestal (since Fastbus TDC and ADC are rather stable, the reasonable schedule for pedestal
events will be 1 pedestal run with 100-1000 events per day)2 0100 Silicon Pedestal (have to be defined)3 0010 Silicon Calibration (have to be defined)4 1111 Sync events (to synchronize Silicon and TOF in case of errors; generated in ENG)5 0001 Reserved Special.
Normal triggers6 0000 Normal 7 0000 TOF LED (gain monitoring of TOF PMTs; trigger from LED electronics)8 0000 Background events (empty buckets; triggered on beam crossing)9 0000 Scaled down singles10 0000 Reserved Normal triggers (fast multiplicity, flow triggers etc:)
Event Types
3/3/99 5
Normal triggers. Normal triggers does not set Special Events field of CIn. The signal sequence is as follows:1 L1 arrives to ENG2 ENG sets Busy Event Gen in COut3 ENG increments Event#4 ENG transfers Event#&Type to all ROCs via DIO5 ENG waits falling edge of all Busy ROCs6 each ROC receives Event#&Type7 each ROC sets Busy ROC in CIn of ENG8 each ROC buffers event data9 each ROC removes Busy ROC in CIn of ENG10 ENG detects removal of all Busy ROCs11 ENG removes Busy Event Gen in CIn
Special triggers.Let’s consider TOF LED Pulser. The hardware trigger is applied to the Calibration Trigger part of the trigger logic. The signal from the corresponding bit of the LVL0 TR goes to the TOF LED input of the control input port (CIn) ENG. The bit pattern of the Special Events field of CIn is transferred to the EventType field of data port DIO.Problem:Actually the ROC should turn off the zero-suppression before the event arrival. If we need to mix zero-suppressed events with non zero-suppressed in one run then TOF ROC should control the Pedestal Pulser like follows:1 TOF ROC generates Busy ROC2 TOF ROC turn off zero suppression3 TOF ROC removes Busy ROC4 TOF ROC generates Pedestal Pulser by writing to the local COut
Signal Sequences
3/3/99 6
Sync event1 ENG sets Busy Event Gen2 ENG increments Event# and sets Type = Sync3 Continue as for Normal triggers from the step 4.…10 ENG detects removal of all Busy ROCs11 ENG repeats the steps 2:10 until all events in the Silicon pipeline are pushed out.
Signal Sequences, Sync Event
3/3/99 7
CIn
TR00
ER00TR strobe
COut16dECL
16dECL
ispLSIispLSIER15
…..…..
TR13
…..…..
VME
CIn should latch TR data, the strobe propagation delay should be less than 20 ns.COut has level outputs (pulse outputs can be discussed).
PCD as the Trigger/ Enable Register
TR clear
3/3/99 8
dECL
toTTL
TTL
todECL
dTTL
to TTL
to dTTL
MC10ELT25
MC10ELT24
SN74LBC978
HIGH
ADR SEL
A23-A8
A7-A1AM5-AM0
ASLWORD
IACK
DS0-DS1
WRITE
IACKIN
DTACK
BERRIACKOUT
IRQnD00-D16
SYSCLK
FIFO64Kx18
DP0-DP15
STROBEs
DIRs
CPI0-CPI15
CPO0-CPO15
16MHz
64MHz
C/ST FIFO
SEL
ispLSI3320-100
INPUT CONTROL PORT 16 bit, 34pins connector
OUTPUT CONTROL PORT 16 bit,34pins connector
I/O DATA PORT
16 bit DATA+2 STROBEs40pins connector
VME P1 connector
Block Diagram of the PCD
3/3/99 9
ispLSIispLSI
DIO
dTTL
VMEispLSIispLSI
DIO
dTTL
VME
FIFO
PCD-Transceiver in TOF/Trigger crate PCD-Receiver in Silicon crate
20MB/sec
64K*16
• No need for Event Builder and CODA• Simple, deterministic synchronization
Data Transfer Using PCD (Suggestion)
3/3/99 10
• Schematic drawing is finished• PCB design is ready
• feasibility analysis for implementation of 1/n• Production of 10-15 PCD boards• ispLSI programming for ENG & ING • ispLSI programming for TR&ER
To Do:
Current Status for 2/25/99
3/3/99 11
EN
G
PP
CP
PC
PP
C
ING
TR
&E
R
TR
&E
R
ING
Silicon
Trigger
TOF
EN
G
PP
CP
PC
PP
C
ING
TR
&E
R
TR
&E
R
ING
Silicon
Trigger
TOF
RC
VS
ND
RC
VMinimal, with external Event Builder
PPC: VME PowerPC processorENG: Event number generatorING: Interface to ENGTR&ER: Trigger register and enable registerRCV: receiving FIFOSND: sender
Ethernet to EB Ethernet to Logger
Maximal, with Event Builder inside one of the VME crates
Configuration of the VME Crates