20141018roorkee Cas Ws

7/25/2019 20141018roorkee Cas Ws

1/135

Synthesis of opamp and phase-locked loop

topologies from first principlesIEEE CAS SBC Workshop on

Advanced Topics in VLSI Circuit Design

Roorkee, India

Nagendra Krishnapura

Department of Electrical EngineeringIndian Institute of Technology, Madras

Chennai, 600036, India

18 October 20141 / 135
http://find/http://goback/

7/25/2019 20141018roorkee Cas Ws

2/135

Motivation

Intuition before full blown analysis

Synthesis instead of ad-hoc introduction

Time domain reasoning/analysis More intuitive Exact analysis difficult for complex systems

Frequency domain analysis

More abstract

Can handle complex systems easily

2 / 135

7/25/2019 20141018roorkee Cas Ws

3/135

Outline

Negative feedback with integrator as the central element

Synthesis of opamp topologies Synthesis of phase locked loop topologies

Conclusions

3 / 135

7/25/2019 20141018roorkee Cas Ws

4/135

Negative feedback with integrator as the central

element

4 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

5/135

Outline

Traditional introduction to negative feedback systems

Integrator as controller in a negative feedback system

Intuition and analysis in the time domain

Pedagogical advantages of the proposed introduction

Conclusions

5 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

6/135

Traditional introduction to negative feedback systems

Vo

-+Vi

A

Algebraic systemcannot explain evolution over time

Unstable with arbitrarily small loop delay

Ideal delayTdin the loop oscillations with a period 2Td

Real systems have non-zero delay and dont respond

instantaneously

6 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

7/135

Intuitive understanding of negative feedback systems

controller(e.g. speed)

sensor output

outputerrortarget

-+

(e.g. speedometer)

(e.g. speedometer reading)

controller: change the outputuntil error goes to zero

sensor

Compare the sensed output to the target (desired output)

Continuouslychange the output until the output

approaches the target

7 / 135

7/25/2019 20141018roorkee Cas Ws

8/135

Example: Driving a car at a given target speed

controller: accelerate or brakeuntil speed error goes to zero

controllerspeed

speedometer reading

output

speedometer

errortarget speed

-+

Compare the sensed speed to the target Speedometer reading to desired speed

Compute (mentally) the difference Look at the speedometer!

Keep accelerating (or braking) until errorgoestozero8 / 135

7/25/2019 20141018roorkee Cas Ws

9/135

Example: Driving a car at a given target speed

controller: accelerate or brakeuntil speed error goes to zero

controllerspeed

speedometer reading

output

speedometer

error

target speed

-+

You dont know how much to press the accelerator or the

brake to obtain the desired speed

Youkeep on doing ituntil the sensed speed is the same as

the target9 / 135

7/25/2019 20141018roorkee Cas Ws

10/135

Other examples

Driving a car

Controlling the volume: Keep turning the volume knob untilthe sensed volume (what your hear) matches target

volume(that you find comfortable)

10 / 135

7/25/2019 20141018roorkee Cas Ws

11/135

Nature of the controller

controller(e.g. speed)

sensor output stuck

outputerrortarget

-+

(e.g. speedometer)

t t

erro

r

stuck sensor

output

small error

large error

small error

large error

constant

Controller integrates the error

11 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

12/135

Negative feedback system with an integrator

(e.g. speed)

sensor output

outputerrortarget

-+

(e.g. speedometer)

(e.g. speedometer reading)

integrator: change the outputuntil error goes to zero

sensor

dt

12 / 135

7/25/2019 20141018roorkee Cas Ws

13/135

Negative feedback amplifier

Vo

-+Vi

Vfb

Veu dt

sensing

the output

computing

the error

R

(k

-1)R

Need the output Voto be gainktimes the inputVi

CompareVo/ktoViand integrate the error

Steady state whenVo= kVifor constantVi

13 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

14/135

Integrator in the negative feedback amplifier

Ve u dt Vo= u Vedt

Ve=1V

t [ns]

Vo[V]

1 2 3 4

4

32

1

u= 10

9

rad/s

u= 2.5x108rad/s

Proportionality constantu

Slope of the output = uVe

14 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

15/135

Integrator: Frequency domain

Ve(s) us

Vo(s) =us

Ve(s) 109

108

|u/j|

107 (log)

[rad/s]

-20dB/decade

109108

7/25/2019 20141018roorkee Cas Ws

16/135

Integrator: Summary

Ve u dt Vo= u Vedt

Ve=1V

t [ns]

Vo[V]

1 2 3 4

4

3

2

1

u= 109rad/s

u= 2.5x108rad/s

Ve(s) us

Vo(s) = usVe(s)

109108

|u/j|

107 (log)

[rad/s]

-20dB/decade

16 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

17/135

Negative feedback amplifier with constant input

0 1 2 3 4 5 60

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

time [ns]

Volts

Negative feedback amplifier, k=4,u=10

9rad/s

Input Vi

Feedback Vf

Error Ve

0 1 2 3 4 5 60

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

time [ns]

Volts


9rad/s

Ideal output 4Vi

Actual output Vo

Error reduces as feedbackVframps up

Reduced error slows the rate of output ramp

17 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

18/135

Negative feedback amplifier with constant input

+-

u dt

(k-1)R

R

Vi Vo

Vf

Ve

0 1 2 3 4 5 6

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

time [ns]

Vo

lts


9rad/s

Input Vi

Ideal output 4Vi

Initial condition=0V



dVo

dt = u

Vi

Vo

k

(1)

Vo(t) = kVi1 exp(u

k

t) + Vo(0) exp(u

k

t) (2)

18 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

19/135

Negative feedback amplifierSteady state

Vo

-+Vi

Vfb= Vi

Ve=0

(k-1)R

R

u dt

Zero state error for a constant inputVi(Vo= kVi)

19 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

20/135

Opamp for implementing a negative feedback amplifier

Vo

-+

Vi

Vfb

Ve

u dt

+

Ve

+

-

ViVo

Vfb

(k-1)R

u

computing

the error

RR

(k-1)R

20 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

21/135

Time domain behavior with constant/step inputs

Vo

-+Vi

Vfb

Veu dt

+

Ve+

-

ViVo

Vfb

(k-1)R

u

computing

the error

RR

(k-1)R

1

u

dVo

dt = Vi

Vo

k

Vo(t) = kVp

1 exp

uk

t

Time constantk/u

Asymptotically reachesVo= kViorVfb= Vi21 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

22/135

Relation to frequency domain analysis

Loop gainL(s) =

uks =

u,loops

Frequency domain:

Unity loop gain frequencyu,loop

Significant negative feedback up tou,loop nearly ideal

behavior up tou,loop(Closed loop Bandwidth)

loop= 1

u,loop

Time domain: Unit step response of the loop gain

= t/(1/u,loop) = t/loop

Closed loop response time constant = 1/u,loop= loop

22 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

23/135

Advantages of this formulation

Not instantaneous-unrealistic anyway

Time evolution naturally built in

Synthesis from common experience of negative feedback

based adjustment in the time domain-amplifier not

arbitrarily thrown in

Intuition and key results obtained from time domainreasoning

Exponential settling

23 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

24/135

Controlled sources using an opamp

Our opamp compares voltages; Therefore, voltages have to be

compared for all controlled sources; opamps that compare

currents can also be used

VCVS:Vo= kVi; CompareVo/ktoVi

CCVS:Vo= RfIi; CompareVoRfIito 0

VCCS:Io= GmVi; CompareIo/Gmto Vi

VCVS:Io= kIi; CompareIoR kIiRto 0

24 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

25/135

Voltage controlled voltage source

VoVi

Vfb= Vi

(k-1)R

R

+

VCVS:Vo= kVi

CompareVo/ktoViand drive the output with the integralof the error

For constantVi,Vo= kViin steady state

25 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

26/135

Current controlled voltage source

Vo0

Vo-IiRf

+

RfIi

VCVS:Vo= RfIi

CompareVo RfIito 0 and drive the output with theintegral of the error

For constantIi,Vo= RfIiin steady state

26 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

27/135

Voltage controlled current source

Vi

Io/Gm

R=1/Gm

+

+

Vopa

Vopa

Io

Io

load

VCCS:Io= GmVi

CompareIo/Gmto Viand drive the output with the integralof the error

For constantVi,Io= GmViin steady state

27 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

28/135

Current controlled current source

R

+

+

Vopa

Vopa

Ioload

0

Ii (k-1)R

IoR-kIiR

Io

Ii

CCCS:Io= kIi

Compare (Io kIi)Rto 0 and drive the output with theintegral of the error

For constantIi,Io= kIiin steady state

28 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

29/135

Negative feedback amplifier with delay

controller: change the output

until error goes to zero

controllertarget

sensed output

output

sensor

error

+-

(delay Td)

controllertarget

sensed output

output

sensor

error

+-

controller: change the output

until error goes to zero

delay Td

Delay is inherent in negative feedback loops. e.g.

Speedometers delay in computing speed

Excess delays can occur in any part of thesystem-modeled in the feedback path

29 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

30/135

Effect of delay on negative feedback

0 1 2 3 4 52

1.5

1

0.5

0

0.5

1

1.5

2

2.5

3

target

outputfeedbackerror

Dont know that we have already reached the target

Overshoot the target and then start falling

The process repeats on the other sideringing or

oscillation

30 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

31/135

Effect of delay on negative feedback

0 2 4 6 8 101.5

1

0.5

0

0.5

1

1.5

2

2.5

target

outputfeedbackerror

Dont know that we have already reached the target

Overshoot the target and then start falling

The process repeats on the other sideringing or

oscillation

31 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

32/135

Negative feedback amplifier with delay-Intuition

A small delay doesnt matterHow small?

If there is a long delay, integrate more slowly to avoidovershootHow slowly?

32 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

33/135

Negative feedback amplifier with delay in the loop

Vo

-+Vi

Vfb

Veu dt

delay Td

R

(k-1)R

Td/loop 1/e(= 0.367): No overshoot

1/e

7/25/2019 20141018roorkee Cas Ws

34/135


0 2 4 6 8 100

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

time [normalized to k/u]

Vo

[normalizedtokVi]

Td/(k/

u) = 0

Td/(k/

u) = 1/e

Td/(k/

u) = 0.5

Td/(k/

u) = 1.0

Td/(k/

u) = 1.5

34 / 135

f db k l fi h d l h l
http://find/

7/25/2019 20141018roorkee Cas Ws

35/135


Td/loop 1/e 0.445 0.465 0.5 0.585 0.695

(0.367)

35 / 135

Eli i i i bili i f d l
http://find/

7/25/2019 20141018roorkee Cas Ws

36/135

Eliminating instability in presence of delay

Stability governed by the ratio ofTdtoloop

ReduceTd: Faster circuit/technology Increaseloop Decreaseu,loop: Slower integration

36 / 135

D l i i i i l i i i l d
http://find/

7/25/2019 20141018roorkee Cas Ws

37/135

Delays in circuit implementationparasitic poles and zeros

Loop gainL(s) = u,loops

Ideal

Mk=1(1 + s/zk)N

k=2(1 + s/pk) Parasitic

Td Td

slope=u,loop slope=u,loop

tt

Unit step response ofL(s) is a ramp of slopeu,loop(same as

ideal) with a delay Td=N

k=1 1/pkM

k=1 1/zk

37 / 135

Cl d l ith i l t d l
http://find/

7/25/2019 20141018roorkee Cas Ws

38/135

Closed loop response with equivalent delay

38 / 135

Ad t f thi f l ti
http://find/

7/25/2019 20141018roorkee Cas Ws

39/135


Not instantaneous-unrealistic anyway

Time evolution naturally built in

Synthesis from common experience of negative feedback

based adjustment in the time domain-amplifier notarbitrarily thrown in

Intuition and key results obtained from time domainreasoning

Exponential settling Possibility of ringing, overshoot, and instability

39 / 135

http://find/

7/25/2019 20141018roorkee Cas Ws

40/135


Traditional viewpoint

Memoryless amplifier (loop gain) in the ideal case Frequency dependence as non-ideal feature

Proposed viewpoint Integrator in the ideal case ( dc gain) Finite dc gain due to non-ideal implementation

As easy as the gain model to convert to ideal opamps

40 / 135

Opamp models
http://find/

7/25/2019 20141018roorkee Cas Ws

41/135

Opamp models

d u

p2p3

A0

finite dc gain model: A0

integrator model: u/sfirst order model: A0/(1+s/d)

full model: A0/(1+s/d)(1+s/p2)(1+s/p3) ...

|Vout/Vd|(dB)

41 / 135

http://find/

7/25/2019 20141018roorkee Cas Ws

42/135


u,loopmore fundamental characteristic of the negativefeedback loop than dc loop gain

Increasingu,looprequires higher power Increasing dc loop gain indirectly influences power

42 / 135

http://find/

7/25/2019 20141018roorkee Cas Ws

43/135


Loop gain of all feedback systems has integrator-likebehavior over some frequency range

Nyquist plot should enter the unity circle near the negativeimaginary axis Bode plot should have 20 dB/decade slope near the unity

gain frequency

43 / 135

http://find/

7/25/2019 20141018roorkee Cas Ws

44/135


Clear why fastest negative feedback systems are slower

than fastest open loop systems

Clear why max. speed of negative feedback systems

increases with technology

44 / 135

http://find/

7/25/2019 20141018roorkee Cas Ws

45/135


Leads directly to opamp and phase locked loop topologies

45 / 135

References
http://find/

7/25/2019 20141018roorkee Cas Ws

46/135

References

Adel S. Sedra and Kenneth C. Smith, Microelectronic Circuits, 6th ed., Oxford University Press 2009.

Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer,Analysis and Design of Analog Integrated

Circuits, 5th ed., Wiley 2009.

Nagendra Krishnapura, Introducing Negative Feedback with an Integrator as the Central Element,Proc.

2012 IEEE ISCAS, May 2012.

Nagendra Krishnapura, Synthesis Based Introduction to Opamps and Phase Locked Loops, Proc. 2012

IEEE ISCAS, May 2012.

Karl J. Astrom and Richard M. Murray, Feedback Systems: An Introduction for Scientists and Engineers,

Available:http://www.cds.caltech.edu/murray/amwiki/index.php/Main_Page

Barrie Gilbert, Opamp myths, Available: http://pe2bz.philpem.me.uk/

Parts-Active/IC-Analog/OpAmps/OpAmpMyths/c007-OpAmpMyths.htm

Hal Smith,An Introduction to Delay Differential Equations with Applications to the Life Sciences, 1st ed.,Springer 2010.

Nagendra Krishnapura, EE5390: Analog Integrated Circuit Design, Available:

http://www.ee.iitm.ac.in/nagendra/videolectures

46 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

47/135

Synthesis of opamp topologies

47 / 135

Opamp (integrator) realization
http://find/

7/25/2019 20141018roorkee Cas Ws

48/135


+

Gm1C1

1

+

-Ve

IgmVout Vout,buf

Vo = Gm1

C1

Vedt (3)

= u Vedt (4)(5)

Gm Cintegrator

u= Gm1/C1

48 / 135

Opamp (integrator) realizationFinite dc gain
http://find/

7/25/2019 20141018roorkee Cas Ws

49/135

Opamp (integ ato ) ealization inite dc gain

++

-Ve

C1Gm1 Ro1

Igm

1Vout Vout,buf

FiniteRo1 Finite dc gain Steady state error

49 / 135

Steady state error due to finite dc gain
http://find/

7/25/2019 20141018roorkee Cas Ws

50/135

y fi g

0 2 4 6 8 100

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

t/

V

Step response

IdealA

o=10

50 / 135

http://find/

7/25/2019 20141018roorkee Cas Ws

51/135

p p ( g )

++

-Ve

C1Gm1 Ro1

Igm

1Vout Vout,buf

Simplest realization: Single stage opamp

EnhancedRo1: Cascode opamp (But, sameu)

51 / 135

Transimpedance amplifier for better I-V conversion
http://find/

7/25/2019 20141018roorkee Cas Ws

52/135

p p fi f

IGm ZcRo1

part of IGm(=Vo/Rout)

52 / 135

Transimpedance amplifier for better I-V conversion
http://find/

7/25/2019 20141018roorkee Cas Ws

53/135

p p fi f

IGm ZcRo1

part of IGm(=Vo/Rout)

Vo

Vo-IGmZc

+

Zc

+

-Vx u

IGm Ro1

smaller part ofIGm(=Vx/Rout)

53 / 135

Improved I-V conversionTwo stage opamp
http://find/

7/25/2019 20141018roorkee Cas Ws

54/135

+

-Ve

Gm1 Ro1

Igm

C1

+

54 / 135

http://find/

7/25/2019 20141018roorkee Cas Ws

55/135

+

-Ve

Gm1 Ro1

Igm

C1

u2 dt

integrator+

-Ve

Gm1

Igm

C1

continuously adjustsVountil Ve0

monitors Veand

Ve=Vo-IGmZc

Vo

+

+

Ro1

55 / 135

http://find/

7/25/2019 20141018roorkee Cas Ws

56/135

+

-Ve

Gm1 Ro1

Igm

C1

u2 dt

integrator+

-Ve

Gm1

Igm

C1


monitors Veand

Ve=Vo-IGmZc

Vo

+

+

Ro1

+

C2Ro2

C1

Gm2

+

-

Ve

Gm1

Igm

+Ro1

56 / 135

Negative feedback amplifier: Frequency domain
http://find/

7/25/2019 20141018roorkee Cas Ws

57/135

(log)

+-

u dt

(k-1)R

R

Vi Vo

Vf

Ve

u/s

uu/k

|A(j)|

loop gain

(log)u/k

|Vo/Vi|

k

ideal over this band

Desired behavior in the region where loop gain is high

57 / 135

Negative feedback amplifier: Frequency domain99
http://find/

7/25/2019 20141018roorkee Cas Ws

58/135

102

101

100

101

101

100

101

Magn

itude


9rad/s

102

101

100

101

100

50

0

[Grad/s]

Phase

1 0.5 0 0.5 11

0.8

0.6

0.4

0.2

0

0.2

0.4

0.6

0.8

1


9rad/s

[Grad/s]

[Grad/s]

Pole at 250Mrad/s

Vo(s) =

u

s ViVo

k (6)Vo(s)

Vi(s) =

k

1 + su/k(7)

First order response; DC gain = k, poleatu/k58 / 135

Negative feedback amplifier: Sinusoidal input
http://find/

7/25/2019 20141018roorkee Cas Ws

59/135

Vo(j)

Vi(j) =

k

1 + ju/k(8)

Vo(j)Vi(j) = k1 +

u/k

2 ; Vo(j)

Vi(j) = tan

1

u/k(9)

dc gain: k(= desired value)

3 dB bandwidth: u/k

59 / 135

Negative feedback amplifier: Low frequency input
http://find/

7/25/2019 20141018roorkee Cas Ws

60/135

0 50 100 150 200 2504

3

2

1

0

1

2

3

4

time [ns]

Volts

Negative feedback amplifier, k=4, u=10

9rad/s

Input at 0.1u/k

inputideal outputactual output

Vo(j)Vi(j) = k

1 +

u/k

2(10)

Vo(j)

Vi(j) = tan1

u/k(11)

(12)

Nearly ideal behavior Gaink, delayk/u

60 / 135

Negative feedback amplifier: High frequency input
http://find/

7/25/2019 20141018roorkee Cas Ws

61/135

0 0.5 1 1.5 2 2.54

3

2

1

0

1

2

3

4

time [ns]

Volts

Negative feedback amplifier, k=4, u=10

9rad/s

Input at 10u/k

inputideal outputactual output

Vo(j)Vi(j) = k

1 +

u/k

2(13)

Vo(j)

Vi(j) = tan1

u/k(14)

(15)

Attenuated output Nearly 90 phase lag

61 / 135

Intuition about two stage opamp constraints
http://find/

7/25/2019 20141018roorkee Cas Ws

62/135

I-V conversion bandwidth unity loop gain frequency

u,desired< u,inner

Gm1C

< Gm2C2

Bias current determined byGm

Higher bias current in the second stage

62 / 135

Further improved I-V conversionThree stage opampC
http://find/

7/25/2019 20141018roorkee Cas Ws

63/135

+

-Ve

Gm1 Ro1

Igm

C1

u2 dt

integrator+

-Ve

Gm1

Igm

C1


monitors Veand

Ve=Vo-IGmZc

Vo

+

+

Ro1

63 / 135

Further improved I-V conversionThree stage opampC
http://find/

7/25/2019 20141018roorkee Cas Ws

64/135

+

-Ve

Gm1 Ro1

Igm

C1

u2 dt

integrator+

-Ve

Gm1

Igm

C1

continuously adjusts

Vountil Ve0

monitors Veand

Ve=Vo-IGmZc

Vo

+

+

Ro1

+

Gm3

Vout

C2

two stage opamp

Ro3 C3Gm2 Ro2

++

-Ve

Gm1

Igm

+

Ro1

C1

64 / 135

Further improved I-V conversionThree stage opamp
http://find/

7/25/2019 20141018roorkee Cas Ws

65/135

+

Gm3

Vout

C2

two stage opamp

Ro3 C3Gm2 Ro2

++

-Ve

Gm1

Igm

+

Ro1

C1

65 / 135

Intuition about three stage opamp constraints
http://find/

7/25/2019 20141018roorkee Cas Ws

66/135

I-V conversion bandwidth unity loop gain frequency

u,desired< u,inner

Gm1C

< Gm2C2

< Gm3C3

Bias current determined byGm

Higher bias currents in the third stage, second stage

66 / 135

Follow up in the frequency domain
http://find/

7/25/2019 20141018roorkee Cas Ws

67/135

Analyze in frequency domain and relate to time domain resultsand intuition

Two stage opamp

DC gain Pole locations, pole splitting (with load) Stability constraints RHP zero and its cancellation

Three stage opamp

DC gain Pole locations Stability constraints Zero pair and their optimization

67 / 135

Opamp (integrator) realizationFinite dc gain
http://find/

7/25/2019 20141018roorkee Cas Ws

68/135

Gm1 Ro1

Igm

C1

+

+-Ve

Vi

68 / 135

Opamp realizationSupply extra current from another

source
http://find/

7/25/2019 20141018roorkee Cas Ws

69/135

source

continuously adjust

IoffIoffuntil Ve=0

monitor Veand

Gm1 Ro1

Igm

C1

+

+-Ve

Vi

Gm1 Ro1

Igm

C1

+

+-Ve

Vi

69 / 135

Opamp realizationAdditional negative feedback control
http://find/

7/25/2019 20141018roorkee Cas Ws

70/135

+-Ve

+Kpd,I dt

integrator

Vi

Gm1 Ro1

Igm

C1

+

IoffGm2a

Vo

70 / 135

Opamp realizationAdditional negative feedback control
http://find/

7/25/2019 20141018roorkee Cas Ws

71/135

+

+

C2Ro2

+-Ve

+-Ve

+Kpd,I dt

integrator

Vi Vi

Gm1 Ro1

Igm

C1

+

Ioff

Gm1 Ro1

Igm

C1

+

Ioffopamp

Gm2aGm2

Gm2a

Vo Vo

71 / 135

Two stage feedforward opamp
http://find/

7/25/2019 20141018roorkee Cas Ws

72/135

+

+

C2Ro2

+-Ve

Vi

Gm1 Ro1

Igm

C1

+

Ioffopamp

Gm2aGm2

72 / 135

Intuition about feedforward opamp constraints
http://find/

7/25/2019 20141018roorkee Cas Ws

73/135

Additional path operates onsteady stateerror of the first stage

Additional pathslowerthan main path Doesnt contribute to extra power consumption

73 / 135

Feedforward opamp settling
http://find/

7/25/2019 20141018roorkee Cas Ws

74/135

Additional path operates onsteady stateerror of the first stage

Additional path too fast

Overshoot, instability

Additional path too slow

Initial settling to low accuracy Creeps up to high accuracy Pole-zero doublet problem

Not suitable for step-like outputs

Lower power consumption for smoother outputs

74 / 135

Feedforward opamp settlingStep response
http://find/

7/25/2019 20141018roorkee Cas Ws

75/135

0 10 20 30 40 500

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

t/

V

Single stage opamp, Ao=100

Single stage opamp, Ao=10

Feedforward opamp, Ao=100, 10

45 46 47 48 49 500.96

0.97

0.98

0.99

1

75 / 135

Three stage feedforward opamp
http://find/

7/25/2019 20141018roorkee Cas Ws

76/135

+

+

Ro2

+

+

C3Ro3

+

-

VeVi

Gm1 Ro1

Igm

C1

+

IoffGm2a

Gm2 C2

Gm3Gm3a

two stagefeedforward opamp

Vo

76 / 135

Follow up in the frequency domain
http://find/

7/25/2019 20141018roorkee Cas Ws

77/135

Analyze in frequency domain and relate to time domain resultsand intuition

Two stage feedforward opamp

Closed loop response

Zero location Pole-zero doublet

Three stage opamp

Closed loop response Location of zeros

Poles and zeros

77 / 135

http://find/

7/25/2019 20141018roorkee Cas Ws

78/135

Easy derivation of actual implementation of opamps

Mysterious looking steps leading to stabilization are

removed Intuitive understanding of constraints in Miller and

feedforward opamps

78 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

79/135

Synthesis of phase locked loop topologies

79 / 135

Outline
http://find/

7/25/2019 20141018roorkee Cas Ws

80/135

Phase locked loop (PLL) requirements

PLL frequency multiplier

Derivation Phase model

Type-I PLL

Practical phase detectors Type-I PLL limitations

Type-II PLL

Feedback systems and stability Type-II PLL

LC oscillator

Programmable frequency divider

80 / 135

Phase locked loops
http://find/

7/25/2019 20141018roorkee Cas Ws

81/135

Frequency synthesizers in radios for local oscillators

Frequency multiplication for reference clock generation

Phase alignment

81 / 135

Local oscillator requirements10kHz interchannel spacing

0.15MHzchannelspacing

bandwidth

Broadcast FM bandBroadcast AM band
http://find/

7/25/2019 20141018roorkee Cas Ws

82/135

5kHz

ffc

530kHz

1610kHz

88MHz

108MHz

0.2MHz

88.2

MHz

890MHz

915MHz

0.2MHz

channelspacing

890.2

MHz

GSM uplink band

935MHz

960MHz

0.2MHz

channelspacing

935.2

MHz

GSM downlink band

Tuned to the desired channel frequency plus an

intermediate frequency (IF) Generate equally spaced frequencies from a reference

frequency 82 / 135

Frequency divider

V
http://find/

7/25/2019 20141018roorkee Cas Ws

83/135

Vref

Vref/Nfref fref/N

R

R(N-1)

N

frequencydivider

Digital frequency divider can generate multiple frequencies

Frequencies not equally spaced

Reference frequency higher than output frequencies

83 / 135

Frequency multiplication analogous to voltage amplification
http://find/

7/25/2019 20141018roorkee Cas Ws

84/135

+-

u dt

(k-1)R

R

Vi Vo

Vf

Ve+

-

u dtfe

inputfrequency

fref

outputfrequency

fout

fout/N

frequencyerror

1/N

84 / 135

Frequency multiplication
http://find/

7/25/2019 20141018roorkee Cas Ws

85/135

Vctl

fref

fout/N

+-

zero, at steady state

Nfrequencymeasure

frequencymeasure

frequency difference

frequencydivider

dt

inputsignalat fref

outputsignalat fout

fout= ffree+KvcoVctl

VCO

85 / 135

Phase and frequency
http://find/

7/25/2019 20141018roorkee Cas Ws

86/135

Sinusoid: cos((t)) Phase: (t)

Instantaneous frequency: fi= 12

d(t)dt

Typically expressed asfi= fo+ fe(t)

fo: average frequency fe: instantaneous frequency error

Phase(t) = 2fot+ o+ 2

fe(t)dt

Phase(t) = 2fot+ o+ (t)

o: phase offset-ideal ramp versus time

(t): instantaneous phase

86 / 135

Phase error70

ideal phaseerror
http://find/

7/25/2019 20141018roorkee Cas Ws

87/135

0 2 4 6 8 1010

0

10

20

30

40

50

60errorphase with error

87 / 135

Integrate frequency difference Phase difference
http://find/

7/25/2019 20141018roorkee Cas Ws

88/135

Vctl

+-

N

frequencymeasure

signalat fref

output

at foutVCO

frequencydivider

measurefrequency

measure phase

measure phasemeasure phase difference

dt

dt

input

signal


88 / 135

Type-I phase locked loop
http://find/

7/25/2019 20141018roorkee Cas Ws

89/135

Vctl

N

output signalat fout

frequency

divider

input signal at frefphase

detector


VCO

Phase detector and VCO in a loop

89 / 135

Voltage controlled oscillator

fout

slope = Kvco
http://find/

7/25/2019 20141018roorkee Cas Ws

90/135

fo

out

Vctl

Vctl fout=KvcoVctl+fo

dt2Kvco

2fot

++Vctl vco

fvco= fo+ KvcoVctl fo: Free running frequency

vco= 2fot+ 2Kvco

Vctldt

Kvco: VCO gain in Hz/V

90 / 135

Phase detector
http://find/

7/25/2019 20141018roorkee Cas Ws

91/135

Kpd(1-2)phasedetector

1

2

Kpd: Phase detector gain in V/radian

Ideal phase detector: assumed to have an output

Vpd

= Kpd

(1

2)

91 / 135


V (f f )/KIn steady state, output signal at fout

(fout=Nfref at
http://find/

7/25/2019 20141018roorkee Cas Ws

92/135

N

frequency

input signal

at fref

VCO

Kpd

Kpd

phasedetector

Vctl= (fout-ffree)/Kvco

Vctl

(fout Nfrefatsteady state)

divider

In steady state,

= (fout-ffree)/KvcoKpd

= ref-out/N

Phase offset = (fout ffree)/KvcoKpdbetween input and

feedback signals || limited to ndue to periodic nature of phase

Limited lock range |fout ffree|

92 / 135

Phase locked loop model

f

2fot
http://find/

7/25/2019 20141018roorkee Cas Ws

93/135

2fout/N t+vco/N

2freft+ref

+-

Kpd

1/N

2foutt+out++Vctl

dt2Kvco

Vctl= 2(fref-fout/N)t + ref- out/N

At steady state, fref=fout/N; Vctl= ref- out/N

Modelled in terms of phases of signals

At steady state (lock),Vctlis a constant fref = fout/N The loop locks with

Vctl= Kpd(refout/N) = (Nfref fo)/KvcoThis is theoperating point of the circuit

93 / 135

Phase locked loop model
http://find/

7/25/2019 20141018roorkee Cas Ws

94/135

2freft+ref+ref

+-

Kpd

1/N

++Vctl+vctl

2fot

2fout/N t+out/N+out/N

2foutt+out+outdt2Kvco

An incrementrefin the input phase causes incrementsout,v

ctl

94 / 135

Phase locked loop modelincremental picture

ref vctl out
http://find/

7/25/2019 20141018roorkee Cas Ws

95/135

ref

+-

Kpd

1/N

vctl

out/N

out

dt2Kvco

An incrementrefin the input phase causes incrementsout,vctl

Type-I loopOne integrator in the loop

Phase model of the PLL

95 / 135

Phase locked loop modelfrequency domain

ref(s) Kpd

vctl(s) out(s)2Kvco
http://find/

7/25/2019 20141018roorkee Cas Ws

96/135

+

-

Kpd

1/N

out(s)/N

s

Loop gainL(s) = 2KpdKvco/Ns

Transfer function

out(s)/ref(s) = N/(1 + Ns/(2KpdKvco)) Type-I loopOne integrator in the loop

Closed loop bandwidth (= unity loop gain frequency)= 2KpdKvco/Nrad/s

96 / 135

Type-I PLLlimitations
http://find/

7/25/2019 20141018roorkee Cas Ws

97/135

Phase error when locked (fout= Nfref): refout/N= (Nfref fo)/KvcoKpd dc value ofKpdmatters; We have a constantKpd

|refout/N|

7/25/2019 20141018roorkee Cas Ws

98/135

Frequency divider output has a varying duty cycle

Phase detector should sensitive to duty cycle

XOR gate etc. are not preferable

Phase detector should be sensitive onlyto rising edges (or

onlyto falling edges) of inputs

98 / 135

Tri-state phase detector

1 QA
http://find/

7/25/2019 20141018roorkee Cas Ws

99/135

+10-1

A A

A

B B

B

D Q

RST

D Q

RST

1

1

A

B

QA

QB

ref

div

output=QA-QB

Output +1,1, 0 +1 if reference leads divider output

1 if reference lags divider output 0 if reference coincides with divider output

99 / 135

Tri-state phase detector-waveforms

Tref Tref
http://find/

7/25/2019 20141018roorkee Cas Ws

100/135

+1

-1

+1

-1

+1

ref-div

ref

QB

+1

QA

A

B

+1

-1

+1

-1

+1

div-ref

ref

QB

+1

QA

A

B

A leading B A lagging B

Flip flops assumed to be reset instantaneously

100 / 135

Tri-state phase detector-frequency difference between inputs

A A D Q1 QA
http://find/

7/25/2019 20141018roorkee Cas Ws

101/135

+10-1

A A

A

B B

B

D Q

RST

D Q

RST

1

A

B

QB

ref

div

output=QA-QB

fA>fB: Eventually get two consecutive edges of A

Circulates between 0 and +1 states: Average output>0

Similarly, average output>0 forfA

7/25/2019 20141018roorkee Cas Ws

102/135

-1

+1

-1

+1

-1

= ref-div

Average value = /

divider o/pdivider o/p

reference pdout

pdout

Tref Output periodic at fref

Tri-statephasedetector

Vout(f) =

2

n=

sincn

2 (f nfref)

Vout(t) =

2 +

n=1

sinc

n

2

cos(2nfreft)

102 / 135

Tri-state phase detector

O l /2
http://find/

7/25/2019 20141018roorkee Cas Ws

103/135

Output average value = /2 Kpd= 1/2 Phase detector offset = 0 Loop locks with = ref out/N= 0 forN fref = fo Input range = 2 PLL lock range =fo 2KpdKvco

7/25/2019 20141018roorkee Cas Ws

104/135

0 2 4 6 8 100.2

0

0.2

0.4

0 2 4 6 8 100.5

0

0.5

=/8

f/fref

104 / 135

PLL with tri-state phase detectorperiodic errornancos(2nfreft) ("error")
http://find/

7/25/2019 20141018roorkee Cas Ws

105/135

ref+

-

Kpd

1/N

vctl

vco/N

outdt2Kvco+

+

Errore(t) added to the input of the phase detector

Disturbances in the VCO output phaseout(t) even with aperfect reference(ref(t) = 0)

VCO output: cos(2Nfreft+ Nref+ out(t))

VCO output not periodic atNfref105 / 135

Phase error

60

70ideal phaseerrorphase with error
http://find/

7/25/2019 20141018roorkee Cas Ws

106/135

0 2 4 6 8 1010

0

10

20

30

40

50

phase with error

106 / 135

PLL with tri-state phase detectorfrequency domain

E(j2f) = nan/2 (fnfref)E(s)
http://find/

7/25/2019 20141018roorkee Cas Ws

107/135

ref(s)+

-

Kpd

1/N

vctl(s)

vco(s)/N

out(s)2Kvco

s+

+

ref(s) = 0 for a perfectly periodic reference

Transfer function from the error to the outputout(s)/E(s) = out(s)/ref(s) = N/(1 + Ns/(2KpdKvco))

E(j2f) =

n(an/2)(f nfref)

107 / 135

Type-I PLL

out(s)

E(s) =

out(s)

(s) (16)
http://find/

7/25/2019 20141018roorkee Cas Ws

108/135

E(s) ref

(s)

= N 2KpdKvco/Ns

1 + 2KpdKvco/Ns (17)

= N 1

1 + sN/2KpdKvco(18)

(19)

Loop gain

L(s) = 2KpdKvco

Ns

(20)

Closed loop bandwidth (Hz)

f3dB =

KpdKvco

N (21)

108 / 135

Type-I PLL

dB
http://find/

7/25/2019 20141018roorkee Cas Ws

109/135

20log(N)

dB

dB

loop gain |L|

2KpdKvco/N

2KpdKvco/N

L/(1+L)|out/ref|

(loop bandwidth)

109 / 135

Feedback system

In our system,

out (s) 2Kpd Kvco/Ns
http://find/

7/25/2019 20141018roorkee Cas Ws

110/135

out( )

E(s) = N

pd vco/

1 + 2KpdKvco/Ns (22)

In general, in a feedback system with a loop gain L(s)

Hclosedloop(

s) =

Hideal(

s)

L(s)

1 + L(s) (23)

(24)

WhereHideal(s) is the ideal closed loop gain (withL = ). Thiscan be approximated as

Hclosedloop(s) = Hideal(s)L(s) |L| 1 (25)

= Hideal(s) |L| 1 (26)

110 / 135

PLL with tri-state phase detectorOutput signalConsidering only the term atfref, andb1 1

Vout(t) = cos(2Nfreft+ b1 sin(2freft)) (27)
http://find/

7/25/2019 20141018roorkee Cas Ws

111/135

( ) ( ( ))

= cos(2Nfreft) cos(b1 sin(2freft)) (28)

sin(2Nfreft) sin(b1 sin(2freft)) (29)

cos(2Nfreft) b1 sin(2freft) sin(2Nfreft)(30)

= cos(2Nfreft) (31)

b1/2cos(2(N 1)freft) (32)

b1/2cos(2(N+ 1)freft) (33)

Spurious tones in the output at a spacing of freffrom thedesired frequencyReference feedthrough

In general, spurious tones will be present at nfreffrom thedesired PLL output

111 / 135

Reference feedthrough
http://find/

7/25/2019 20141018roorkee Cas Ws

112/135

b1 = a1|H(j2fref)| (34)

= a1N

KpdKvco/jNfref1 + KpdKvco/jNfref

(35)

a1NKpdKvcojNfref (36)= 2

Nf3dB

frefsinc

2 (37)

Maximum value ofb1 = 4KpdKvcowhen =

112 / 135

Reference feedthroughexample

To generate 1 GHz from 1MHz reference
http://find/

7/25/2019 20141018roorkee Cas Ws

113/135

g

b1/2 = 102 (spurious tones at (N 1)fref40 dB below thefundamental output atN fref)

N= 103

= (locked with a phase shift of)

f

3dB/f

ref = 5 106 f

3dB= 5 Hz

Lock range = 2Nf3dB 10 kHz

Lock range is too small; Cant switch to the next channel

which is 1 MHz away!

May not be able to lock for any value ofN, unless the free

running frequency happens to beNfreffor someN

113 / 135


In steady state, output signal at fout
http://find/

7/25/2019 20141018roorkee Cas Ws

114/135

N

frequency

input signalat fref

VCO

Kpd

Kpd

phase

detector

Vctl= (fout-ffree)/Kvco

Vctl

y

(fout=Nfrefatsteady state)

divider

In steady state,

= (fout-ffree)/KvcoKpd

= ref-out/N

= 0 iffouthappens to be equal tofref. Zero spurs!

114 / 135

Changing the free running frequency of a VCO
http://find/

7/25/2019 20141018roorkee Cas Ws

115/135

(ffree+KvcoVoff)+KvcoVctl ffree+KvcoVctlVctl

ffree = ffree+KvcoVoff

VoffVctl

VCOVCO

Add a bias to the input to change the free running

frequency

115 / 135

Slowly change the bias until = 0

continuously adjustVoff until =0

monitor and
http://find/

7/25/2019 20141018roorkee Cas Ws

116/135

+

Voffuntil 0

N

frequency

input signalat fref

Voff

= ref-out/NKpd

Kpd

phasedetector

divider

VCO

output signal at fout(fout=Nfrefat

steady state)

ffree

Slowly change the biasVoffuntil = 0

116 / 135

Slowly change the bias until = 0

Kpd I dt V = (f -f )/K KIn steady state,

phasedetector

integral
http://find/

7/25/2019 20141018roorkee Cas Ws

117/135

N

frequency

input signalat fref

Voff

Kpd

Kpd

Kpd,I dtpd,I

phasedetector

divider

In steady state,

= 0

Voff

(fout

ffree

)/Kvco

Kpd

VCO


steady state)

ffree

= ref-out/N

Measure and integrate it to controlVoff

117 / 135

Type-II phase locked loop

phaseintegral

phase detector + loop filter
http://find/

7/25/2019 20141018roorkee Cas Ws

118/135

N

input signal

at fref

Kpd

Kpd

Kpd,I dtKpd,I dt

In steady state,

= 0

VCO


steady state)

p

detector

= ref-out/N

phasedetector

proportional

Proportional + integral loop filter

118 / 135

Type-II PLL with a tri-state phase detector
http://find/

7/25/2019 20141018roorkee Cas Ws

119/135

Lock range is not limited by the phase detector

Loop locks with zero phase difference between reference

and feedback signals

tri-state phase detector output is zero for zero input phasedifference No reference feedthrough!

Reference feedthrough does exist in reality due to

mismatches

119 / 135

Type-II PLLphase model

2fotzero atsteady state
http://find/

7/25/2019 20141018roorkee Cas Ws

120/135

2fout/N t+out/N

-

Kpd

1/N

2foutt+out++Vctl

dt2Kvco

dVctl/dt 2(fref-fout/N)t + ref- out/N

At steady state, fref=fout/N; ref- out/N = 0;

dtKpd,I2freft+ref

+

+

+


120 / 135
http://find/

7/25/2019 20141018roorkee Cas Ws

121/135

Type-II PLLincremental model

Kpd,I

7/25/2019 20141018roorkee Cas Ws

122/135

-

Kpd

1/N

+

+

+

2Kvco

s

s

out(s)vctl(s)ref(s)

out(s)/N


122 / 135

Type-II PLLFrequency domain

p1> 2KpdKvco/N
http://find/

7/25/2019 20141018roorkee Cas Ws

123/135

-

Kpd

1/N

Vctl+

+

+

2Kvco

s

Kpd,I

s

1+s/p1

out(s)1vctl(s)ref(s)

out(s)/N

more poles can be used

123 / 135

Type-II PLLImplementation

+1

-1

+1 = ref-div

reference

di id /

Tref

divider o/p

reference iout

R1divider o/p

referenceiout

R1

+proportionaloutput

+

i t l

proportional

tri-statephasedetector

http://find/

7/25/2019 20141018roorkee Cas Ws

124/135

-1

+Icp

-Icp

divider o/p

pdoutdivider o/p

reference iout

C1

C1

+

-

-

integraloutput

-

+ integraloutput

+IcpR

-IcpR

slope=Icp/Cintegral

output

proportionaloutput


Phase detector with a current output (Icp)

Integral termKpd,I/s: Current flowing into a capacitorC1

Proportional termKpd

: Current flowing into a resistorR1

Series RC to obtain the sum

Kpd= IcpR1/2;Kpd,I= IcpC1/2

124 / 135

Tri-state phase detector with charge pump

Vdd

Icp
http://find/

7/25/2019 20141018roorkee Cas Ws

125/135

D Q

RST

D Q

RST

1

1

A

B

QA

QB

R1

C1

Icp

iout

(UP)

(DN)

ref

div

+

-

+ integraloutput

proportional

QAandQBdrive a charge pump Charge driven into the loop filterIcpTref/2

125 / 135

Noise sources in a PLL

+ 2Kvco

Kpd,I

s

outref

vnc

vco
http://find/

7/25/2019 20141018roorkee Cas Ws

126/135

-

Kpd

1/N

++

s

out/N

Noise can be added asref(reference phase noise,

charge-pump noise, divider output phase noise) orvnc(loop filter noise) orvco(VCO phase noise)

Need to compute transfer functions from each of these

noise sources toout

126 / 135

Type-II PLL: transfer functions

L(s) = u,loop z1

1 + s

1 (38)
http://find/

7/25/2019 20141018roorkee Cas Ws

127/135

s s z1u,loop =

2KpdKvco

N =

IcpRKvco

N (39)

z1 = Kpd,I

Kpd

= 1

RC

(40)

out(s)

ref(s) = N

1 + s/z11 + s/z1 + s2/z1u,loop

(41)

out(s)

Vnc(s) =

N

Kpd

s/z11 + s/z1 + s2/z1u,loop

(42)

out(s)

vco(s) =

s2/z1u,loop1 + s/z1 + s2/z1u,loop

(43)

127 / 135


L(s)

1 + L(s) =

1 + s/z1

1 + s/z1 + s2/z1 u loop(44)
http://find/

7/25/2019 20141018roorkee Cas Ws

128/135

1 + L(s) 1 + s/z1 + s2/z1u,loop

Two poles and a zero

Zeroz1 = Kpd,I/Kpd

Natural frequencyn= 2Kpd,IKvco/N Quality factorQ=

z1/u,loop=

NKpd,I/2Kvco/Kpd

Damping factor= 1/2Q= 1/2

u,loop/z1

For well separated (real) poles (z1 u,loop),

p1 z1 + z21 /u,loop z1,p2 u,loop z1,

Pole zero doublet {p1, z1};p1at a slightly higher frequencythanz1

128 / 135


5

0

5

dB

]2
http://find/

7/25/2019 20141018roorkee Cas Ws

129/135

103

102

101

100

101

25

20

15

10

/u,loop

1/N|

out/

ref|

[dB

103

102

101

100

1

0

1

2

=4.08

=0.3162

=1

out(s)

ref(s)

= N 1 + s/z1

1 + s/z1 + s2

/z1u,loop

(45)

Peaking in |out/ref| because of the zero

Damping factor 1 to avoid peaking slowsettling129 / 135


0

10

20

30

[d

B]

PLL transfer functions
http://find/

7/25/2019 20141018roorkee Cas Ws

130/135

102

101

100

101

102

70

60

50

40

30

20

10

f/fu,loop

Magnituderesponse

out

/ref

out/vnc*1V

out/

vco

(Example parameters:

N= 10, z1= 0.1u,loop, N/Kpd= 2Kvco/u,loop= 25 V1)

|out/ref|: Lowpass with a dc gainN

|out/vnc|: Bandpass with peak gainN/Kpd= 25 V1

|out/vco|: Highpass with a high frequency gain of 1

130 / 135

Type-II PLL phase noise example

80

60

40

20PLL phase noise components
http://find/

7/25/2019 20141018roorkee Cas Ws

131/135

102

101

100

101

102

180

160

140

120

100

80

f/fu,loop

dBc/Hz

reference

ref. contribution to PLL

VCOVCO contribution to PLL

Total

(Example parameters:

N= 10, z1= 0.1u,loop, N/Kpd= 2Kvco/u,loop= 25 V1)

Reference contribution dominant below 0.1u,loop VCO contribution dominant above 0.1u,loop VCO contribution reduced by the loop uptou,loop Charge pump and loop filter noise ignoredintheabove

131 / 135

Intuition about the Phase locked loop

Reason for using a phase detector for frequency synthesis
http://find/

7/25/2019 20141018roorkee Cas Ws

132/135

Reason for using a phase detector for frequency synthesis Reason for an additional integrator in the loop filter

Integral path for adjustingVoffslower than the mainpath (type-I)

PLL bandwidth (unity loop gain frequency) is the same as inthe type-I loop

Presence of a zero before the PLL bandwidth (unity loopgain frequency)

Integral path influences the phase transfer functions onlywell below the PLL bandwidth

132 / 135

Analysis of type-II phase locked loop
http://find/

7/25/2019 20141018roorkee Cas Ws

133/135

Pole zero locations

Phase (jitter) transfer functions

Higher order loop filter for higher spur suppression

133 / 135

Conclusions

Negative feedback: Continuous adjustment to reduce error
http://find/

7/25/2019 20141018roorkee Cas Ws

134/135

Negative feedback: Continuousadjustment to reduce error

Integrator is the key element of the negative feedback loop

Implementing a voltage integrator and seeking to improve

its performance leads to commonly used opamp topologies

Implementing a negative feedback frequency multiplier andseeking to improve its performance leads to type-I and II

phase locked loops

Valuable intuition gained before embarking on analysis

134 / 135

References

Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer,Analysis and Design of Analog Integrated

Circuits, 5th ed., Wiley 2009.

R. D. Middlebrook, Methods of design-oriented analysis: Low-entropy expressions,New Approaches to
http://find/

7/25/2019 20141018roorkee Cas Ws

135/135

, g y py p , pp

Undergraduate Education IV, Santa Barbara, 26-31 July 1992.

Nagendra Krishnapura, Introducing negative feedback with an integrator as the central element,Proc. 2012

IEEE ISCAS, May 2012.

Shanthi Pavan, EC201: Analog Circuits, Available:


Floyd M. Gardner,Phaselock Techniques, 3rd ed., Wiley-Interscience 2005.

Roland Best,Phase Locked Loops: Design, Simulation and Applications, 5th ed., McGraw-Hill 2007.

Stanley Goldman,Phase Locked Loop Engineering Handbook for Integrated Circuits, Artech House 2007.

Behzad Razavi,Design of Analog CMOS Integrated Circuits, 1st edition, McGraw-Hill, 2000.

Nagendra Krishnapura, EE5390: Analog Integrated Circuit Design, Available:


135 / 135
http://find/

Documents

20141018roorkee Cas Ws