2004 Initial Meeting 2005 R³B/EXL workshop

Synergy Group for Front-End Electronics and DAQ (SGFD)http://www.gsi.de/fair/experiments/NUSTAR/WGs/FEE-DAQ/http://www.gsi.de/fair/experiments/NUSTAR/WGs/FEE-DAQ/

2004 Initial Meeting

2005 R³B/EXL workshop

2006 NUSTAR/SPIRAL2 3 annual Meetings (GANIL, GSI, KVI…

2007 NUSTAR/SPIRAL2/Italy … Legnaro…

2007 NUSTAR/SPIRAL2/Spain … Huelva)

FP7 LoIsFP7 LoIs

SGFD scope for NUSTAR/FAIR experiments

i. Integration• FAIR Infrastructure • controls coupling• interconnects to other detection systems e.g. AGATA

ii. Standardisation, Flexibility • free coupling of different DAQ systems• interconnects for triggers and control signals • modularity of the system (local triggers / timestamps)• ‚look and feel‘ controls framework

iii. Standardisation, Synergies • Digitization & digital signal proccessing FPGA, DSP boards• Front End Electronics ASICS

Interface definitions .

Integration, Interoperability, andIntegration, Interoperability, and ModularityModularity

• data-transfer docking stations (station A)• slow-control docking stations (station B)

e.g. GridCC (AGATA, CMS, …)• time-synchronization docking (station C) station BuTiS@FAIR (100ps/km) + local TDS

System design for i & ii:

EXL & R³B DAQ / H.Simon

Data-transfer docking stations (station A)

Backends…

• data collection from detector systems (N M)• transfer and event building

– Interface to processor farm– Interface to online analysis– Interface to slow control systems– …

• storage

Under evaluation: Narval(Ganil/Agata)

DABC(„FAIR“ DAQ)


Slow-control docking stations (station B)H. Wörtche, H.S

1. checking setup (hardware, systems)2. system initialisation3. system parameter setting 4. monitoring (analog/digital) and safety

• C&C loops: C&C loops: Settings Settings Raw Data, preanalyzed data, analized data Raw Data, preanalyzed data, analized data• procedure: calibration, optimization, monitoring, stabilisationprocedure: calibration, optimization, monitoring, stabilisation• eg PID : identification figure-of-merit eg PID : identification figure-of-merit variation of parameters variation of parameters

tight integration, hierarchic in data treatmenttight integration, hierarchic in data treatment First implementations: digital signal processingFirst implementations: digital signal processing with f-o-m determination with f-o-m determination

(timing, n-gamma) @ KVI(timing, n-gamma) @ KVI


System design for iii:

Needed: Intermediate steps for R³B and EXL/R³B Demonstrators: timeline now !

„Available from the shelf“: e.g. AMS-02 readout: low power VA64_hdr.9a (Ideas)AMS-02 readout: low power VA64_hdr.9a (Ideas) 0.7 mW/ch, correct channel count …0.7 mW/ch, correct channel count … others: others: Ians talk

But: But: ¬ ¬ triggering and sparsification/readout speed !triggering and sparsification/readout speed !

Front End Electronics


R³B precursor: extended experimental Setup at Cave C

For 2007:

proton tracking behind magnet with drift chambers (100×80 cm2)resolution ~200 m

p 16 mm

For 2007: proton tracking around the target with Si-strip detectors


Vertex reconstruction for ions and protons

41 × 72 mm2 , strip pitch about 100m

Dynamic range – 100 keV - 14 MeV

Front of the SSD

FEEAMS(-02) readout:e.g. NIM A 439 (2000) 53

6+10 read out 2*5(320) + 6(384) VA_hdr.AMS64 resp. 9a chips IDEAS/Norway

SIDEREM NIM module


VA_S1320 ch

VA_S2320 ch

VA_K384 ch

HCC

HCC

S

K

J. Hofmann, W. Ott, N.Kurz (GSI)

12 Bit ADC ca. 80 s readout time (5MHz) DSP TMS320VC6414 (TI)FPGA Virtex-4 LX25 (Xilinx)

SIlicon Strip DEtector REadout Module (SIDEREM)


SIDEREM systemJ. Hofmann, W. Ott, N.Kurz (GSI)


Proton Driftchamber FEE

GTB BusPiggy back

PNPI St Peterburg

PNPI

Fermilab

ASDQ block diagramme


System integration via GTB piggy back

L. Uvarov, V. Golovtsov, V. Yatsura, A. Kandzadeev (PNPI)Ch. Wimmer, Ch. Müntz, J. Stroth (UNI Frankfurt) J. Hofmann, W. Ott, N.Kurz (GSI)

• Cable connections over distances up to 100m. • Screened 50 wires cable, 50 pin Mini-Ribbon connectors.• Single master, up to 15 slaves for GTB32 configuration.• Data rates up to 25 Mbytes/s.• Differential transfer, address and data are multiplexed.• 16 or 32 bit address and data width.• Access to slaves via Token or direct Addressing

GTB features:


SAM/GTB readout setupJ. Hofmann, W. Ott, N.Kurz (GSI)


What‘s missing ?

• Self trigger capability• Timestamps• Frontend Trigger Integration

e.g. programmable

event storage and trigger post processing

i.e. variable latency


One way out (… more to come …)

Christian J. Schmidt et al.

N-XYTERThe First Dedicated Neutron

Detector Readout ASIC

INFM - Perugia

Forschungszentrum Jülich

Hahn Meitner Institut - Berlin

Ruprecht Karls Universität - Heidelberg

AGH University of Sci. and Tech. - Krakow


N-XYTER: The DETNI Neutron Detector Readout ASIC

Architecture: 128 channel data driven charge sensitive front end

Front end for either polarity input signals:

Charge sensitive pre-amp

Fast analogue shaper as timing channel: init peak detector, timestamp

Slow analogue shaper as energy channel with peak detection

Readout: de-randomizing analogue energy and digital time stamp (2ns resolution) FIFO 2D-spatial information through X-Y-coincidence possible background suppression through spectroscopic window resolution enhancement through center of gravity determination de-randomizing robust and self sparsifiing readout strategy (token ring).

AMS 0.35 microns


Specifications for DETNI-ASIC as of 19.06.04

Property Spec agreed upon Gd/Si-MSD Gd/CsI-MSGC B-CASCADE GEM

channel pitch 50 µm 50 µm Arbitrary arbitrary

input capacitance Cin 30 pF 10....15 pF or

rather 25pF ?

23 pF X

40 (33)pF Y

10....30pF

Tp timing channel 30 ns

T energy channel T5% = 650 ns Def: Peak is above 5% no longer than T5%

Max ENC at Cin and

Tp for timing channel

optimize 550 e 2000 e 660 e

Dynamic range & gain two versions, low gain later

(8 – 120)*103 e

(2 –30)*105 e

(8 – 69)*103 e (2 - 30)*105 e (2 – 400)*103 e

no. of chan. per chip 128 128 64, 128 64, 128

timing resolution 4 ns (opt. res.) 8 ns 4 ns 10 ns

Max. % dead-time 10 % -> fifo depth: 10 10 % 10 % 10 %

average rate per chan. 160 kHz 160 kHz 960 kHz 160 kHz


Token Ring Schema as proposed by Ulrich Trunk 2003

U lrich TrunkP hys ika lisches Institu t der U n ive rs itä t H e ide lbe rg

T h res ho ldTo k e nM an a g e r

T im e s ta m p

R O C

R O C

Re

ad

out

Bu

s

R O C

R O C

Periodic readout at 20MHz

Token asynchronously passes from

channel to channel in search of data

Within one readout cycle token could

pass through all channels

If token encounters occupied

channels, data readout is initiated.

After readout the token passes to the

next channel.

20 MHz/128 Ch ≈ 160 kHz

10 Bit ADC (ENOB 10.4)


DETNIDETNI Collaboration CollaborationS.S. Alimova, A. Brognab, S. Buzzettib,c, W. Dabrowskid, T. Fiutowskid,

B. Gebauera, G. Kemmerlinge, M. Kleinb, C. Petrillof, F. Sacchettif, Ch.J. Schmidtg, K.H. Soltveitb, R. Szczygield,h, Ch. Schulza,

C. Thielmanne, U. Trunkb, P. Wiacekd, Th. Wilperta

aHahn-Meitner-Institut Berlin, Glienicker Str. 100, D-14109 Germany

bPhysikalisches Institut der Universität Heidelberg, Philosophenweg 12, D-69120 Heidelberg, Germany

cINFM & Dipartimento di Elettronica et Informazione, Politecnico di Milano, Piazza Leonardo da Vinci 32, Milano I-20133, Italy

dFaculty of Physics and Applied Computer Science, AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Krakow, Poland

eCentral Institute for Electronics, Research Centre Jülich, 52425 Jülich, Germany

fINFN & Dipartimento di Fisica, Universita di Perugia, Via A. Pascoli, Perugia I-06123, Italy

gGesellschaft für Schwerionenforschung, Planckstr. 1, 64291 Darmstadt, Germany

hInstitute of Nuclear Physics, Polish Academy of Sciences, ul. Radzikowskiego 152, 31-342 Krakow, Poland


Access via (Super)FRS projectBrano Sitar et al., Chiara Nociforo, H.S., Martin Winkler + Detector Lab. GSI

„Bratislava“ wire chambers (FP6 design study)

1. Deliverable includes single wire readout

2. Idea: Test N-XYTER 256 Ch. evaluation board

3. Interface via USB2 to PC

readout board Q3 /2007

chamber Q1or2/2008


No summary

FIN

NUSTAR@FAIR: DAQ/FEE and slow control

NUSTAR COUNCIL

NUSTAR DAQ

Haik Simon (coord.)Michael BöhmerMichael BlockChristophor KozhuharovNikolaus KurzIan LazarusJohan NybergLolly PollaccoHeinrich Wörtche…

EXLIan Lazarus

R³BHaik Simon

DESPECJohan Nyberg

…

Thomas NilssonNUSTAR Slow Control

Heinrich Wörtche

‚GSI‘ DAQNikolaus Kurz, Hans

Essel

Experiments

Related

…

Spiral2

Alpi


Time-synchronization docking (station C)

BuTiS: Bunchphase Timing System @ FAIR

• Standard frequencies: 100 kHz, 10 MHz, 76 MHz(PHELIX), 155,52MHz(OC-3, network std.),200 MHz

• Absolute time stamps (locally via GPS)

• Precision better 100 ps / km

Optical fiber system, receiver cost high: (few 10k€)

one receiver/ cave local time distribution system

Documents

2004 Initial Meeting 2005 R³B/EXL workshop