Interrupts

general concepts

interrupt systems

Interrupts - concepts 2/27

Interrupt - the event inside or outside of microprocessor system,

requested immediate service by software executed by

microprocessor.

Interrupts - concepts 3/27

Interrupt service routine - instruction sequence realising action

required by interrupt.

reading inputs

calculations

writing outputs

open valve

Interrupts - concepts 4/27

Main program (background program) - program executed by processor

during the absence of interrupts

ATTENTION: operation of interrupted program can’t be disturbed by

interrupt service

...

A:=200

B:=44

A:=A+B

M[201]:=A

...

in main program:

...B:=11A:=B*BM[101]:=A

...

in interrupt service routine:

M[201]=132 M[101]=121

...

A:=200

B:=44

A:=A+B

M[201]:=A

...

in main program :

A,Bstack...

B:=11A:=B*BM[101]:=A

...stackB,A

in interrupt service

routine :

M[201]=244 M[101]=121

B

A

D

G

O

O

D

Interrupts - concepts 5/27

Typical content (operation sequence) of interrupt service routine:

1. Storing working registers onto stack.

2. Precise recognition on interrupt cause.

3. Erasing interrupt.

4. Additional operations.

5. Restoring working registers from stack.

6. Interrupt system enable.

7. Return to interrupted program.

cont. main program32 4 5 6 71main program

INT

IE

Interrupts - concepts 6/27

Example of incorrect structure of interrupt service routine:

1. assumption:

interrupt system enabling (6) before erasing interrupt cause (3).

2 61main programme2 61 2 61 2 61 2 61 etc.

INT

IE

Interrupts - concepts 7/27

Examples of incorrect structure of interrupt service routine :

2. assumption: the absence of interrupt cause erasing (3):

2 4 5 6 71main program 2 4 5 6 71 2 4 5 6 71

INT

IE

permanent, execution of interrupt service routine

main program 2 4 5 6 71 2 4 5 6 71

INT

IE

2 4 5 6 71

else with execution of the single instruction from main program

Interrupts - concepts 8/27

Examples of incorrect structure of interrupt service routine :

INT

IE

cont. main program32 4 5 71main program

3. assumption: the absence of interrupt system enabling (6):

Interrupts - concepts 9/27

Examples of incorrect structure of interrupt service routine :

4. assumption: incorrect restoring of the working registers from the stack (not equal numbers of writings and readings):

execution of random codes32 4 5 76main programm

INT

IE

1

Return addressReg. AReg. BReg. C

stack:

PC

Return addressReg. AReg. BReg. C

stack:

PC

Interrupts - concepts 10/27

Interrupt system priority - urgency diversification of interrupts and

their service routines. Realising by assignment of different priorities to

interrupt sources.

It’s particular case of tasks priority.

Interrupts - concepts 11/27

Realising of interrupt system priority:

• by hardware:

- integrated controllers (MSI, LSI) ...

interrupt controller

CPU

I/O1 I/O2 I/On

ass. priorities: n>..>2>1

ass. priorities : 1>2>...>n

CPU

I/O1 I/O2 I/On

Vcc

Vcc

Interrupts - concepts 12/27

- or suitable connection structure (chain of interrupting devices);

Interrupts - concepts 13/27

Realising of interrupt system priority :

• by software - common beginning of interrupt service routines,

acting as software interrupt system arbiter

(recognise the sources of current active interrupts and decide about

sequence of service) ...

CPU

I/O1 I/O2 I/On

Vcc

Interrupts - concepts 14/27

... software interrupt system arbiter (SISA) with individual pooling

CPU

I/O1 I/O2 I/On

Vcc

cont. main program4 5 6 71 32SISAmain program

INTX

Interrupts - concepts 15/27

... software interrupt system arbiter (SISA) with grouped pooling

cont. main program4 5 6 71 32SISAmain program

INTX

CPU

I/O1 I/O2 I/On

Vcc

Interrupts - concepts 16/27

Multi-level interrupt system - current acting interrupt service routine can

be suspended by new interrupt, usually of higher priority.

Interrupts - concepts 17/27

Vectorised interrupts – each source of IRQ has separate service routine

executed directly after occuring the request.

Vectorisation can be achieved by:

• additional specialized hardware controllers, exmp. 8259A;

• some microprocessors and many microcontrollers, exmp. Z80.

No interrupt vectors = software arbitration.

Interrupts - concepts 18/27

Interrupts from different sources are asynchronous events

- they occur quite independently

CPU

I/O1 I/O2 I/O3

VccINT

instr. cycle #n+1instr. cycle #n

interrupt sequence (“saw by CPU”): 1 i 3 (“simultaneously”), 2

INT1

INT2

INT3

INT

instr. cycle #n-1

the moment of testing interrupt input by CPU

Interrupts systems 19/27

1. Single-level without priorities

Features:

• time delays (t1 , t2) of interrupt service routines;

• possibility of loss waiting for service interrupt;

• max. service delay can be sum of service times of other interrupts.

System used in little systems with 1..2 interrupt sources.

t1

2 1 2 3

t2

M P2 M P1 P2 P3 M

interruptsrequests

Interrupts systems 20/27

2. Single-level with priorities

Features:• more important interrupts will be served before others;

• possible time delay (t1 , t2) of services;

• low-priority interrupts can have long time delay;

• possibility of loss waiting for service low-priority interrupt.

System used with few number of interrupt sources.

t2

2 3 1,2

t1

M P2 M P3 P2 P1

seeming simultaneous occur of interrupts 1 & 2

interruptsrequests

priorities:

3>2>1

Interrupts systems 21/27

3. Multi-level without priorities

Features:• immediate start of interrupt service routine;

• each interrupt service can be suspended (even for long time) by other interrupts.

Rarely used system.

2 1 3 2 1

M P2 P1 M P3 P2 P1P2 P3 M

interruptsrequests

Interrupts systems 22/27

4. Multi-level with priorities

Features:• low-priority interrupts wait longer for service;

• more important interrupts are served faster.

System recommended with higher number of interrupt sources.

2 1 1 2 3

M P2 P1 M P1 P2 P3 P2 P1 M

interruptsrequests

priorities:

3>2>1

Interrupts - applications 23/27

Interrupt types - their applications

1. Clock interrupts - regular, constant frequency f > 1Hz:

• time interval measure (np. w ms);

• real time measure;

• in small microprocessor systems: service of basic I/O devices (keyboard, display, etc.).

Interrupts - applications 24/27

2. I/O devices interrupts - irregular,

usually inform about:

• I/O device readines for new data transfer;

• finish transmission.

Interrupts - applications 25/27

3. From system supervising circuits - unique, usually have high priority - inform about special system states:

• power failure;

• parity error in memory block;

• software working cycle failure - watchdog;

• error/exception processor/coprocessor.

Interrupts - applications 26/27

4. Interrupt from process devices - irregular:

inform about special events in controlled process:

• from alarm switch;

• overflow of allowed temperature, pressure, speed, etc.

Interrupts - applications 27/27

Task partitioning between main program and interrupt service routines

I II IIImain program

LOOP: JP LOOP(s.c. dead loop)

low priority tasks almost all tasks

interrupt service routinesall tasks (100%) high priority tasks functions restricted only

to data transfer, alarmstate services

featuresfull synchronisation withtime and events

needed data exchangesystem between twolayers of software

problems insynchronisation withtime flow