18/19 September 2002CodeSimulink: a HW/SW Codesign Environment1 A Codesign and Cosimulation Environment Based on MATLAB/Simulink Models Application to

18/19 September 2002

CodeSimulink: a HW/SW Codesign Environment

1

A Codesign and Cosimulation Environment Based on

MATLAB/Simulink Models

Application to the design of a Common Rail test bench

L.M. Reyneri, E. Bellei, E. Bussolino, L. Mari, F. Renga

September 2002

Politecnico di Torino



2

Part I

A Typical Design Framework



3

Common Rail Test bench



4

SW

PowerElectronics

UserInterface

Plant

User

HW

Mechanical Electrical

Environment

System Specifications



5




6

SW

PowerElectronics

UserInterface

Plant

User

HW


Environment

Electromechanical Designer

Design Partition - I



7

SW

PowerElectronics

UserInterface

Plant

User

HW


Environment

Electronics Designer

Design Partition - II



8

SW

PowerElectronics

UserInterface

Plant

User

HW


Environment

Control SWDesigner

User I/F Designer

Design Partition - III



9

SW

PowerElectronics

UserInterface

Plant

User

HW


EnvironmentPsychology

LawMarket

Design Partition - IV



10

SW

PowerElectronics

UserInterface

Plant

User

HW


Environment

Design Partition – Simulations (?)SPICE VHDL

SystemCVCC

AssemblerC/C++

VisualBASIC

AutocadFEM



11

SW

PowerElectronics

UserInterface

Plant

User

HW


Environment

Intermediate Result

V, A, W,Hz,

if thenelse gotolinux, ???

UNI, inches,degrees, ???

impactuser-friendlycolours, ???

Windows,mm, icon,click, ???



12

Someone will take decisions…



13

… and someone will payfor the mistakes



14

SW

PowerElectronics

UserInterface

Plant

User

HW


Environment

Final Result (perfect agreement…)

It’s YOURfault !!!

my part is fine


my part is fine


my part is fine


my part is fine


my part is fine



15

SW

PowerElectronics

UserInterface

Plant

User

HW


Environment

Conclusion (but it works…)

Patches



16

Part II

HW vs. SW vs. Analog

Integrated Design



17

HW/SW Design Styles and Languages

Programs C, Pascal, Ladder, MATLAB

compilers: flexible, powerful, user I/F, handle disks, peripherals

Electrical schematics

Anal: transistors Digit: gates

slow, requie know-how, easy to make design errors

HW descript. languages

Structural VHDL, Verilog

Like schematics but textual; they require high know-how

Behavioural VHDL, Verilog

High level description flexible, more accessible

Logic synghesis

Silicon compilers Short design t, optimization requires specific know-how

Simulators Simulink Easy, well known, requires limited know-how, does not generate HW

CodeSimulink idem, yet also generates HW !!!



18

Techniques and Platforms

Software uC, uP, DSP flexible, reusable, available, very short time-to-market, slow

PC, PLC idem, user-friendly, expensive

Digital ASIC little flexible, large quantities, long time-to-market, protectable

FPGA, discrete cheap, short time-to-market, protectable, little user-friendly, average flexibility

Analogic ASIC, discreti little flexible, small accuracy, sensitività to noise, necessary

Other tecn. Micromech. optical ecc.

Under development, not yet competitive

Hybrid systems

SW+HW (digit.+anal.)

powerful, cheap, limited power, high perfromance, flexible, complex to design



19

When do we need HW?

Complex or high speed functions (counters, timers, PWM)

To reduce complexity of SW (slower sample time, smaller CPU)

Repetitive and/or regular operations Reliability



20

Traditional HW/SW designSystem description/specs.

HW/SW partitioning

HW/SW interfaces

Detailed design HW SW

Simulation/verification

Does it work?

Enough performance

Compilation HW SW

ProgrammationASIC/FPGA DSP/PC

(System-on-chip)

Assembly and testing

Enough performance?

Production

High level languages

Requires experience

Critical

Very seldom

Very expensive loop

Automatic

Often yes, but…



21

Integrated HW/SW codesign

HW/SW partitioning

Fast performance estimation

Compilation HW SW


(System-on-chip)


Enough performance?

Production

Functional simulation

Enough performance?

Very quick loop


High level simulator

Automatic/driven/manual

Automatic

Often yes, but…

System description/specs.



22

Part III

CodeSimulink environment for HW/SW/mixed-mode codesign and

cosimulation



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Existing Codesign tools

VCC uses C++ for an object-oriented description

Polis, Esterel control-dominated systems (no control system!)

CoWare N2C Uses C

CodeSimulink data-dominated systems (e.g. control systems, visione, etc.)



24

Codesign under CodeSimulink

HW/SW partitioning


Compilation HW SW


(System-on-chip)


Enough performance?

Production


Enough performance?

Very quick loop




Automatic

Often yes, but…




25

System Description



26

Assigning Functional Parameters



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Simulations

• Functional verification

• Parameter tuning, ecc.



28


HW/SW partitioning


Compilation HW SW


(System-on-chip)


Enough performance?

Production


Enough performance?

Very quick loop




Automatic

Often yes, but…




29

Implementations Digital HW; different architectures:

– Synchronous parallel (base architecture)– bit-serial (smaller, slower)– systolic (faster)– interfaces among architecture

Analog HW; different architectures (under developm.):– Voltage/current single-ended/differential– Frequency/pulseWidth modulation

SW: different CPU’s External/Simulink: to simulate “external” world (plant,

actuators, sensors, environment, etc.)



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HW/SW partitioning (manual)



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Implementation parameters

DATAWIDTH (number of bits) BINARYPOINT (position of fixed point) REPRESENTATION ((un)signed, sign/modulus) OVERFLOW (saturation/wraparound) TRUNCATION (floor, ceil, round, etc.) PIPELINE (latency, speed)

+/- 1101 0

+3.50



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Different Data Types

Scalars (one data per sample) Vectors (a vector of data per sample; mux/demux):

– serial (data sequentially on a single channel)– parallel (data in parallel on different channels)

Matrices (a matrix of data per sample; for instance images in TV or vision):– serial– parallel/serial– serial/parallel



33

Serial and parallel vectors

2

Scalar data

1 2

21,3,5,7 2,6,10,14

serial vector

2

2

2

2

1 2

7 14

5 10

3 6

Parallel vector



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Assigning HW parameters



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Parameters are associated with signals

Parameters assigned with output ports !



36

Adding interfaces between architectures

Block to block: automatic (e.g. HW: synchronous data-flow protocol)

HW/SW: they depend on chosen platform (see further)

digital/analogue: they depend on A/D, D/A converters

HW/external, SW/external (encoder, PWM, A/D.D/A, etc.): they have appropriate parameters



37

Synchronous data-flow protocol

DATO

VAL

RDY

DATO

VAL

RDY

DATO

VAL

RDY

• If source has a valid data (VAL), and…

• if destinations are ready to receive it (RDY), …

• then data is transferred at next clock edge

• Guarantees correct timing!



38

Post-assigning simulations(bit-accurate)

6,-6

6,-2

6,0



39


HW/SW partitioning


Compilation HW SW


(System-on-chip)


Enough performance?

Production


Enough performance?

Very quick loop




Automatic

Often yes, but…




40

Quick Performance Estimation

Every cell has an (approximate) performance model which depends on:

technology (HW/SW/analogic) architecture (parallel, bit-serial, etc.) accuracy: --> num. bit (HW), power (anal.), etc. CodeSimulink “accumulates” performance Quick performance estimation, without time-

consuming compilation



41

Quick performance estimation



42

Quick performance estimation

DataWidth Energy Area LatencyPID_sim_derivative 12 2,00E+00 40 1PID_sim_gain 12 9,00E-01 17 1PID_sim_gain1 12 9,00E-01 17 1PID_sim_gain2 12 9,00E-01 17 1PID_sim_integrator 12 2,00E+00 33 1PID_sim_sum3 12 3,00E+00 51 1sim_extBrushless 12 3,00E+00 56 1sim_extEncoder1 12 2,00E+00 31 1sim_extSwWrite 12 1,00E+00 20 1sim_sum2 12 2,00E+00 34 1



43

Performances

Number of cells (FPGA) or area (ASIC) Power dissipation (battery duration...) Latency (computing delay) Max. clock Frequency (not yet…) Max sample frequency Code and data size (RAM size) Accuracy (S/N, bit number), from simulations



44


HW/SW partitioning


Compilation HW SW


(System-on-chip)


Enough performance?

Production


Enough performance?

Very quick loop




Automatic

Often yes, but…




45

CodeSimulink compilation

Separation of multiple platforms Hierarchy removal (flattening) Separation of SW, digital HW, analog HW blocks Adding interfaces Translation: CodeSimulink (SW) --> C (RTW) Translation: CodeSimulink (digital) --> VHDL Translation: CodeSimulink (analogic) --> EDIF



46

HW/SW Compilation

Possibility to edit VHDL/C/EDIF code Compilation: VHDL --> ASIC, FPGA (Altera,

Xilinx, others) (Leonardo - Mentor Graphics + proprietary tool)

Compilation: C --> executable (ANSI C compiler) Post-compilation performance evaluation



47

Every cell is made of...

Simulink symbol Fast functional model for simulations (template) Performance estimation model (SW, HW, …)

(template) VHDL, EDIF, C description (template) Parameter editing mask (template) Documentation (template)



48


HW/SW partitioning


Compilation HW SW


(System-on-chip)


Enough performance?

Production


Enough performance?

Very quick loop




Automatic

Often yes, but…




49

Platforms

SW-only (CPU, microprocessors, PC’s, etc.) HW-only (ALTERA, XILINX, ASIC, etc.) HW/SW:

– board (CPU+FPGA)– Systems-on-chip (ASIC: core+gates)– Programmable systems-on-chip



50

A few commercial platforms

SIDSA: HDST100 board (ARM7TDMI + Altera 10k100) SIDSA: HDST200 board (ARM7TDMI + Altera 10k100) SIDSA: FIPSOC chip (80C51 + FPGA) SUNDANCE: HDT355 board (TMS320C30 + Altera 10k100) SUNDANCE: HDT367 board (ARM + Xilinx Virtex) TRISCEND: chip (80C51 + FPGA) TRISCEND: chip (ARM7TDMI + FPGA) ALTERA: Excalibur chip (ARM7TDMI + FPGA)



51

CodeSimulink Libraries

Basic “Simulink” (+, *, integr. deriv. mux, demux, in, out, filters, f(x), 1/z, sources, scopes, etc., etc., etc.)

Toolboxes (image processing, neuro-fuzzy, flowchart)

Application-dependent (under request)



52


HW/SW partitioning


Compilation HW SW


(System-on-chip)


Enough performance?

Production


Enough performance?

Very quick loop




Automatic

Often yes, but…




53

Advantages (Code)Simulink

Flexibility Very high (shorter redesign time); no need to take care of interfaces and timing; quick performance modifications

Reusability existing Simulink schematics

Time-to-market Very short (consequently)

Accessibility Does not require experienced designer; simpler integration of work team with heterogeneous know-how’s



54

Applications

Control, image processing, neuro-fuzzy networks Design of consumer electronic circuits Design of high performance circuits Not suited to design microprocessors Speeding-up Simulink simulations, running on

HW (limited resolution)



55

Project Status (obsolete)

Compiler is complete Synchronous parallel library is complete Other libraries are under development New technologies/platforms to be characterized

(semi-automatic procedure) We are looking forward to cooperate (e.g. joint

development of applications)



56

Other Simulink-based tools

There are other commercial HW design tools based on Simulink:– DSP Builder from Altera– System Generator from Xilinx

These are mostly HW-only design tools (using Simulink as an HDL language)



57

Advantages of CodeSimulink

Handles both digital and SW and analog and RF and mixed-signal SoC’s

Automatically takes care of data exchange and timing (HW/HW, HW/SW, digital/analog)

Accurate high-level functional models of digital, analog, RF and mixed-signal interactions

High-level performance modeling (power, speed, area, code size, etc.)

Supports FPGA and ASIC and programmable SoC



58

Advantages of CodeSimulink

Natively handles scalars, vectors, matrices Supports multi-platforms, multi-cores (multi-SW,

multi-HW, hybrid) Supports Visual Basic / Windows GUI’s

(simulations and compilation) Supports bit-parallel, bit-serial, systolic data paths

and bundled-data asynchronous design (under developm.)

Interfaces to low-level simulators (ModelSim, MaxPlus, Quartus, Xilinx, Spice-like)



59

Limitations of (Code)Simulink

Data-dominated systems Mostly fixed time sampling strategy (multirate) Library-based (sub-optimal) Models require technology characterization



60

Commercialization of CodeSimulink

Free for universities for academic purposes Sundance ltd. is going to commercialize this

product at end of May 2003



61

Part IV

Application of CodeSimulink to the design of a Common Rail Test bench



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Part V

CodeSimulink HW/SW Codesign tool

Internal operation



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Index

HW/SW Compilation (L. Mari) Quick Performance Estimation (A. Serra) HW Performance Models (A. Cerrato) SW Performance Models (M. Lazarescu) Numeric optimization (G. Belforte) HW/SW Platforms (M. Chiaberge)

Documents

18/19 September 2002CodeSimulink: a HW/SW Codesign Environment1 A Codesign and Cosimulation Environment Based on MATLAB/Simulink Models Application to