I N V E N T R ATM

T H E I N T E L L I G E N T A P P R O A C H T O I N T E L L E C T U A L P R O P E R T Y

MICROCONTROLLER/PROCESSOR

M16X1 6 - B I T M I C R O C O N T R O L L E R

O V E R V I E W

The M16X is a 16-bit microcontroller which is software-

compatible with the Siemens C16x and STMicroelectronics

ST10 families of microcontrollers.

The M16X is designed for high instruction throughput

and rapid response to interrupts with minimal intervention

from the CPU. It features a four-stage pipeline, a

programmable external bus interface that can support

either 8-bit or 16-bit data buses, an interrupt controller with

support for 28 sources at 16 levels of interrupt priority, and

an 8-channel PEC.

It has a 16Mbyte linear address space for code and data,

and can be configured for a 1 or 2Kbyte internal RAM block

and for up to 128Kbytes of internal ROM. It can also be

configured to use a Bootstrap ROM after reset.

The M16X also has a powerful peripheral subsystem,

comprising two general-purpose timer units, a programmable

watchdog timer, a synchronous/ asynchronous serial port

with baud rate generator, and a high-speed synchronous port.

The two timer units together offer five 16-bit timers and a

capture/reload register.

K E Y F E A T U R E S

♦ High-performance 16-bit CPU

♦ Software-compatible with Siemens C16x/ STMicroelectronics ST10microcontrollers

♦ 16Mbyte linear address space

♦ Configurable internal RAM size

♦ Configurable internal ROM size

♦ Programmable external bus interface

♦ 28 source/16 priority level interruptcontroller

♦ 8-channel PEC

♦ Two timer units offering five timers

♦ Watchdog timer

♦ Synchronous/Asynchronous serial port

♦ High Speed Synchronous serial port

♦ Idle and Power-down modes

♦ Fully synthesizable

♦ Scan test ready

D E L I V E R A B L E S

♦ Verilog source code

♦ VHDL source code

♦ Synthesis script for Design Compiler

♦ Verilog & VHDL test benches

♦ Reference technology netlist

Corporate Headquarters General Information European Headquarters Pacific Rim Headquarters Japanese HeadquartersMentor Graphics Corporation Mentor Graphics Corporation Mentor Graphics Corporation Mentor Graphics Taiwan, Ltd. Mentor Graphics Japan Co., Ltd.8005 S.W. Boeckman Road P.O. Box 5050 Immeuble le Pasteur Rm. 1603, 16F, Gotenyama HillsWilsonville, OR 97070-7777 Wilsonville, OR 97070-5050 13/15, rue Jeanne Braconnier International Trade Building 7-35, Kita-Shinagawa 4-chomeU.S.A. U.S.A. 92360 Meudon La Foret 333, Sec.1, Keelung Road Shinagawa-Ku, Tokyo 140Phone: 503-685-7000 Phone: 800-547-3000 France Taipei, Taiwan, Republic of China JapanFax: 503-685-1202 Phone: 503-685-8000 Phone: 33-1-40-94-74-74 Phone: 886-2-27576020 Phone: 81-3-5488-3030

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All trademarks mentioned in this documentare trademarks of their respective owners.The Power to Create is a trademark ofMentor Graphics Corporation.

Copyright 1998-1999, Mentor Graphics Corporation.

04/99 PD-40089.005-FC The Power to Create

http://www.mentorg.com/inventra

B L O C KD I A G R A M

C O R E C P UThe M16X CPU comprises a four-stage instruction pipeline anda 16-bit ALU. It also incorporates a separate multiply/divide unit, abit-mask generator and a barrel shifter.

The core design is optimized for high instruction throughputwith most instructions, including shift and rotate instructions ofany size, being executed in one machine cycle. The exceptions aremultiply and divide instructions, and branch instructions where anew branch is taken. The use of a Jump Cache allows other branchinstructions to be executed in one cycle.

The CPU also includes a set of 16 word-wide general-purposeregisters. These are implemented as a number of register bankswithin the internal RAM block with a Context Pointer indicatingthe base address of the current register bank. The register banks areallowed to overlap for easy parameter passing. The number ofregister banks is limited only by the amount of internal RAM spaceavailable.

P E R I P H E R A L SThe M16X’s peripherals comprise two multi-function general-purpose timer units, a programmable watchdog timer, asynchronous/asynchronous serial port with baud rate generator,and a high-speed synchronous port.

The timer units together provide five 16-bit timer/countersand a capture/reload register. The timer/counters can operate inseveral different modes - Timer; Gated Timer; or Counter - andcan count either up or down, all quite independently of each other.Each timer unit includes a ‘core’ timer that can be used to latchoverflows/underflows, the output from which can be concatenatedwith the output from other timers in the same unit to provide 32- or33-bit timers for high resolution, long period timing.

I N T E R R U P T H A N D L I N GThe M16X’s interrupt controller offers support for interruptsfrom up to 28 sources within a 16-level priority system with added‘group’ priority to allow appropriate handling of events with similarpriorities.

The M16X offers a range of interrupt processing mechanisms:‘Normal’ interrupt processing; processing by an 8-channel PeripheralEvent Controller (PEC); Trap functions; plus some special handlingfor external interrupts. The PEC allows data transfers betweenperipherals and memory to be handled by inserting single data moveinstructions into the instruction pipeline rather than by calling aninterrupt service routine. This only halts CPU operation for oneinstruction cycle and doesn’t require the program status to be saved.

CLOCKS/WDT

PIPELINE

ADDRESSGENERATOR

RAMCONTROLLER

ROMCONTROLLER

EXTERNAL BUSCONTROLLER

TIMERS ASYNC/SYNCSERIAL PORT

HIGH-SPEEDSYNC SERIAL

PORT

INTERRUPTCONTROLLER

A L U

PORTCONTROLLER