SISTEMIEMBEDDED

SystemInterconnectFabricAvalon-ST:StreamingInterface

Videoout:PixelBufferDMAcomponent

FedericoBaronti Lastversion:20160503

AvalonStreamingInterface

• Lowlatency,highthroughput,unidirectionalpoint-to-point(fromasource toasinkinterface)datatransfer(stream)

• Supportforcomplexprotocols:– Packet transferswithpacketsinterleavedacrossmultiplechannels

– Sideband(fromsourcetosink)signallingofchannels,errors,startandendofpackets

Example:Avalon-MM andAvalon-ST

Someterminology• Symbol:Asymbolisthesmallestunitofdata.Formost

packetinterfaces,asymbolisabyte.Oneormoresymbolsmakeupthesingleunitofdatatransferredinacycleorabeat

• Beat:Asinglecycletransferbetweenasourceand asinkinterfaceconsistingofoneormoresymbols

• Channel:Achannelisaphysicalorlogicalpathorlinkthroughwhichinformationpassesbetweentwoports

• Packet:Apacketisanaggregationofdataandcontrol infothataretransmittedtogether– Apacketmaycontainaheadertohelproutersandother

networkdevicesdirectthepackettothecorrectdestination– Thepacketformatisdefinedbytheapplication,notbythe

Avalonspecification

Avalon-STInterfaceSignal Roles (1)

Avalon-STInterfaceSignal Roles (2)

• AlltransfersofanAvalon-STconnectionaresynchronouswiththerisingedgeoftheassociatedclocksignal

• Alloutputsfromasourceinterfacetoasinkinterface,includingthedata,channel,anderrorsignals,mustberegisteredontherisingedgeofclock

• Inputstoasinkinterfacedonothavetoberegistered• Registeringsignals onlyatthesourceprovidesforhighfrequency

operationwhileeliminatingback-to-backregisterswithnointerveninglogic

Avalon-STInterfaceProperties

ExampleofaSource-Sink connection

Datalayout• Example: datawidth=32bits;

dataBitsPerSymbol =8firstSymbolInHighOrderBits =true

Symbol031 24

Symbol123 16

Symbol215 8

Symbol37 0

DataTransferwithoutBackpressure• Whenthesourceinterfacewantstosenddata,itdrivesthedata andtheoptionalchannel anderrorsignalsandassertsvalid

• Thesinkinterfacesamplesthesesignalsontherisingedgeofthereferenceclockwhenvalid isasserted

SinkInterfacesamplingcycles

DataTransferwithBackpressure(1)• Thesinkindicatestothesourcethatitisreadyforanactivecyclebyassertingready

forasingleclockcycle.Cyclesduringwhichthesinkisreadyfordataarecalledreadycycles

• Duringareadycycle,thesourcemayassertvalidandprovidedatatothesink.Ifithasnodatatosend, itdeasserts validandcandrivedatatoanyvalue

• Eachinterfacethatsupports backpressuredefines thereadyLatency parametertoindicatethenumberofcyclesfromthetimethatready isasserteduntil validdatacanbedriven

• IfreadyLatency hasanonzerovalue,thesourceinterfacemustconsidercycletobeareadycycleifready isassertedoncycle

• WhenreadyLatency =0,dataistransferredonlywhenreadyandvalidareassertedonthesamecycle.Inthismodeofoperation, thesourcedoesnotreceivethesink’sreadysignalbefore itbegins sendingvaliddata.Thesourceprovides thedataandassertsvalidwhenever itcanandwaitsforthesinktocapturethedataandassertready.Thesourcecanchangethedataitisproviding atanytime.Thesinkonlycapturesinputdatafromthesourcewhenready andvalid arebothasserted

• WhenreadyLatency >=1,thesinkassertsready before thereadycycleitself.Thesourcecanrespond during theappropriatecyclebyassertingvalid.Itmaynotassertvalidduring acyclethatisnotareadycycle

DataTransferwithBackpressure(2)

• readyLatency =4

DataTransferwithBackpressure(3)• readyLatency =0

• readyLatency =1

PacketDataTransfer(1)

• Threeadditionalsignals:– startofpacket,endofpacket,empty

• Bothsourceandsinkinterfacesmustincludetheseadditionalsignals

• Noautomaticadaptation(bysysteminterconnectfabric)

PacketDataTransfer(2)• startofpacket isrequiredbyalltheinterfacessupportingpacket

transfersandmarkstheactivecyclecontainingthestartofthepacket.Thissignalisonlyinterpretedwhenvalid isasserted

• endofpacket isrequiredbyallinterfacessupportingpackettransferandmarkstheactivecyclecontainingtheendofthepacket.Thissignalisonlyinterpretedwhenvalid isasserted.

• empty isoptionalandindicatesthenumberofsymbolsthatareemptyduringthecyclesthatmarktheendofapacket.Thesinkonlychecksthevalueoftheemptyduringactivecyclesthathaveendofpacket asserted– Theempty symbolsarealwaysthelastsymbolsindata,thosecarried

bythelow-orderbitswhenfirstSymbolInHighOrderBits =true– Theemptysignalisrequiredonallpacketinterfaceswhosedatasignal

carriesmorethanonesymbolofdataandhaveavariablelengthpacketformat

– Thesizeoftheemptysignalinbitsisceiling(log2())

PacketDataTransfer(3)• Transferofa17-bytepacket

(readyLatency =0)• Datatransferoccursoncycles2,3,5,

6,and7,whenbothready andvalidareasserted

• Duringcycle1,startofpacket isasserted,andthefirst4bytesofpacketaretransferred

• Duringcycle6,endofpacket isasserted,andemptyhasavalueof3,indicatingthatthisistheendofthepacketandthat3ofthe4symbolsareempty

• D16istransmittedoverdata[31:24](firstSymbolInHighOrderBits =true)

Avalon-ST:Adapters• AdaptersareconfigurableQsys/SOPCBuildercomponentsthatarepartofthestreaminginterconnectfabric.Theyareusedtoconnectsourceandsinkinterfacesthat donotmatchexactly

• Qsys includesthefollowingfouradapters:– DataFormatAdapter– TimingAdapter– ChannelAdapter– ErrorAdapter

• IfyouconnectmismatchedAvalon-STsourcesandsinksinQsyswithoutinsertingadapters,Qsys generateserrormessages

ExampleofAvalon-STComponent• PixelBufferDMAController

– TheDMAcontrollerusesitsAvalon-MMmasterinterfacetoreadvideoframesfromanexternalmemory.Then,itsendsthevideoframesoutvia theAvalon-STinterface.Thecontroller’sAvalon-MMslaveinterfaceisusedto read/writethecontroller’sinternalregistersbytheprocessor

PixelBufferDMAController(1)• Avalon-MMSlaveinterface:

PixelBufferDMAController(1)• TheBuffer registerholdsthe32-bitaddressofthestartofthe

memorybuffer.Thisregisterisread-only,andshowstheaddressofthefirstpixeloftheframecurrentlybeing sentoutviatheAvalon-ST

• TheBackBuffer registerallowsthestartaddressoftheframetobechangedunderprogramcontrol– Tochangetheframebeingdisplayed,thedesiredframe’sstartaddress

isfirstwrittenintotheBackBuffer register– Then,asecondwriteoperationisperformedontheBuffer register.The

valueofthedataprovidedinthissecondwriteoperationisdiscarded.Instead,itinterpretsawritetotheBufferregisterasarequesttoswapthecontentsoftheBuffer andBackBuffer registers.

– Theswapdoesnotoccurimmediately. Instead,theswapisdoneafterthePixelBuffer reachesthelastpixelassociatedwiththecurrentframe.Inthemeantime,bitSoftheStatusregisterwillbesetto1.Afterthecurrentframeisfinished,theswapisperformedandbitSiscleared.

PixelBufferDMAController(1)module VGA_Pixel_Buffer(

//Inputsclk,reset,

slave_address,slave_byteenable,slave_read,slave_write,slave_writedata,

master_readdata,master_readdatavalid,master_waitrequest,

stream_ready,//....

//Bi-Directional

//Outputsslave_readdata,

master_address,master_arbiterlock,master_read,

stream_data,stream_startofpacket,stream_endofpacket,stream_empty,stream_valid

);

PixelBufferDMAController(2)

18

q[17..0]

q[17]

q[16]

q[15..0]

stream_endofpacket

stream_startofpacket

stream_data

stream_empty0

16

FIFO:Image_Buffer

FSM Avalon-MMSlaveIF

fifo_read

fifo_em

pty

stream_ready

stream_valid

fifo_almost_full

fifo_almost_em

pty18

d[17..0]Avalon-MMMasterIF

16

d[15..0]

FSMmanagesAvalon-MMMastertransferstokeepFIFOlevelbetweenalmost-fullandalmost-empty

d[16]

startofpacket

d[17]

endofpacket

VGA_Pixel_Buffer.v

References

• Altera,“AvalonInterfaceSpecifications,”mnl_avalon_spec.pdf– 5.AvalonStreamingInterfaces