1 Run-time flexibility in FPGAs (Opportunities and Challenges) Trial Lecture Mohamed Ezzat El-Hadedy Aly The Norwegian Center of Excellence for Quantifiable

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Run-time flexibility in FPGAs (Opportunities and Challenges)

Trial Lecture

Mohamed Ezzat El-Hadedy Aly

The Norwegian Center of Excellence for Quantifiable Quality of Service in Communication Systems (Q2S)

Norwegian University of Science and Technology (NTNU)

Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

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Outline of the talk (1/2) • Introduction

• Reconfigurable Computing

• Run-time (FPGA) Basics

• FPGA Reconfiguration Modes

• Run-time Reconfiguration Categories

• Run-time Reconfiguration Tools for Xilinx FPGAs

• Run-time Reconfiguration Applications

• Advantages of Run-time Reconfiguration

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Outline of the talk (2/2) • Partial Run-time Reconfiguration

Challenges

• Opportunities

• Ongoing research

• Conclusion

4

FPGA Chip


Introduction

Hardware reconfiguration is allowed during execution of an application

Design A

Design A

Design B

Design B

Design C

Design C

5

Introduction

Keccak Hash Function

Keccak Hash Function

Groestl Hash Function

Groestl Hash Function

Blake Hash Function

Blake Hash Function Skein Hash

FunctionSkein Hash

Function

SHA-256 Hash Function

SHA-256 Hash Function

JH Hash FunctionJH Hash Function

6 Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

Introduction

FPGA Definition• Field-Programmable Gate Arrays (FPGAs) are a recent kind

of programmable logic devices. They allow the implementation of integrated digital electronic circuits without requiring the complex optical, chemical and mechanical processes used in a conventional chip fabrication

• FPGAs can be embedded in traditional system design flows to perform prototyping and emulation tasks. In addition, they also enable novel applications such as configurable computers with hardware dynamically adaptable to a specific problem

• FPGA: Circuits that can be modified or configured by an end-user


Introduction

Block R

AM

s

Block R

AM

s

ConfigurableLogicBlocks

I/OBlocks

BlockRAMs

FPGA Structure


Basic CLB structure

Introduction

• Four slices are grouped by pairs, and each pair is organized in a column with independent carry chain

• Configurable switch matrix: There are connections between the horizontal and vertical routing resources to allow signals

to change their routing direction

The basic building block of a Configurable Logic Block


Basic LC structure

Introduction

Look Up Tables (LUT) are the kind of logic that is used in SRAM based FPGAs. Basically, each LUT is a collection of single bit memory cells storing individual bit values in each of the cells

LUT

10Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

Introduction

I/O Blocks

IOBs provide a bidirectional programmable interface between the output and the internal structure of the FPGA device

Routing possibilities for an I/O Blocks

• Input signal• Output signal• High impedance signal

Each signal has two storage elements that can be used as registers or latches

Block RAM

The BRAM is a configurable memory module that attaches to a variety of BRAM interface controllers [1]. The BRAM can be used to store big amounts of data

[1] Xilinx, "IP Processor Block RAM (BRAM)", DS444, Ver. 1.00a, March, 2011.


Fle

xibi

lity

Performance, cost, development time

Reconfigurable Computing


Reconfigurable Computing

Computation performed by executing instructions.CPU Computing

Computation using hardware that can be adapted at the logic level to solve specific problems.

Standard Definition :

• Some applications are poorly suited to microprocessors. • VLSI “explosion” provides increasing resources.

Why is reconfigurable computing interesting


FPGA Reconfiguration Modes

• Compile-time Reconfiguration• One configuration per application• System must be halted and then restarted with new program• Most common approach

Static Reconfiguration

Traditional FPGA architectures are primarily statically programmed devices, allowing only one configuration to be loaded at a time



• The physical hardware is smaller than the sum of required resources.

• With dynamic reconfiguration we can swap the number of configurations in and out of the actual hardware, as they are needed

Dynamic Reconfiguration

Whereas static reconfiguration allocates logic for the duration of an application, dynamic reconfiguration (often referred as run-time reconfiguration) uses a dynamic allocation scheme that re-allocates hardware at run time (i.e. during execution of the application)



• One configuration at a time• Context switching time in order of milliseconds

• Programming using a serial bit-stream• High overhead for small configuration changes• Not suitable for run-time reconfiguration

Single Context [2]

[2] Compton, C., Hauck, S. (2000). An Introduction to Reconfigurahle Computing. IEEE Computer (April 2000).

AESPCI

SHA-512

AESPCI

SHA-1

3DESPCI

SHA-1

context 1 context 2 context 3


• Multiple memory bits for each programming bit location• Context switching time in order of nanoseconds

• Multiplexed set of single context devices• One context can be reprogrammed when another is active

Multi-Context [2]


A multi-context device has multiple layers of programming bits, where each layer can be active at a different point in time



• Addresses are used to specify the target location of the configuration data

• Allows reconfiguration of only a part of a device while the rest of the device executes.

• Reduces the amount of data that must be transferred to the FPGA

Partial Reconfiguration [2]

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Module A

Module C

Module B

PR Architecture Example

FPGA

Bitstreams storage

Battery

External I/O

Module C

3. Smaller partial bitstreams

Module A request

1. System controller does not need to be placed in an external device

2. Access to fast Internal Configuration Access Port (ICAP – 32 bits, 100 MHz)

4. No need to halt complete system when reconfiguring a module

5. Time multiplexing of FPGA resources, load and unload HW modules on demand

Base system configuration

JTAG

Reconfigurable area

disabled

disabled

Con

trol

ler

(Mic

rob

laze

)

ICAP

Fla

sh c

ontr

olle

r

Module C

Module B

enabled

Module Aenableddisabled

Static area

Module A

Module B



• The device consists of independently configurable pipeline stages • Each stage is ready to execute immediately after

its programming• Used in data-path style computations

Pipeline Reconfiguration [3]

[3] H. Schmit, “Incremental Reconfiguration for Pipelined Applications,” Proceedings of the IEEE Symposium on FPGAs jiir Custom Comnputing Muchines (FCCM), p. 47-55, 1997


Configure 1Configure 1

Time

Sta

ges


Pipeline Reconfiguration (Data–path style)

Exec.1Exec.1


Exec.1Exec.1

Exec.2Exec.2



Exec.2Exec.2

Exec.3Exec.3

Exec. 4Exec. 4


Exec.3Exec.3

t1 t2 t3 t4 t5


Run-time Reconfiguration Categories

Algorithmic Reconfiguration [4]

• The goal is to reconfigure the system with a different computational algorithm that implements the same functionality, but with different performance, accuracy, power, or resource requirements

• Adapts dynamically to environmental or operational changes

BsA

1

sH

2Cs BsA

1

sH

Changing the control algorithm from being 2nd order to 3rd order.

[4] Neema S., et al, “Adaptive Computing and Runtime Reconfiguration,” Proceedings of the 1999 Military and Aerospace Applications of Programmable Devices and Technologies Conference, September 1999.

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Architectural Reconfiguration [4]

• The goal is to modify hardware topology by reallocating resources to computations

FPGA

DSP

DSP

FFT

PSR

X

Corr. Filters

Conv. Filters

ExtractROI

IFFT

PostProc.*

FPGA

DSP

DSP

FFT

PSR

X

Corr. Filters

Conv. Filters

ExtractROI

IFFT

PostProc.

*




Functional Reconfiguration[4]

• Reconfigure the programmable device with different configurations to execute different functions over time

• Eliminating redundant hardware

FPGA

DSP

DSP

Band-pass

Low-pass

Band-pass

FPGA

DSP

DSP

Band-pass

Low-pass

Limiter

Band-pass




Fast Configuration

• Reconfiguration time is non- productive time• Reconfigure the device as fast as possible in order to

minimize reconfiguration overhead

• Configuration prefetching• Configuration compression

• Relocation and Defragmentation • Configuration caching

Techniques for fast reconfiguration


Fast Configuration

• Loading a configuration onto a device in advance, in order to overlap reconfiguration with useful computation

Configuration Prefetching [5]

• Can be exploited if configuration can be done concurrently with computations

• Requires prediction which configuration will be needed in next couple of milliseconds• Gets complicated when multiple branches exist in

program

Configuration Prefetching issues [5]

[5] Pawel Chodowiec, «Run-time Reconfiguration state of the ar», George Mason University


Fast Configuration

Minimize the amount of data that must be loaded to the device in multi-context environment

Additional decompression circuits must be put on the FPGA die

Configuration Compression [5]

Reducing the amount of configuration data that must be transferred to the device•Use fast cache near reconfigurable hardware

Configuration Caching [5, 6]

[6] K. Compton and S. Hauck, “Reconfigurable Computing: a Survey of System and Software,” ACM Computing Surveys, pp. 171-210, vol. 34, no. 2, June 2002.


• Loading and uploading configurations fragments free space

• May reconfigure any part of the device• Configurations most likely occupy contiguous areas• Relocation needed if fragmentation of a free space

prevents loading new configurations

Relocation and Defragmentation [5]

Fast Configuration

c1 c3

c2

Newconfiguration

c4

c5c1

c3

c2

c4

c5Relocation /defragmentation


Run-time Reconfiguration Tools for Xilinx FPGAs

Xilinx ISE [7, 8]

• Partially configurable circuits can be implemented using Modular Designs• Special macros and constraints must be applied to

partially reconfigurable circuits• Xilinx recommends using modular designs with

simple circuits only

[7] Altera, White paper, «FPGA Run-Time Reconfiguration: Two Approaches», March 2008, ver 1.0.

[8] S. A. Guccione, D. Levi, and P. Sundararajan, “Jbits: A java-based interface to fpga hardware,” in Proceedings of the 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), 1999.


JBits [7]• JBits is a set of Java classes which provides an API to

access the Xilinx FPGA bitstream• A bitstream can be produced by Xilinx design tools or

read back from actual hardware• JBits API are low-level functions for direct manipulation

of all configuration details• JBits require good knowledge of the FPGA• May be used as a basis for other tools


• Where to get it?http://www.xilinx.com/labs/projects/jbits/ • A tutorial:http://www.hopsys.com/whitepaper.html http://www.klabs.org/richcontent/MAPLDCon99/.../

p27_sundararajan_s.ppt

More about Jbits?

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Tools Based on JBits

• JRTR [9]• Direct and simplified support for RTR designs

• XVPI [10]• Hardware/Software Interface

• BoardScope [11]• Chip debug tool

• VirtexDS (Device Simulator) [12]• Full simulation of runtime reconfigurable system

possible• Simulates the reconfiguration

• Jroute [13]• Automatic routing

[9] Scott McMillan and Steven A. Guccione. Partial run-time reconfiguration using JRTR. In Reiner W. Hartenstein and Herbert Gruenbacher, editors, Field-Programmable Logic and Applica- tions, pages 352{360. Springer-Verlag, Berlin, August 2000. Proceedings of the 10th Interna- tional Workshop on Field-Programmable Logic and Applications, FPL 2000. Lecture Notes in Computer Science 1896.



Design Tools

• PlanAhead• Xilinx floorplanning tool• Available on:

http://www.xilinx.com/tools/planahead.htm

• ReCoBus-Builder• Easy usable builder for Reconfigurable systems• Available on: www.recobus.de


[10] Sundararajan, P and S. A. Guccione, “XVPI: A Portable Hardware / Software Interface for Virtex,” Reconfigurable Technology: FPGAs for Computing and Applications II, Proc. SPIE 4212, pp. 90-95, Bellingham, WA, November 2000.

[11] D. Levi and S. A. Guccione, “BoardScope: A Debug Tool for Reconfigurable Systems,” In John Schewel, ed., Configurable Computing Technology and its Use in High Performance Computing, DSP, and Systems Engineering, Proc. SPIE Photonics East, Bellingham WA, pp. 239-346, 1998.

[12] S. P. McMillian, B. J. Blodget, and S. A. Guccione. VirtexDS: A device simulator for Virtex. In Reconfigurable Technology: FPGAs for Computing and Applications II, Proceedings of SPIE, volume 4212, pages 50–56, Bellingham, Washington, November 2000.

[13] E. Keller. JRoute: a run-time routing API for FFGA hardware. In Seventh Reconfigurable Architectures Workshop (RAW 2000), Cancun, Mexico, May 2000.


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Run-time reconfiguration applications

Applications for non-frequent reconfiguration [14]

• Rapid prototyping,• Searching (text, genetic database)• Mode changing (test equipment, radio)• Self-repair / self-optimizing

Applications for high-speed reconfiguration (area saving) [14]

• Networking (exchange packet filters according to traffic)• Modulation/frequency/encryption hopping in military

radios

Applications for high-speed reconfiguration (acceleration) [14]

• Crypto (e.g. asym. crypto for key exchange & symmetric for data)

[14] Dirk Koch: Partial Runtime Reconfiguration for Industrial Applications – Methods and Tools, Talk at the FPGA-forum in Trondheim (Norway) Feb. 2010.


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Run-time reconfiguration applications

Evolvable Hardware Systems

• Evolving Artifical Neural Networks• Evolvable Hardware Platforms• Partial reconfiguration would allow to test different

possible combinations• Fuzzy systems• Modular Robotics (Yet Another Modular Robot (YaMoR

unit)More details : http://lslwww.epfl.ch/~upegui/docs/DPR.pdf


Signal Processing/Image Processing Systems

• JPEG Encoder/Decoder systems• Edge detection applications


Advantages of Run-time Reconfiguration

Run-time Reconfiguration benefits [7]:

• Reduced power consumption• Hardware reuse (E.g reduced memory requirements)• Obsolescence avoidance• Flexibility• Reduced time to reconfigure• Application Portability


• In Partial Reconfiguration only the reconfigured partial run time (PRR) is stalled while static region and other PRRs continue operating • Smaller bitstreams sizes


Advantages of Run-time Reconfiguration

Obsolescence avoidance [7]

One of the most touted advantages of FPGAs in military designs is the ability to “future proof” applications through the careful application of hardware and software design, and the careful use of third-party application program interfaces (APIs) and design applications


Application Portability [7]

One of the goals of a run-time configurable system is to encapsulate the reconfigurable system into a portable application or avionics pod

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Xilinx PR Implementation FlowXilinx PR Implementation Flow

HDL Design DescriptionHDL Design Description

HDL SynthesisHDL Synthesis

Set Design ConstraintsSet Design Constraints

Placement Analysis Placement Analysis

Implement Static Design and PR Modules

Implement Static Design and PR Modules

MergeMerge

Final Bitsreams

Manual steps

Manual steps

PRR Challenges [15]

• Complicated design flow• Requires manual

intervention and knowledge about target

device• Can decrease the performance of the

system as compared to full configuration if system design is not carefully considered

Partial Run-time Reconfiguration (PRR) Challenges

[15] Shaon Yousuf, Ann Gordon-Ross, «RunTime FPGA Partial Reconfiguration for Image Processing Applications», University of Florida - PPT Presentation

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[16] Chris Conger, Ann Gordon-Ross, and Alan D. George , «Design Framework for Partial Run-Time FPGA Design Framework for Partial Run-Time FPGA ReconfigurationReconfiguration», University of Florida, ERSA, 2008.

Con

trol

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(Mic

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laze

)

ICAP

Fla

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ontr

olle

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Current PR Design Flow [16]

• Steps– Partition the system into modules– Define static modules and reconfigurable

modules – Decide the number of PR regions (PRRs)– Decide PRR sizes, shapes and locations – Map modules to PRRs– Define PRR interfaces, instantiate slice

macros for PRR interfaces

• Optimization problems– Design partitioning– Number of PRRs– PRR sizes, shapes and locations – Mapping PRMs to PRRs– Type and placement of PRR interfaces

Module AModule C

Module B

Static modules Reconfigurable Modules (PRMs)

12

FP

GA

# of PRRs

PRR 1

PRR 2

Sta

tic

regi

on

Static modules

Modules: A and B

Modules: C

Des

ign

part

itio

ning

Des

ign

floo

rpla

nnin

g an

d bu

dget

ing



PRR Challenges

• There is no robust documented design methodology to guide a user through the implementation of the reconfiguration

region [7].• Large bitsream

• Reconfiguration costs large amount of energy• Commercial tool support is limited

• Security issues • Virus scan of configured hardware is not easy because

Bit-files change on every synthesis process run Configured hardware has to be reread into a bit-file

Scanner has to simulate the hardware Reconfigurable hardware itself can be reconfigurable



Opportunities

• Provide High level algorithms to hardware• Improve the exist commerical tools to increase the efficiency

from differents aspects• Power consumption

• Area• Speed

• Reduce the configuration time

• Develop, implement and evaluate a novel compilation and synthesis system approach

• Develop a smart routing and placement tools to prevent bad configuration


Ongoing research

• Fine-grained Partial Runtime Reconfigurable on Virtex-5 FPGAs (In 18th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Charlotte, North Carolina, USA, May, 2010) Demonstrates systems based on Virtex-5 series FPGA

that provide full support for active partial run-time reconfiguration

The ReCoBus-Builder tool with a special adjusted communication architecture to improve the performance and efficiency, combined with an easy usable design flow


Ongoing research

• Advanced Partial Run-time Reconfiguration on Spartan-6 FPGAs (In Proceedings of the IEEE International Conference on Field-Programmable Technology

(ICFPT'10), Beijing, China, December, 2010) Demonstrates systems based on Spartan-6 series FPGA

that provide full support for active partial run-time reconfiguration

Provide new flow design that allows the migration of modules among different systems.

Context Switching Reconfigurable Hardware for Communication Systems (COSRECOS) Tool

http://www.mn.uio.no/ifi/english/research/projects/cosrecos/


• Routing Optimizations for Component-based Systems Design and Partial Run-time Reconfiguration on FPGAs (In Proceedings of the IEEE International Conference on

Field- Programmable Technology (ICFPT'10), Beijing, China, December, 2010.)

Proposed methods to significantly enhance the resource utilization (the strict bounding box constraints) of the FPGA routing fabric

Achieve area and reconfiguration time improvements of up 33% in a run-time reconfigurable system using Xilinx spartan-6 Technology

Ongoing research


• Run-time reconfigurable systems utilize reconfigurable hardware better

• Hardware and software based techniques can be applied to minimize reconfiguration overhead

• Penalty in reconfiguration time• Still, a considerable research effort is onging to improve the

tools to provide an ever increasing efficieny and ease of use • Open area for optimization exist for different aspects, such

as power consumption, hardware reuse, Flexibility, Reduced time to reconfigure, Application Portability and small bit-stream files

Conclusion

Conclusion

Documents

1 Run-time flexibility in FPGAs (Opportunities and Challenges) Trial Lecture Mohamed Ezzat El-Hadedy Aly The Norwegian Center of Excellence for Quantifiable