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EECS 465: Digital Systems
Lecture Notes # 7
(A) Introduction to Sequential Circuits(B) Latches and Flip-Flops
(C) Counter Design
SHANTANU DUTT
Department of Electrical and Computer EngineeringUniversity of Illinois, Chicago
Phone: (312) 355-1314: e-mail: [email protected]: http://www.eecs.uic.edu/~dutt
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(A) Introduction to Sequential Circuits
• Current o/p depends on the current i/p and past history of all i/ps seen by the circuit.
Where the relevant past history should be representable by a finitenumber of classes or states
No RedRed Light
State
Reset
Encode as state=0
Light = Red O/P = 0
Light = Green O/P = 1
Light = Not green O/P = 0
Light = Not red O/P = 0
Encode asstate = 1
State Transition Diagram
Design Problem: Output of the circuit is 1 only if it has seen a red light in the past and currently light is green.
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Circuit-Level Model of a Sequential Circuit.
CombinationalCircuit
MemoryUnit
Z0
Zm-1
Going toexternalworld
x0
xn-1
I/p fromexternalpoint
Statebits ofseq. ckt.
CurrentState
NextState
yk-1
y0
y’k-1
y’0
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Components to store bits ( latches or flip flops )
1)
1
1
0
1
Problem: can’t store new data
Cascade of inverter
0
I/P 1/0 O/PA
ALD
LD
LD
LD
Will conduct whenA=1, and open whenA=0
2)
(B) Latches and Flip-Flops
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Another storage element:
3) Cross coupled NOR gates ( R-S latch )
R=0
0
Q
1
S=10
Q
Q
RQ
S
Q
(Set)
(Reset)
NOR gates ( R-S latch )
Property of a NOR gate
A=0
B
B
BBA
When one I/P of NOR is 0, it acts like an inverter.When one I/P is 1, then O/P=0.Different I/P conditions for R-S latch:i) R=S=0, current I/P is stored indefinitely
( becomes cascade of inverters)Hold
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ii) R=1, S=0, when we want to store a 0 in the R-S latch. Q=0, 1Q
iii) R=0, S=1, when we want to store a 1 in the latch. Q=1, 0Q
iv) R=1, S=1; Forbidden inputs!
Both Q = 0, : Q and its complement have the same value ! Will play havoc in the rest of the logic circuit. Transit to: R=0, S=0.
R=1, S=1, both Q and and 0.Q
0 0 O/P oscillates.
Q
Q
R=10
S=10
0
1
01
01
0
Oscillatesbetween 1 and 0when we transit fromR=S=1 to R=S=0.
0Q
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Cross-coupled NORR
Q
S
Q
Cross-coupled NANDR
S
Q
Q
Hold State R=S=0 Hold State R=S=1
Q
QR=1, S=1
R=0, S=0
Forbidden I/Ps
From R, S = 1, 1 transit to R=0, S=1then Q, transit to 1, 0 ( correctly )
From R, S = 1, 1 transit to R=1, S=0then Q, correctly transit to 0, 1
Q
Q
Two implementations for R-S latch:
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4) The D-Latch
R-SLatch
DS
RR1
S1
Q
enbQ
Clocked Latch(level-sensitive clock latch)— see terminology defined later.
D=1, S=1, R=0 Q=1,D=0, S=0, R=1 Q=0,enb=0 R1,S1=0 (hold state)
0Q
1Q
enb=1
enb=1
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5) The J-K Latch:— Proposed to get rid of the forbidden I/P problem of R-S i) J=1, K=0: (a) Let Q=1, R=0,S=0
Hold state of R-S Q=1, 1Q 0Q
0Q0Q
ii) J=0, K=1 Q=0, using a similar analysisiii) J=K=0 Hold stateiv) J=K=1, suppose Q=1, =0 R=1, S=0 Q=0, =1 S=1, R=0 Q=1, =0 This type of toggling continues as long as J=K=1, and the latch is enabled ( CLK=1 below )
Q
(b) Let Q=0, , R=0, S=1 Q=1,
1Q
R
R-S
Q
QS
RQ
1
Q 01 01
10 10
CLK
K
J
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Latch classification with respect to response to “control signal”Terminology: Note that the terminology below applies to all types of latches:
R-S, D, J-K, T, etc., though the examples are given for the R-S latch.
i) Transparent Latch: O/P responds to latch I/Ps without any enable or clock signal.
R Q
S
Q
Clock:
Fixed frequency alternating 1 and 0 signal
ii) Clocked or Level-Sensitive Latch:
Q
Q
S
Clockorenb
R O/P responds to I/Ps only when enb or clock is at a pre-determined level (highor low — In this example, it is High)
R
S
Symbol:
R
S
CLK(high enable)
Symbol: or R
S
CLK (low enable)
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iii) Edge-Triggered Flip-Flop (FF) or simply Flip-FlopO/P will respond to I/Ps only at either: (a) the positive or rising edge of the enb/clock signal (positive edge-triggered FF), or
(b) the negative or falling edge of the enb/clock signal (negative edge-triggered FF).
Clock:
O/P responseperiod for apositive edge-triggeredFF.
O/P responseperiod for anegative edge-triggeredFF
O/P responseperiod for aHIGH-enable/clocklevel-sensitivelatch
O/P resp. period fora low-enable/clocklevel sensitive latch
Symbol:
RS
CLK
Symbol:
RS
CLK
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Setup Times and Hold Time of FFs and Latches • Assume, positive edge-triggered D-FF
THold relates to propagation delayof another part of circuit.
D
CLK
TSetup relates to propagation delays of various gates in the FF.The high point of
the CLK determines the positive edge’s arrival. • If negative edge-triggered
CLK
D
THoldTSetup
Negative edge arrival
• If D-Latch is high-level sensitive: Tsetup and Thold have to be around the negative edge of clock (more specifically, when the clock begins to go low), similar to negative edge-triggered.•If D-Latch is low-level sensitive: Tsetup and Thold have to be around the positive edge of clock, similar to positive edge-triggered.
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Solutions to Race Condition Problem with Level Sensitive Latches
Solution 1: Master-Slave FF:
Master-Slave J-K is a solution to race-condition problem: Any change in Q, during CLK=0 is not propagated to P, and hence back to Q, during thesame CLK=0. Any change to Q, will occur in next CLK=0 period.
J
K
Q
Q
(O/P responds when CLK goesFrom 1 to 0)
J-KM-S
Master-Slave J-K works similarto a J-K latch: E.g. LetJ=1, K=1, CLK=1Q=1, =0 =1 , P=0 When CLK=0Q=0, =1
Q
Q
Q
R-SLatch
CLK
K
J
QR
S
R-SQm
mQ R
S
sQ
Qs
1
0
1
0P
P1
0
1
0
Master R-S is level sensitive. Slave R-S is level sensitive.
Q
QP Q
Q
P
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Solution 2: Edge-Triggered FF:
Q
Q
R
S
D
Clk=1
D
D
0
0
Holds D whenclock goes low
Holds whenclock goes low
DQ =D
DQ
R
S
D
Clk=0
D
D
D
Assume D=1
D=1=SQ=1,
RD 0
0Q
CLK
Q
Q
R
S
D
Clk=0
D
D
0
0
Q responds to internal S signal; responds to internal R signal.Q
When CLK is 1 D I/P isinternally sampled butdoes not appear at the O/P.
O/P is held (changing D does notcause any change in internalsignals in the FF or in its output)
O/P appears (Q=D)
D
D
D
D
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Characteristic Equations of Latches/FFs
The next O/P Q+ defined in terms of the current O/P Q and the I/P.(FF/Latch is the simplest possible sequential ckt.)
1) R-S Latch— Truth Table:
S(t) R(t) Q(t) Q+ = Q( t+ ) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 x 1 1 1 x
Values at time t
Hold
Reset
Set
Forbidden
Q(t)\SR 00 01 11 10 0 0 0 x 1 1 1 0 x 1
Q+= S+ Q(Characteristic equation)
R
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Similarly: Characteristic Equations of
2) J-K, Q+ = Q + J.3) D-FF, Q+ = D4) Toggle FF/Latch Q+ = T + Q or T-FF / Latch
K Q
Q T
Whenever I/P T is high,the FF will toggle, i.e., Q+ = .When T=0, Q+=Q.
Q
Of course, these characteristic equations come into play onlywhen the FF/Latch is enabled.
Q
QT
Symbol:
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Excitation Table
— Reversed Truth Table— What the inputs to FFs should be for given output transitions (Q Q+)
Q Q+ R S J K T D0 0 x 0 0 x 0 00 1 0 1 1 x 1 11 0 1 0 x 1 1 01 1 0 x x 0 0 1
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— Conversion between FFsExample: J-K to D
D-FF
D
0 1
x x
0 1
0
1
Q
D
x x
1 0
DQ
D
O/P function = J J=D
Function = K K= D
Map the D,Q input combination to a QQ+ transitionand then map this to J-K excitation required.Thus, when D=1, Q=0, Q+=1 J,K = 1,x D=0, Q=0, Q+=0 J,K = 0,x D=1, Q=1, Q+=1 J,K = x,0
D=0, Q=1, Q+=0 J,K = x,1.
This should behave like a D-FF.
J
K
D
CLK
Logic
J
K
Q
QD
CLK
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Example 2: D J-K
Excitation Table for D
Q Q+ D0 0 00 1 11 0 01 1 1
J K Q Q+
0 0 0 00 0 1 10 1 0 0 0 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0
Q
Q
DJ
K
CLK
TT for J-K
JKQ
0
1
00 01 11 10
0 0 1 1
1 0 0 1
Function is
Q
Q
D
CLK
JK
Q
Q
J-K FF/LatchQKQJD
QJ
QK
Logic
should work like a J-K
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(C) Counter Design
• A counter is a special case of an FSM that cycles through its states on receiving triggering clock pluses.• It does not have any external data I/Ps.
A
B
C
D
EReset
000
001
010
011
100
FFs
LogicCounter O/P
Next Statebits
nn
CLK
• The states need to be encoded by binary bits.
No external I/Ps
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Synthesis (3-Bit Up Counter)
000 111
001 110
010 101
011 100
Reset
(a) State Transition Diagram
C B A C+ B+ A+ TC TB TA0 0 0 0 0 1 0 0 10 0 1 0 1 0 0 1 10 1 0 0 1 1 0 0 10 1 1 1 0 0 1 1 11 0 0 1 0 1 0 0 11 0 1 1 1 0 0 1 11 1 0 1 1 1 0 0 11 1 1 0 0 0 1 1 1
InputPresent State
OutputNext State
Toggle Flip-FlopInputs
(b) State Transition TableFF Excitation Table Revisited
Q Q+ R S J K T D0 0 x 0 0 x 0 00 1 0 1 1 x 1 11 0 1 0 x 1 1 01 1 0 x x 0 0 1
Excitation table for R-S, J-K, T, and D Flip-Flops
(What next statewill be given thecurrent state.)
State Transition Diagram and Table for a 3-bit Binary Up-Counter
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From excitation table for FF inputs, get K-map for the FF inputs.
1 1 1 11 1 1 1
00 01 11 10
01
CB
A
TA=1
0 0 0 00 1 1 0
00 01 11 10
01
A
CB
TC=AB
0 0 0 01 1 1 1
00 01 11 10
01
ACB
TB=A
K-maps for Up-Counter Using Toggle Flip-Flops.
Obtain logic expr. for FF I/Ps (as functions of current state bits A,B, C, --- A=QA, B=QB, C=QC) and realize the counter
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Counters with More Complex Sequencing (Non-Consecutive Binary Outputs)
000 110
010 101
011
State Transition Diagram
C B A C+ B+ A+
0 0 0 0 1 00 0 1 x x x0 1 0 0 1 10 1 1 1 0 11 0 0 x x x1 0 1 1 1 01 1 0 0 0 01 1 1 x x x
Present State Next State
State Transition TableImplementation Using J-K FFs:
C B A C+ B+ A+ JC KC JB KB JA KA0 0 0 0 1 0 0 x 1 x 0 x0 0 1 x x x x x x x x x0 1 0 0 1 1 0 x x 0 1 x 0 1 1 1 0 1 1 x x 1 x 01 0 0 x x x x x x x x x1 0 1 1 1 0 x 0 1 x x 11 1 0 0 0 0 x 1 x 1 0 x1 1 1 x x x x x x x x x
PresentState
NextState
Remapped NextState
State Transition Table and Remapped Next-State Functions
Q Q+ J K0 0 0 x0 1 1 x1 0 x 11 1 x 0
QKQJQ
J-K Flip-Flop Excitation Table
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Next State Functions
CBJ
J
AJ
A
B
C
1CK
CAK
AK
A
B
C
0 0 x xx 1 x x
00 01 11 1001
CBA
JC
x x 1 xx x x 0
CBA 00 01 11 10
01
KC
1 x x xx x x 1
CBA 00 01 11 10
0
1JB
x 0 1 xx 1 x x
CBA 00 01 11 10
0
1KB
0 1 0 xx x x x
00 01 11 1001
CBA
JAx x x xx 0 x 1
00 01 11 1001
CBA
KA
Remapped K-Maps for J-K Implementation.
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Actual Implementation ( Using J-K)
J QCLKK Q
J QCLKK Q
J QCLKK Q
+
Countsignal
AC
KB
B JA
C
A
JA
BKB
A
C
J-K Flip-Flop Implementation of 3 Bit Counter.
A C B A
C
