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ECE465 Lecture Notes # 11
Clocking Methodologies
Shantanu DuttUIC
Acknowledgement: (1) Most slides prepared by Huan Ren from Prof. Dutt’s Lecture Notes (some modifications made by Prof. Dutt). (2) Some slides extracted from Prof. David Pan’s (UT Austin) slides as indicated.
Me
mory
Timing Methodologies• Synchronous Sequential Circuits
Comb. Logic
Clk
External I/P External O/P
• Features Required for Correct Operation– 1) All State Transitions take place
only with respect to a particular event in the clock (e.g., positive or negative edge, etc. )
A
C11/0
B
11/0
00,11/0 01/1
00,01,10/0
01/0
10,00/1
Transition occurs only on positive edge of Clk
TOPP,Logic
TNSP,Logic
(critical path delayIn the o/p logic part)
(critical path delayIn the NS logic part)
Timing Methodologies (contd)• Features Required for Correct Operation
– 2) Only one state transition should take place in one clock period.– 3) All inputs to all FFs/latches should be correctly available with
appropriate setup time (Tsetup or Tsu) and hold time (Thold or Th) around the triggering edge of the clock.
i’th state transition
(i+1)’th state transition
(i+2)’th state transition
(i+3)’th state transition
Tperiod=TClk
[could be to the same state]
≥ Tsetup ≥ Thold
Input
Clock
Clock Routing• A path from the clock source to clock sinks (FFs)
• Different FFs are at different distances from the clock source
Clock Source
FF FF FF FF FFFF FF FFFF FF
From: David Pan, UT Austin
• This leads to the clock arriving at different FFs at slightly different time. This difference in clock arrival times is called clock skew
Timing Methodologies: Clock Skew Problem• Real-world problems that can cause the three requirements to be violated
– A) Clock Skew: Max(arrival time difference of the “same” clock edge betw all FF pairs).
01
D1 FF1D Q Logic
FF2D Q
IN
Q1
0 1
D2Q2
0
Clk Clk1 Clk2
00 10
Current state
Correct transition
11
Incorrect transition
New value of D2 overwrites old value before Q2 changes
This causes an incorrect Q2 change when +ve edge arrives at Clk2
Clk1
Clk2
D1
D2
Q1
Q2
Tskew
Safe: If blue horse wins race & wins it by a margin of at least Th
21
Unsafe: If brown horse wins race
2
1
Values before the clock +ve edge
Safe Value of Tskew
Clk1
Clk2
D1
D2
Q1
≥Tsu≥Th
Typical or min TPLH
min TP,Logic
Tskew ≥Th
01
D1 FF1D Q Logic
FF2D Q
IN
Q1
0
D2Q2
0
Clk Clk1 Clk2
Safe if: min (TPLH of FF)+min (TP,Logic between Q1 & Q2)>Tskew+Th
i.e. if: Tskew < min (TPLH)+min (TP,Logic)-Th
Similarly for 1 to 0 transition of Q1: TPHL comes into play, then safe if: Tskew < min (TPHL)+min (TP,Logic)-Th
• Thus we need: Tskew < min (min TPLH, min TPHL)+min (TNS
P,Logic) –Th
= min(TP,FF) + min(TNS P,Logic) – Th,
where TNSP,Logic is the prop. delay of the next state (NS)
logic portion of the entire comb. logic in the system.• Thus, the safe Tskew limit is based on minimum
propagation delay of FFs and the NS logic
•Tskew= max (|difference between clock pulses (rising edges) of clock inputs of any two FFs in the system|)
Another problem of clock skew
01
D1 FF1D Q Logic
FF2D Q
IN
Q1
0
D2Q2
0
Clk1 Clk2 ClkClk2
Clk1
Tskew
Less time avail. for logic and FF delays TFF + Tlogic + Tsu
• Clock skew causes another problem:1. If the clock is not designed taking skew into account, then there will not be enough
time to complete the FF-load and comb. logic operations Tsu time before the next clock edge arrives at Clk2
2. If clock skew is taken into account, as it should be, the clock period Tclk will be larger by an amount of Tskew, thus making it “unnecessarily” slower
Tclk
Determining Clock Period: Edge Triggered System
Comb. Logic
FF1
FF2
Clk
Clk1
Clk2
Clk
Level sens. latch
Positive edge trigg.
Clk
negative edge trigg.
Memory of FF bank with delay TP,FF
TOPP,Logic
Clk1
Clk2
TP,FF
TsuTP,Logic
Tskew
TClk
TClk-Tskew > max(TP,FF)+ max(TNSP,Logic)+Tsetup
= TP,FF+ TNSP,Logic+Tsetup
i.e., we will use the normal convention of using• TP,FF to mean max(TP,FF)• TNS
P,Logic to mean max(TNSP,Logic)
Also, TClk-Tskew > TP,FF+ TOPP,Logic, where TOP
P,Logic is the output logic portion of combinational logic.
Max(typical TPHLand typical TPLH)
TNSP,Logic
Determining the Clock Period (Contd.)
• If with skew– TClk> Tskew+ TP,FF+ TNS
P,Logic +Tsetup AND
– TClk> Tskew+ TP,FF+ TOPP,Logic
– Thus TClk> max(Tskew+ TP,FF+ TNSP,Logic +Tsetup, Tskew+ TP,FF+ TOP
P,Logic)
• Use 10% buffer for safety– TClk=1.1max(Tskew+ TP,FF+ TNS
P,Logic +Tsetup, Tskew+ TP,FF+ TOPP,Logic)
• Tskew= max (|difference between clock pulses (rising edges) of clock inputs of any two FFs in the system|)
Clk1
≥ TP,FF + TNSP,Logic + Tsetup, AND
≥ TP,FF + TOPP,Logic
TClk
Determining the Clock Period of a Datapath w/ a Controller FSM
FFsn
CLK
n
OutputLogic
m2
Next StateComb.Logic
m1
I/Ps (external + from datapath)
O/Ps (= Control Signals)
DatapathRegisters
Control logic(muxes, decoders, tri-state buffers, load/enablei/ps)
Delay1 =
TP
,FF
+ T
NS
P,L
og
ic +T
setup
Delay2 = TP,FF+ TopP,Logic +max(Tcontrol_logic)
FU(s)
FU(s)
FU(s)
Subpath delay =TP,FF+ TFU(s) + Tsetup
T1=max(Delay1, Delay2)A simple technique: Find the approximate greatest common divisor (gsd) of the various subpath delays.Update T1=max(Delay1, Delay2, above gsd)TClk = 1.1T1
Each subpath w/ delay Di will have cc delay of ceiling(Di/ TClk)
• Ignoring clock skew here for simplicity. Can be added later on after deciding the non-skew clock period by adding 1.1Tskew to it.
Another Problem in Seq. Circuits: Race Condition
• A race condition occurs when a FF/latch output changes more than once in a clock cycle (cc).
• This happens when after the O/P of a latch changes, it feeds back to its input via some logic when the latch is still enabled in the same cc. This cause the O/P to change again.
Clk
D
Q
≥Tsu
2 changes of state in Q in 1 cc
Clk
D latch
Comb. Logic
Other I/Ps
DQ
Race Condition (contd)• Race condition is generally a problem with level sensitive latches.• Can be solved using:
– a) Edge-triggered FFs.
Clk
D
Q
D FF
Comb. Logic
Other I/Ps
Clk
DQ
– b) Narrow-width clocking.
Only 1 O/P change per cc.
TClk
Tw
TClk > Tskew+ TP,FF+ TP,Logic+Tsetup
Tw < min (TP,FF)+min(TP,Logic)
min (min TPLH, min TPHL)
D latch
Comb. Logic
Other I/Ps
DQ
NarrowWidth Clk
Correct State Transition Using Level-Sensitive Latches: No race cond. but potential exists
00
100/00/1
011/1
011/11/0
1/00/0
Comb. Logic
0
1
0
1
0
1
Transition for the darkened arrow:
Clk
Comb. Logic
0
1
0
0
1
1
Clk
Comb. Logic
0
0
1
0
1
1
Clk
0/1
2 level sens. latches
CS NS
Race Condition due to unequal path delays for different NS bits: Incorrect State Transition Using Level-Sensitive Latches
Required transition for the thick arrow becomes incorrect transition corresponding to the dashed arrow
Comb. Logic
0
1
0
1
0
1
Clk
Comb. Logic
0
1
0
1
1
1
Clk
Comb. Logic
0
1
1
1
1
1
Clk
Comb. Logic
1
1
1
0
0
1
ClkComb. Logic
1
0
0
0
0
1
Clk2 level-sens. latches
fast
slow
1/0
00
100/00/1
011/1
111/1
1/0
0/00/1
No Race Condition Using Edge-Triggered FFs
00
100/00/1
011/1
011/1
1/01/0
0/0
• Correct transition for the darkened arrow irrespective of the relative speed of different excitation (next state) outputs
Comb. Logic
0
1
0
1
0
1
Clk
Comb. Logic
0
1
0
1
1
1
Clk
Comb. Logic
0
1
0
1
1
1
Clk
0/1
Comb. Logic
0
1
0
0
1
1
ClkComb. Logic
0
0
1
0
1
1
Clk2 M-S or edge-triggered FFs
fast
slow
Period Between State Transitions (also clock period)
No Race Condition Using 2-phase clocking and MS level sensitive latches
• Generally, Cost(master-slave (MS) LS latches) < Cost(edge-trigg. FF)
• Correct transition for the darkened arrow irrespective of the relative speed of different excitation (next state) outputs
00
100/00/1
01
011/1
1/01/0
0/0
Comb. Logic
0
1
0 0
1
1
Clk2 Clk1
Comb. Logic
0
0
1 1
0
1
Clk2 Clk1
Clk2
Clk1
Comb. Logic
0
1
0 1
1
1
Clk2 Clk1
fast
slow
Comb. Logic
0
0
0 1
1
1
Clk2 Clk1
fast
slow
T2-1Tgap
T1-2
0
1
OR
Two-phase clock period determination
Tgap1 > Tskew (to avoid overlap and thus a race condition & this also takes care of the skew problem that reduces that part of clock period available for the delays of the FF + logic + Tsu )T2-1+T1-2 (0< <1) + Tgap1 > TP,FF+TP,Logic+Tsu + Tskew (1)(Note: Introducing a Tgap1 of at least Tskew also takes care of the reqmt to allow for Tskew in the above sum of the 3 delay components)(1- )T1-2 > TP,FF + Tsu (2)The value of is really not going to matter, since disappears in T1-2 + (1- )T1-2 = T1-2, and on adding (1) and (2) we get: T2-1+T1-2 > 2TP,FF+TP,Logic+2Tsu (3)T1-2 = T2-1 (for symmetry requirements)Tgap1 = Tgap2 (for symmetry requirements) > Tskew
this again takes care also of skew reducing the clock period in the various prop. delays and setup times are incurred. So, finally:Tclk = 1.1(T2-1 + T1-2 + Tgap1 + Tgap2 ) = 1.1(2TP,FF+TP,Logic+2Tsu+2Tskew) [w/ 10% safety gap]
Comb. Logic
O/PsI/Ps
Clk2 Clk1
CS NS
Clk2
Clk1 T2-1Tgap1
T1-2
TClk
Tgap2
T1-2
T1-2
Note: Tgap1 = Tgap2 = Tskew, takes care of both requirements: a) no overlap in Clk1 and Clk2 due to skew; b) enough clock period Tclk to process all delays, where two different arrival times of clk1 (or clk2) at two different master (or slave) latches can differ by Tskew (the "usual" problem that we saw for edge-triggered FFs). No extra Tskew allowance needed in Tclk for the latter issue.
Clock Skew• Clock skew is the maximum difference in the arrival time of a
clock signal at two different components.• Clock skew forces designers to use a large time period between
clock pulses. This makes the system slower.• So, in addition to other objectives, clock skew should be
minimized during clock routing.
From: David Pan, UT Austin
Clock Design Problem• What are the main concerns for clock design?• Skew
– No. 1 concern for clock networks– For increased clock frequency, skew may
contribute over 10% of the system cycle time • Power
– very important, as clock is a major power consumer!
– It switches at every clock cycle!• Noise
– Clock is often a very strong aggressor– May need shielding
• Delay– Not really important– But slew rate is important (sharp transition)
From: David Pan, UT Austin
The Clock Routing Problem
• Given a source and n sinks (FFs).
• Connect all sinks to the source by an interconnect tree so as to minimize:– Clock Skew = maxi,j |ti - tj|
– Delay = maxi ti
– Total wirelength– Noise and coupling effect
From: David Pan, UT Austin
H-Tree Clock Routing
4 Points4 Points 16 Points16 Points
Tapping PointTapping Point
From: David Pan, UT Austin
Method of Means and Medians (MMM)
• Applicable when the clock terminals are arbitrarily arranged.
• Follows a strategy very similar to H-Tree.• Recursively partition the terminals into two sets of
equal size (median). Then, connect the center of mass of the whole circuit to the centers of mass of the two sub-circuits (mean).
• Clock skew is only minimized heuristically. The resulting tree may not have zero-skew.
From: David Pan, UT Austin
An Example of MMM
centers of masscenters of mass
From: David Pan, UT Austin