* Initialization (power-up, run)

    * Error reporting

    * Spy buffer implementation - depth, format, freezing, reading

Software items in Alberto talk

    * Version control and depository for firmware and online software * Monitoring

* Initialization (power-up, run) • INIT_event & Reset: INIT_event should empty everything

that is event-specific: the pipeline registers, reset FSMs, reset errors in EE Word, exit TMODE; Should not touch memories content, Input Fifos, VME Error registers, Spy buffers if they are in freeze mode….. Experience during running under test will adjust the INIT procedures. They should be two INIT procedures: Reset and INIT_event. Reset should be used to reset things that INIT_event do not touch (Input Fifos..). Both produced by VME/ATCA. IMPORTANT: provide both the Reset and INIT_ev signals to all FPGAs on your board.

• At power on or Reset: reset all pipeline registers, all FIFOs, all Spy Buffer pointers and overflow flags…..

• Test Mode: (a) memories, input Fifos and output registers available to VME/ATCA (b) FSMs are halted to ini state (c) exit with INIT

Errors

• Parity error – for each link between boards Parity (PA) should be calculated at the link starting point and checked at the end point (automatic in serial links?). Parity Error detection should be registered

• FIFO Overflow – each FIFO full flag should produce error if set.

• Internal Overflow (for example overflow in a HLM in a DO)• Invalid Input data (for example invalid HIT from ROD)• Lost Synchronism (event tags in different streams do not

match)• Truncated output • …….• What else?

Each classified error should have one bit reserved in the EE word and in a VME Error register (Read Only register, with clear from VME write)

TAGEE

TAGEE

TAGEE

TAGEE

IN

OUT

FIFO

IN

OUT

FIFO

Spy Buffers: what They are?

Pointer: incremented each time a word is popped from FIFO or sent to output. When it overflows it wraps around and an ‘overflow flag’ is set → circular memory

TWO MODES:SPY or FREEZE

To be read by VME

Copying dataduring run

Clustering in parallel –

224 Rols

48 DF

: cross-point for clusters -

Final Fit-HW

Board-boardConnector

4 DO

s

AMBoard

4 TFs

4 HW

s

DO

s

AM

4 TFs

4 HW

s

4 DO

s

AMBoard4 T

Fs

4 HW

s128 PUs = 512 pipelines Final Fit-H

W

32 boards

RO

SR

OS

FL

ICSlinks or cables

PU

Spy Buffers: where they are? @each designer boundary

Spy Buffers: when and how they are frozen?

TWO different cases:(a)One bit in the EE word received on input stream means ‘freeze immediately after you have finished to process the current event’. The event to be monitored will be chosen by DF that will set the EE bit into all FTK streams

(b) One severe error happened: Freeze is sent immediately to the previous board together with the event tag meaning ‘As soon as the event is processed, set the freeze’. The Freeze can be set in the outgoing EE word for the following boards (is it really necessary?).

Spy Buffers & FIFOs: how much deep? Format

• Deep: 8 streams → 8 + 8 Fifos + 8 spy buffers = 24 mem-blocks. In the chip we have 172 blocks of 1000 locations → ~6000 locations (6 <events>)

• Format: each function block has its optimized data format of input and output? Ex. AMBFTK has different words size for hits (15 bits) & roads (32 bits). Is it an exception? What about DO and TF? Time info should be stored at each clock? 32 bit for timing?

Processing Time measurements

Final Fit-HW

4 DO

s

AMBoard

4 TFs

4 HW

s

RO

S

DF

FLIC

L1 accept time

Each engine starts a counter at L1 accept time and when a word of the right event is written in the Spy buffer uses the right counter and writes the time. ?

ORThe first engine starts a counter from L1 Accept, than with the first word sent to the second engine it starts the counter of the second engine and sends to it its counts up to that moment to be added ?

Other kind of measurementsFirst event word extracted from FIFO starts a counter, last EE word stops the counter → event processing time inside the engine.

1. Standard VME registers/memories

1. Error register – WR = clear2. For each FIFO: flag register (empty, HFull, Full) - RO3. For each FSM: state machine - RO4. Output Status (Hold flags) – RO5. Output register (or output spy buffer): a VME wr will send data

on a link 6. For each Spy Buffer: Spy Buffer register: Pointer, OVFL flag,

status(freeze/spy. WR=clear of Pointer & flag. Status is RO 7. Severity error register: for each error bit 1 (or 2) bit is

dedicated to enable an ‘action’ in case of error. Will activate the stop-less removal and/or freeze signal.

8. Board ID or chip firmware ID? (ex PROM-ID) 9. Input FiFos: R/W 10. All associated memories R/W

Downloading of MC or real events in each board Input FIFOs downloaded by VME- random generationIn particular starting from the DF

Monitoring (which standard plots? Timing and #roads, #hits…?)

Version control and depository for firmware and online software

See Alberto Slices