Unit VI 80386DX Signals, Bus Cycles, 80387 Coprocessor–Signal Diagram –Description of signals...

Unit VI

80386DX Signals, Bus Cycles,

80387 Coprocessor

• 80386DX Signals

–Signal Diagram

–Description of signals

• 80386DX Bus Cycles

–System clock

–Bus states

–Pipelined and Non-pipelined bus cycles

BUS control signals

• ADS#: Address status

• READY#: Transfer acknowledge

• NA#: Next address request

• BS16#: Bus size 16

Address Pipelining

• Provides a choice of bus cycle timings.

• Pipelined or non-pipelined address timing is selectable on a cycle-by-cycle basis with the Next Address (NA#) input.

• When address pipelining is not selected, the current address and bus cycle definition remain stable throughout the bus cycle.

• When address pipelining is selected, the address (BE0# - BE3#, A2 - A31) and definition (W/R#, D/C# and M/IO#) of the next cycle are available before the end of the current cycle.

Read and Write Cycles

• Data transfers occur as a result of bus cycles, classified as read or write cycles.

• Two choices of address timing are dynamically selectable: non-pipelined, or pipelined.

• After a bus idle state, the processor always uses non-pipelined address timing.

• However, the NA# (Next Address) input may be asserted to select pipelined address timing for the next bus cycle.

• When pipelining is selected and the Intel386 DX has a bus request pending internally, the address and definition of the next cycle is made available even before the

current bus cycle is acknowledged by READY#.

• Terminating a read cycle or write cycle,

like any bus cycle, requires

acknowledging the cycle by asserting the

READY# input.

• Until acknowledged, the processor inserts

wait states

Non-pipelined read & write cycles (No wait

states)

• At the end of the second bus state within

the bus cycle, READY# is sampled

• If asserted the bus cycle terminates

• Else the cycle continues another bus state

(a wait state) and READY# is sampled

again at the end of that state.

• This continues indefinitely until the cycle

is acknowledged by READY# asserted

Non-pipelined read & write cycles (With wait states)

Pipelined Address

• Address pipelining is the option of requesting the

address and the bus cycle definition of the next, internally pending bus cycle before the current bus cycle is acknowledged with READY# asserted.

• Following any idle bus state (Ti), addresses are non-pipelined. Within non-pipelined bus cycles, NA# is only sampled during wait states.

• Therefore, to begin address pipelining during a group of non-pipelined bus cycles requires a non-pipelined cycle with at least one wait state

• Once a bus cycle is in progress and the current address has been valid for at least one entire bus state, the NA# input is sampled at the end of every phase one until the bus cycle is acknowledged

• If NA# is sampled asserted, the Intel386 DX is free to drive the address and bus cycle definition of the next bus cycle, and assert ADS#, as soon as it has a bus request internally pending. It may drive the next address as early as the next bus state, whether the current bus cycle is acknowledged at that time or not.

• 80387 NDP

–Features

–Control register bits for coprocessor support

–80387 register stack

–Data types

–Load and store instructions

–Trigonometric and transcendental instructions

– Interfacing signals of 80386DX with 80378

• High performance 80-Bit Internal Architecture

• Implements ANSI/IEEE standard 754-1985 for Binary floating-point arithmetic

• Expands Intel386DX CPU data types to include 32-, 64-, 80-bit floating point, 32-, 64-bit integers and 18-bit BCD operands

• Extends Intel386DX CPU instruction set to include Trigonometric, Logarithmic, Exponential and Arithmetic instructions for all data types

• Upward object code compatible

• Full-range transcendental operations for SINE, COSINE, TANGENT, ARCTANGENT and LOGARITHM

• Built-in Exception handling

• Operates independently in all modes of 80386

• Eight 80-bit Numeric registers

• Available in 68-pin PGA package

• One version supports 16MHz-33MHz

• Data registers: Eight 80-bit registers,

• Tag Word: the tag word marks the content of each numeric data register, two bits for each data register

• Status word: the 16-bit status word reflects the overall state of the MCP

• Instruction and Data pointers: two pointer registers allows identification of the failing numeric instruction which supply the address of failing numeric instruction and the address of its numeric memory operand.

• Control Word: several processing options are selected by loading a control word from memory into the control register

MCP Status Word

Seven data types are supported

Data transfer instructions

Operation Instructions

Addition FADD, FADDP, FIADD

Subtraction FSUB, FSUBP, FISUB, FSUBR, FSUBRP, FISUBR

Multiplication FMUL, FMULP, FIMUL

Division FDIV, FDIVP, FIDIV, FDIVR, FDIVRP, FIDIVR

Other operations

FSQRT, FSCALE, FPREM, FPREM1, FRNDINT, FXTRACT, FABS, FCHS

Comparison Instructions

Processor Control Instructions

Constant Instructions

Interfacing Signals of 80386DX with

80387

80386

Pin

80387

Pin

M/IO# NPS1#

A31 NPS2

A2 CMD0#

W/R# W/R#

ADS# ADS#

D31-D0 D31-D0

BUSY# BUSY#

ERROR# ERROR#

PEREQ PEREQ

THE END