Transistor Circuit DC Bias Part 1 ENGI 242. February 2003ENGI 2422 DC Biasing Circuits Fixed-Bias...

Transistor Circuit DC BiasPart 1

ENGI 242

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DC Biasing Circuits

• Fixed-Bias Circuit• Emitter-Stabilized Bias Circuit• Collector-Emitter Loop• Voltage Divider Bias Circuit• DC Bias with Voltage Feedback• Miscellaneous Bias Circuits

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Maximum Power Curve

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Fixed-Bias Circuit

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DC Equivalent circuit

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Base-Emitter (Input) Loop

Using Kirchoff’s voltage law: – VCC + IBRB + VBE = 0

Solving for IB: CC BE

B B

V - VI =

R

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Collector-Emitter (Output) Loop

Since: IC = IB

Using Kirchoff’s voltage law: VCE – VCC – IC RC

Because: VCE = VC - VE

Since VE = 0V, then: VC = VCE

Also: VBE = VB - VE

with VE = 0V, then: VB = VBE

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BJT Saturation RegionsWhen the transistor is operating in the Saturation Region, the transistor is conducting at maximum collector current (based on the resistances in the output circuit, not the spec sheet value) such that:

CC CE Csat

C

CEwhere

V - VI =

RV = 0 .2 V

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Determining Icsat

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Determining Icsat for the fixed-bias configuration

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Load Line Analysis

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Load Line Analysis

The end points of the line are : ICsat and VCEcutoffFor load line analysis, use VCE = 0 for ICSAT, and IC = 0 for VCEcutoff

ICsat:

VCEcutoff:

Where IB intersects with the load line we have the Q pointQ-point is the particular operating point: • Value of RB

• Sets the value of IB

• Where IB and Load Line intersect• Sets the values of VCE and IC.

CE

C

CC Csat V 0V

C

CE CC I 0mA

VI =

R

V = V

|

|

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Circuit values effect Q-point

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Circuit values effect Q-point (continued)

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Circuit values effect Q-point (continued)

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DC Fixed Bias Circuit Example

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Load-line analysis

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Fixed-bias load line

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Movement of Q-point with increasing levels of IB

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Effect of RC on the load line and Q-point

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Effect of VCC on the load line and Q-point

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Example

Emitter Stabilized Bias

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Emitter-Stabilized Bias Circuit

Adding a resistor to the emitter circuit (between the emitter lead and ground) stabilizes the bias circuit

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Improved Bias Stability

The addition of RE to the Emitter improves the stability of a transistorStability refers to a bias circuit in which the currents and voltages will remain fairly constant for a wide range of temperatures and transistor forward current gain ()The temperature surrounding the transistor circuit is not always constantTherefore, the transistor is not a constant value

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Base-Emitter Loop

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Equivalent Network

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Reflected Input impedance of RE

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Base-Emitter Loop

Applying Kirchoffs voltage law: - VCC + IB RB + VBE +IE RE = 0

Since: IE = ( + 1) IB

We can write: - VCC + IB RB + VBE + ( + 1) IB RE = 0

Grouping terms and solving for IB:

Or we could solve for IE with:

CC BEB

B E

V - VI =

R + (β+1)R

BCC E BE E E

R- V + I + V + I R = 0

( + 1)

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Collector-Emitter Loop

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Collector-Emitter Loop

Applying Kirchoff’s voltage law: - VCC + IC RC + VCE + IE RE = 0

Assuming that IE IC and solving for VCE: IC = VCC – VCE – (RE + RC)

Solve for VE: VE = IE RE

Solve for VC: VC = VCC - IC RC

or

VC = VCE + IE RE

Solve for VB: VB = VCC - IB RB or

VB = VBE + IE RE

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Transistor Saturation

CC CE CSAT

C E

V - VI =

R + R

At saturation, VCE is at a minimum

We will find the value VCEsat = 0.2V

For load line analysis, we use VCE = 0

To solve for ICSAT, use the output KVL equation:

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Load Line Analysis

The load line end points can be calculated:

At cutoff:

At saturation:

C CE CC I = 0 mAV V |

CE

CCC V = 0V

C E

VI =

R + R|

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Emitter Stabilized Bias Circuit Example

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Load Line For The Emitter-bias Configuration.