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6T-SRAM Layout VDD
GND
WL
BLBL
M1 M3
M4M2
M5 M6
3T-DRAM LayoutBL2 BL1 GND
RWL
WWL
M3
M2
M1
Read-Only Memory Cells
WL
BL
WL
BL
1WL
BL
WL
BL
WL
BL
0
VDD
WL
BL
GND
Diode ROM MOS ROM 1 MOS ROM 2
MOS OR ROM
WL [0]
V DD
BL [0]
WL [1]
WL [2]
WL [3]
V bias
BL [1]
Pull-down loads
BL [2] BL [3]
V DD
MOS NOR ROM
WL [0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
V DD
BL [1]
Pull-up devices
BL [2] BL [3]
GND
MOS NOR ROM Layout
Programmming using theActive Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (9.5l x 7l)
MOS NOR ROM Layout
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (11l x 7l)
Programmming usingthe Contact Layer Only
MOS NAND ROM
All word lines high by default with exception of selected row
WL [0]
WL [1]
WL [2]
WL [3]
V DD
Pull-up devices
BL [3]BL [2]BL [1]BL [0]
MOS NAND ROM Layout
No contact to VDD or GND necessary;
Loss in performance compared to NOR ROMdrastically reduced cell size
Polysilicon
Diffusion
Metal1 on Diffusion
Cell (8l x 7l)
Programmming usingthe Metal-1 Layer Only
NAND ROM LayoutCell (5l x 6l)
Polysilicon
Threshold-alteringimplant
Metal1 on Diffusion
Programmming usingImplants Only
CMOS NOR2 GATE LAYOUT
CMOS NAND2 GATE LAYOUT
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