Stick Diagrams and Tutorial

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Stick Diagrams

Stick Diagramsby

Rita Jain Professor and HeadDepartment of Electronics and Communication Engineering Lakshmi Narain College of Technology, Bhopalritajain_bpl@yahoo.com

1 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

LayoutThe Design Rules describe: Minimum width to avoid breaks in a line Minimum spacing to avoid shorts between lines Minimum overlap to ensure two layers completely overlap Unit Transistor Transistor dimensions are specified by their W/L ratio For 0.6 m process, W = 1.2 m and L = 0.6 m Such a minimum width contacted transistor is called UNIT TRANSISTOR

2 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Inverter LayoutTransistor dimensions specified as Width / Length Minimum size is 4 / 2, sometimes called 1 unit For 0.6 mm process, W=1.2 m, L=0.6 m

3 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

LayoutA conservative but easy to use Design Rules for nwell process is as follows: Metal and diffusion have minimum width spacing of 4 Contacts are 2 X 2 and must be surrounded by 1 on the layers above and below Polysilicon uses a width of 2 Polysilicon overlaps diffusion by 2 where a transistor is desired and has a spacing of 1 away where no transistor is desired Polysilicon and contacts have a spacing of 3 from other polysilicon or contacts N-well surrounds PMOS transistors by 6 and avoids NMOS transistors by 64 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Simplified Design RulesConservative rules to get you started

5 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick DiagramsStick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers

6 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick DiagramsVLSI design aims to translate circuit concepts onto silicon. stick diagrams are a means of capturing topography and layer information using simple diagrams. Stick diagrams convey layer information through colour codes (or monochrome encoding). Acts as an interface between symbolic circuit and the actual layout.7 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick DiagramsDoes show all components/vias. It shows relative placement of components. Goes one step closer to the layout Helps plan the layout and routing

Does not show Exact placement of components Transistor sizes Wire lengths, wire widths, tub boundaries. Any other low level details such as parasitics.

8 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Wiring TracksA wiring track is the space required for a wire 4 width, 4 spacing from neighbor = 8 pitch

Transistors also consume one wiring track

9 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Well SpacingWells must surround transistors by 6 Implies 12 between opposite transistor flavors Leaves room for one wire track

10 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Area EstimationEstimate area by counting wiring tracks Multiply by 8 to express in

11 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Example: Inverter

12 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Example: NAND3Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 l by 40 l

13 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick Diagrams Some rulesRule 1. When two or more sticks of the same type cross or touch each other that represents electrical contact.

14 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick Diagrams Some rulesRule 2. When two or more sticks of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connectionexplicitly).

15 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick Diagrams Some rulesRule 3. When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

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Stick Diagrams

Stick Diagrams Some rulesRule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side.

17 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick Diagrams

N+

N+

18 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick DiagramsVDD X X X VDD

x

x

Stick Diagram

x

x

X Gnd

Gnd19

Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick DiagramsVDD X X X

VDD

x

x

x

x

X Gnd

Gnd20

Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick Diagrams NotationsMetal 1 poly ndiff pdiffCan also draw in shades of gray/line style.

Similarly for contacts, via, tub etc..21 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

How to draw Stick Diagrams

22 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

NOR Gate

23 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stacked LayoutPower

A

Out

C BGround

24 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Methods for generating Stick DiagramsConstruct a Logic Graph of the Schematics Identify each transistor by a unique name of its gate signal (A, B, C, D ..) Identify each connection to the transistor by a unique name (1,2,3,4,5,..) Construct an Euler Path for both pull-up and pull-down network Euler Path is defined by a path that traverses each node in the path, such that each edge is visited only once Path is defined by the order of each transistor name Euler Path for the pull-up network must be same as the path of pulldown network Euler paths are not necessarily unique It may be necessary to redefined the function to find a Euler path

25 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Methods for generating Stick DiagramsOnce the Euler path is found it is time to layout the stick diagram Trace two lines horizontally to represent PMOS and NMOS Trace the number of Inputs vertically across each strip. These represent the gate contacts to the devices that are made of poly Surround NMOS and PMOS by P-well and N-well Trace a blue line horizontally above and below the PMOS and NMOS lines to represent the metal of VDD and VSS Label each poly line with the Euler path label, in order from left to right Place the connection label upon NMOS and PMOS devices26 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick DiagramsSketch a stick diagram for O3AI and estimate area Y = ((A+B+C).D)

27 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick DiagramsVDDVDD

A B C Y D B

A Y D D

D

C Y

A

B CVSS

A

B

CVSS

Pull-up Network

Pull-down Network

28 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Stick Diagrams

29 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Area Estimation

30 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

OAI21 Logic GraphA j B X = !(C (A + B)) C A i i B B X A C X C

B j A C

GND A B C PDN

VDD PUN

31 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal

Stick Diagrams

Home Work1. Draw the stick diagram for two input CMOS NAND gate. 2. Draw the stick diagram for two input NAND gate using NMOS Logic. 3. Draw the stick diagram for 2:1 MUX using a) Pass transistors b) Transmission gates. 4. Draw Stick Diagrams for the following equations Y = ( A + B + C ).D : Y = A + ( B + C ).D5. 6. For a process technology with L = 5 micron meter give the size of the layout for the following : (a) 4-input NOR gate and 4-Input NAND gate Draw Stick Diagra