SPP V1 Memory Map

John DeHartApplied Research Laboratory

Computer Science and Engineering Department

SPP V1 Memory Map

2 - David M. Zar – 04/21/23

Revision History

9/11/2007 (JDD):»Created

3 - David M. Zar – 04/21/23

Counters Two sets of counters maintained for each successful lookup:

» Pre-Queue: Pkt counter and Byte counter» Post-Queue: Pkt counter and Byte counter

Each counter is 32-bits Organization of Counters:

» Addr of a pre-q pckt ctr: BASE+(4 * 4 * Index) + (0*4)» Addr of a pre-q byte ctr: BASE+(4 * 4 * Index) + (1*4)» Addr of a post-q pckt ctr: BASE+(4 * 4 * Index) + (2*4)» Addr of a post-q byte ctr: BASE+(4 * 4 * Index) + (3*4)

Pre-Queue Pkt CtrPre-Queue Byte CtrPost-Queue Pkt CtrPost-Queue Byte CtrPre-Queue Pkt CtrPre-Queue Byte CtrPost-Queue Pkt CtrPost-Queue Byte Ctr

Pre-Queue Pkt CtrPre-Queue Byte CtrPost-Queue Pkt CtrPost-Queue Byte Ctr

. . .

BASECounter Index 0

Counter Index 1

Counter Index N

4 - David M. Zar – 04/21/23

LC Ingress SRAM Channel 3

Unallocated

Unallocated

Unallocated

Unallocated

Unallocated

0x000000

0x100000

0x200000

0x300000

0x400000

0x500000

0x600000

0x700000

MI Counters

0x7FFE9FTx Pkt Counters

(turned off for Perf.) 0x7FFF3F

0x7FFEA0

Unallocated 0x7FFFFF0x7FFF40

0x1800000x17FFFF

HF Init

0x100000

0x1801ff0x180200Counter Error Cnts 0x180220

Rx Pkt Counters(turned off for Perf.)

0x7FFE00

Unallocated 0x7000000x7FFDFF

Unallocated 0x1802210x1FFFFF

PreQ/PostQ Cntrs

5 - David M. Zar – 04/21/23

LC Ingress SRAM Channel 2

Buffer Descriptors(0x38000 * 32B)(229376 * 32B)

(7MB)

0x000000

0x700000

0x740000

QM1 Queue Desc Array(16384 * 16B = 256KB)

QM1 Queue Desc Array(16384 * 16B = 256KB)

QM2 Queue Desc Array(16384 * 16B = 256KB)

QM3 Queue Desc Array(16384 * 16B = 256KB)

0x780000

0x7C0000

QM1 Sched0 QDs(2048 * 16B)

0x700000

0x708000 QM1 Sched1 QDs(2048 * 16B)

QM1 Sched2 QDs(2048 * 16B)

QM1 Sched3 QDs(2048 * 16B)

QM0 Sched4 QDs(2048 * 16B)

Unused QDs(2048 * 16B)

Unused QDs(2048 * 16B)

Unused QDs(2048 * 16B)

0x740000

0x710000

0x718000

0x720000

0x728000

0x730000

0x738000

6 - David M. Zar – 04/21/23

LC Ingress SRAM Channel 1

QM QParams(No longer pre-assigned

to a QM)(32768 * 16B)

0x000000

0x040000

0x080000

0x0C0000

QM0 Sched(3278 * 44B= 0x23368)

0x0A3368

0x080000

0x0C66D0

QM1 Sched(3278 * 44B= 0x23368)

QM2 Sched(3278 * 44B= 0x23368)

QM3 Sched(3278 * 44B= 0x23368)

0x0E9A38

0x10CDA0 QM0 Freelist(3278 * 4B= 0x3338)

QM1 Freelist(3278 * 4B= 0x3338)

QM2 Freelist(3278 * 4B= 0x3338)

QM3 Freelist(3278 * 4B= 0x3338)

0x1100D8

0x113410

0x116748 Unallocated

0x119A80

0x7FFFFF

QSCHED Params(Rate and Intfc) (128B)

0x119B000x119AFF

7 - David M. Zar – 04/21/23

LC Egress SRAM Channel 3

Flow StatsHash Table

(4MB)

Unallocated

0x000000

0x100000

0x200000

0x300000

0x400000

0x500000

0x600000

0x700000

MI Counters

0x7FFE9FTx Pkt Counters

(turned off for Perf.) 0x7FFF3F

0x7FFEA0

Unallocated 0x7FFFFF0x7FFF40

0x1800000x17FFFF

HF Init

0x100000

0x1801FF0x180200Counter Error Cnts 0x18021F

Rx Pkt Counters(turned off for Perf.)

0x7FFE00

FS Freelist SRAM Ring

0x700000

0x77FFFF

Unallocated 0x1802200x1FFFFF

FS to XScale SRAM Ring 0x73FFFF0x740000

Unallocated 0x780000

PreQ/PostQ Cntrs

8 - David M. Zar – 04/21/23

LC Egress SRAM Channel 2

Buffer Descriptors(0x38000 * 32B)(229376 * 32B)

(7MB)

0x000000

0x100000

0x200000

0x300000

0x400000

0x500000

0x600000

0x700000 Queue Desc Array(65536 * 16B = 1MB)

9 - David M. Zar – 04/21/23

LC Egress SRAM Channel 1

QM QParams(No longer pre-assigned

to a QM)(32768 * 16B)

0x000000

0x040000

0x080000

0x0C0000

QM0 Sched(3278 * 44B= 0x23368)

0x0A3368

0x080000

0x0C66D0

QM1 Sched(3278 * 44B= 0x23368)

QM2 Sched(3278 * 44B= 0x23368)

QM3 Sched(3278 * 44B= 0x23368)

0x0E9A38

0x10CDA0 QM0 Freelist(3278 * 4B= 0x3338)

QM1 Freelist(3278 * 4B= 0x3338)

QM2 Freelist(3278 * 4B= 0x3338)

QM3 Freelist(3278 * 4B= 0x3338)

0x1100D8

0x113410

0x116748 Unallocated

0x119A80

0x7FFFFF

QSCHED Params(Rate and Intfc) (128B)

0x119B000x119AFF

10 - David M. Zar – 04/21/23

Egress Scratch Memory (16 KB)0x0000

0x0400

0x0800

0x0C00

TO_XSCALE_RING (Ring 1)FROM_XSCALE_RING (Ring 2)

COUNTER_RING (Ring 3)

0x1000

0x1400

0x1800

0x1C00

0x2000

0x2400

0x2800

0x2C00

0x3000

0x3400

0x3800

0x3C00

PS_TO_QM_RING_1 (Ring 4)PS_TO_QM_RING_2 (Ring 5)QM_TO_FS_RING_1 (Ring 6)QM_TO_FS_RING_2 (Ring 7)FS1_TO_FS1_RING (Ring 8)FS_TO_TX_RING_1 (Ring 9)FS_TO_TX_RING_2 (Ring 10)

PACKET_TX_AVAIL_TBUF_ELE_SCR_ADDR (4B)

SRAM RING OCCUPANCY COUNTERS

0x0000

0x0100

0x0200

0x0300

11 - David M. Zar – 04/21/23

NPE/MR SRAM Channel 3

PreQ and PostQ Ctrs

Unallocated

Unallocated

Unallocated

Unallocated

Unallocated

Unallocated

0x000000

0x100000

0x200000

0x300000

0x400000

0x500000

0x600000

0x700000

HF Init (40B)

0x000000

Tx Pkt Counters (2560B)(turned off for Perf.)

0x0000300x00002F

Unallocated

SD Init (8B)0x0000080x000007

0x000FFF0x001000Rx Pkt Counters (2560B)

(turned off for Perf.)

Unallocated

0x00127F0x0012800x0014FF0x001500

0x0FFFFF

SD Counters (24B) 0x0015170x001518

SD VLAN Code Opt Tbl(0x1000 Entries x 24B)

Error Ctrs (32B) 0x001537Slice Specific Mem 0x001538

0x011537

IPv4/I3 specific data(0x1000B)

0x011538

0x0125370x012538

SE Src IP Tbl (128B)SE Init (16B) 0x00003F

0x0000400x0000BF0x0000C0

0x218000SE Per Slice Control Tbl(0x1000 Entries x 20B)

0x314000

12 - David M. Zar – 04/21/23

NPE/MR SRAM Channel 2

Buffer Descriptors(0x38000 * 32B)(229376 * 32B)

(7MB)

0x000000

0x100000

0x200000

0x300000

0x400000

0x500000

0x600000

0x700000 Queue Desc Array(65536 * 16B = 1MB)

13 - David M. Zar – 04/21/23

NPE/MR SRAM Channel 1

QM QParams(No longer pre-assigned

to a QM)(32768 * 16B)

0x000000

0x040000

0x080000

0x0C0000

QM0 Sched(3278 * 44B= 0x23368)

0x0A3368

0x080000

0x0C66D0

QM1 Sched(3278 * 44B= 0x23368)

QM2 Sched(3278 * 44B= 0x23368)

QM3 Sched(3278 * 44B= 0x23368)

0x0E9A38

0x10CDA0 QM0 Freelist(3278 * 4B= 0x3338)

QM1 Freelist(3278 * 4B= 0x3338)

QM2 Freelist(3278 * 4B= 0x3338)

QM3 Freelist(3278 * 4B= 0x3338)

0x1100D8

0x113410

0x116748 Unallocated

0x119A80

0x7FFFFF

QSCHED Params(Rate and Intfc) (128B)

0x119B000x119AFF

14 - David M. Zar – 04/21/23

Extra Slides The rest of the slides are old or here for extra

info.

15 - David M. Zar – 04/21/23

LC Egress SRAM Channel 1QM0 QParams

(65536 * 16B)0x000000

0x100000 QM1 QParams(65536 * 16B)

QM2 QParams(65536 * 16B)

0x200000

0x300000 QM3 QParams(65536 * 16B)QM0 Sched

(13109 * 44B= 0x8CD1C)

0x48CD1C

0x400000

0x519A38

QM1 Sched(13109 * 44B= 0x8CD1C)

QM2 Sched(13109 * 44B= 0x8CD1C)

QM3 Sched(13109 * 44B= 0x8CD1C)

0x5A6754

0x633470 QM0 Freelist(13109 * 4B= 0xCCD4)

QM1 Freelist(13109 * 4B= 0xCCD4)

QM2 Freelist(13109 * 4B= 0xCCD4)

QM3 Freelist(13109 * 4B= 0xCCD4)

0x640344

0x64D018

0x659CEC Unallocated0x6669C00x7FFFFF

16 - David M. Zar – 04/21/23

LC Ingress SRAM Channel 1QM0 QParams

(65536 * 16B)0x000000

0x100000 QM1 QParams(65536 * 16B)

QM2 QParams(65536 * 16B)

0x200000

0x300000 QM3 QParams(65536 * 16B)QM0 Sched

(13109 * 44B= 0x8CD1C)

0x48CD1C

0x400000

0x519A38

QM1 Sched(13109 * 44B= 0x8CD1C)

QM2 Sched(13109 * 44B= 0x8CD1C)

QM3 Sched(13109 * 44B= 0x8CD1C)

0x5A6754

0x633470 QM0 Freelist(13109 * 4B= 0xCCD4)

QM1 Freelist(13109 * 4B= 0xCCD4)

QM2 Freelist(13109 * 4B= 0xCCD4)

QM3 Freelist(13109 * 4B= 0xCCD4)

0x640344

0x64D018

0x659CEC Unallocated0x6669C00x7FFFFF

17 - David M. Zar – 04/21/23

NPE/MR SRAM Channel 1QM0 QParams

(65536 * 16B)0x000000

0x100000 QM1 QParams(65536 * 16B)

QM2 QParams(65536 * 16B)

0x200000

0x300000 QM3 QParams(65536 * 16B)QM0 Sched

(13109 * 44B= 0x8CD1C)

0x48CD1C

0x400000

0x519A38

QM1 Sched(13109 * 44B= 0x8CD1C)

QM2 Sched(13109 * 44B= 0x8CD1C)

QM3 Sched(13109 * 44B= 0x8CD1C)

0x5A6754

0x633470 QM0 Freelist(13109 * 4B= 0xCCD4)

QM1 Freelist(13109 * 4B= 0xCCD4)

QM2 Freelist(13109 * 4B= 0xCCD4)

QM3 Freelist(13109 * 4B= 0xCCD4)

0x640344

0x64D018

0x659CEC Unallocated0x6669C00x7FFFFF

18 - David M. Zar – 04/21/23

Egress Scratch Memory (16 KB)

0x0000

0x3FFC

PACKET_TX_AVAIL_TBUF_ELE_SCR_ADDR

TO_SCALE_RING

FROM_XSCALE_RING

COUNTER_RING

PS_TO_QM_RING_1

PS_TO_QM_RING_2

QM_TO_TX_RING_1

QM_TO_TX_RING_2

0x1F00

0x3000

0x3400

0x3800

0x3c00

0x1F04

0x2800

0x2400

…

0x2C00

19 - David M. Zar – 04/21/23

dl_system#define BUF_SRAM_BASE SRAM_CHANNEL_1_BASE_ADDRESS#define NUM_IN_PORTS 10 ; number of input ports #define NUM_OUT_PORTS 10 ; number of output ports

#define_eval PACKET_COUNTERS_SRAM_BASE SRAM_CHANNEL_3_BASE_ADDRESS #define RX_PACKET_COUNTERS_SRAM_SIZE 16 * NUM_IN_PORTS#define_eval PACKET_TX_COUNTER_BASE PACKET_COUNTERS_SRAM_BASE +

RX_PACKET_COUNTERS_SRAM_SIZE #define PACKET_TX_COUNTER_SIZE 16 * NUM_OUT_PORTS

#define PS_TO_QM_RING_1 7#define PS_TO_QM_RING_1_SIZE 256#define PS_TO_QM_RING_1_BASE 0x3000

#define PS_TO_QM_RING_2 8#define PS_TO_QM_RING_2_SIZE 256#define PS_TO_QM_RING_2_BASE PS_TO_QM_RING_1_BASE + 4 * PS_TO_QM_RING_1_SIZE

#define QM_TO_TX_RING_1 9#define QM_TO_TX_RING_1_SIZE 256#define QM_TO_TX_RING_1_BASE PS_TO_QM_RING_2_BASE + 4 * PS_TO_QM_RING_2_SIZE

#define QM_TO_TX_RING_2 10#define QM_TO_TX_RING_2_SIZE 256#define QM_TO_TX_RING_2_BASE QM_TO_TX_RING_1_BASE + 4 * QM_TO_TX_RING_1_SIZE

Um, shouldn’t this be “4” for the four bytes

per queue entry? And… Should the rings be

256 or 512?

20 - David M. Zar – 04/21/23

Planet Lab Memory Map The following SRAM is used in every design:

»Buffer Descriptors in Channel 1 (8 MB): 0x40000000»RX PACKET COUNTERS (debug) in Channel 3 (640

bytes)»TX PACKET COUNTERS (debug) in Channel 3 (640

bytes) Scratch Memory usage:

»TO_XSCALE_RING: 0x2800 – 0x2bff»FROM_XSCALE_RING: 0x2c00 - 0x2cff»PS_TO_QM_RING_1: 0x3000 – 0x33ff»PS_TO_QM_RING_2: 0x3400 - 0x37ff»QM_TO_TX_RING_1: 0x3800 – 0x3bff»QM_TO_TX_RING_2: 0x3c00 – 0x3fff»TX1 - PACKET_TX_AVAIL_TBUF_ELE_SCR_ADDR:

SCRATCH_BASE + 0x1f00

21 - David M. Zar – 04/21/23

Substrate Decap (IPv4) Memory Map

Initialization data»Enet MAC Addr MR blade (48b)

Dynamic Data»VLAN-to-CodeOption index table

2^12 = 4096 VLANs 4b Code Option field 1LW for minimal cycles (16KB req’d: SRAM) or, 4b for minimum memory (2KB req’d: SRAM, Scratch, LM)

»Counters 2 LWs total for packets received & sent 4 LWs total for Ethernet VLAN validation 6 LWs per VLAN for UDP/IP validation

using power-of-2 sizes saves cycles; multiply becomes shift now 32B per VLAN x 4096 VLANs = 128KB SRAM req’d

22 - David M. Zar – 04/21/23

Parse (IPv4) Memory Map Initialization data

»none; only compile-time constants and ring data used

Dynamic Data: counters»2 LWs total for packets received and sent»9 LWs per VLAN for UDP/IP validation

using power-of-2 sizes saves cycles; multiply becomes shift now 64B per VLAN x 4096 VLANs = 256KB SRAM req’d

23 - David M. Zar – 04/21/23

Lookup (IPv4) Memory Map Initialization data Dynamic Data

24 - David M. Zar – 04/21/23

HF(IPv4) Memory Map Initialization data (88b + #GP*88b)

»Enet Addr MR blade (48b)» IP Addr MR blade (32b)»#GPs (8b)»Table[#GP]

Enet Addr (8b) Upper 40 bits are same as Enet Addr MR Blade above

IP Addr (8b) Upper 24 bits are same as IP Addr MR Blade above

Local Delivery UDP dest (16b) QID (20b)

Exception UDP dest (16b) QID (20b)

Dynamic Data (None)

25 - David M. Zar – 04/21/23

QM (IPv4/LCI/LCE) Memory Map Constants

» #Q – 128K (total for all QM)» QM_NUM_QUEUES» QD_BASE_ADDR 0x000000» QD_SIZE 0x200000» QPARAMS_BASE_ADDR 0x200000» QPARAMS_SIZE 0x200000» QSCHED_BASE_ADDR 0x400000» QSCHED_SIZE 0x140000» PORT_RATES_BASE_ADDR 0x540000» PORT_RATES_SIZE 0x28

Initialization data (none) Dynamic Data (SRAM)

» Port Rates (5 * 32b)» Per Queue

Queue Parameters (per queue) Discard Threshold (32b) Quantum (32b) Qlen (32b) Rsvd (32b)

Queue Descriptor (128b) Scheduling Structure/Freelist (SRAM) (12W/5Q)

26 - David M. Zar – 04/21/23

KeyExtractor (LC) Memory Map Ingress

» Initialization data (none)» Dynamic Data (none)

Egress» Initialization data (none)» Dynamic Data (none)

27 - David M. Zar – 04/21/23

Lookup (LC) Memory Map Ingress

» Initialization»Dynamic Data (none)

Egress» Initialization (none)»Dynamic Data (none)

28 - David M. Zar – 04/21/23

HF (LC) Memory Map Ingress

» Initialization Enet Addr (48b)

»Dynamic Data (none)

Egress» Initialization (none)»Dynamic Data (none)

29 - David M. Zar – 04/21/23

Port Splitter (LC) Memory Map Ingress

» Initialization (none)»Dynamic Data (none)

Egress» Initialization (none)»Dynamic Data (none)

30 - David M. Zar – 04/21/23

SRAM Channel 1 (8 MB) – 0x40000000

0x000000

0x7FFFFC

Queue Parameters - Each is 4, 32-bit words (16 bytes) - So room for 64K

Queue Scheduling Structure (*2) - Each is 11, 32-bit words (44 bytes) - Allocated 13109

Queue Free List (*2) - Each is 1, 32-bit words (4 bytes) - Allocated 13109 (same as # of QSS)

Port Rates - Each is 1, 32-bit words (4 bytes) - Ten ports

0x100000

0x219A38

0x2333E0

.

.

.

0x233408

31 - David M. Zar – 04/21/23

SRAM Channel 2 (8 MB) – 0x80000000

0x000000

0x7FFFFC

BUF_SRAM_BASE - Buffer Descriptors - Each is 8 32-bit words (32 bytes) - So room for 224K

Queue Descriptors - Each is 4 32-bit words (16 bytes) - So room for 64K

0x6FFFFF

32 - David M. Zar – 04/21/23

IPv4 SRAM Channel 3 (8 MB) – 0xC0000000

0x000000

0x190000

0x010000

0x090000

Packet/Byte Counters (4 words * 16K) - PRE_Q_PKT_CNT - PRE_Q_BYTE_CNT - POST_Q_PKT_CNT - POST_Q_BYTE_CNT

MI Counters (512K) - PRE_Q_PKT_CNT - PRE_Q_BYTE_CNT - POST_Q_PKT_CNT - POST_Q_BYTE_CNT

Initialization Data

0x7FFFFC

33 - David M. Zar – 04/21/23

IPv4 SRAM Channel 3 (8 MB) – 0xC0000000

0x000000

0x001000

Per Block Initialization MemoryRX: Base = 0x000000, Size = 0SD: Base = 0x000000, Size = 8PR: Base = 0x000008, Size = 0LK: Base = 0x000008, Size = 0HF: Base = 0x000008, Size = 8PS: Base = 0x000010, Size = 0QM: Base = 0x000010, Size = 0TX: Base = 0x000010, Size = 0

0x000010

34 - David M. Zar – 04/21/23

IPv4 SRAM Channel 3 (8 MB) – 0xC0000000

0x001000

0x100000

Per Block Dynamic MemoryRX: Base = 0x001000, Size = 0x280TX: Base = 0x001280, Size = 0x280SD: Base = 0x001500, Size = 0x24018PR: Base = 0x025018, Size = 0x40008

IPv4 POST_Lookup Counters (PreQ, PostQ):Base: 0x025018, Size 0x0010000

0x074520

35 - David M. Zar – 04/21/23

IPv4 SRAM Channel 3 (8 MB) – 0xC0000000

0x7FFFFC

0x100000

BUF_SRAM_BASE - Buffer Descriptors - Each is 8 32-bit words (32 bytes) - (0x800000 – 0x100000)/32B = 229376 - So room for 229376 Buffer Descriptors

36 - David M. Zar – 04/21/23

LC SRAM Channel 3 (8 MB) – 0xC0000000

0x000000

0x7FFFFC

PACKET_COUNTERS_SRAM_BASE - 16 words per port, 16 ports (1024 bytes, total) - Used in RX for debugging

PACKET_TX_COUNTER_BASE - 16 words per port, 16 ports (1024 bytes, total)

Per Lookup Result Counters (pre-Q and post-Q) - 16 MR, 256 indices, 4 32-bit counters per index = 64KB (See next slide for ctr details)

Per MI Counters - 64K * 2 * 4 = 512KB

0x000400

0x000800

0x010800

0x0908000x100000

37 - David M. Zar – 04/21/23

LC Ingress SRAM Channel 1Q Params

(65536 * 16B)

QM0 Sched(13109 * 44B= 0x8CD1C)

QM1 Sched(13109 * 44B= 0x8CD1C)

•QM0 Freelist•(13109 * 4B = 0xCCD4)

•QM1 Freelist•(13109 * 4B = 0xCCD4)

QM0 & QM1 Port Rates(10 * 4B)

Unallocated

0x000000

0x100000

0x18CD1C

0x219A38

0x22670C

0x2333E0

0x233418

0x600000Unallocated

0x7FFFFF

38 - David M. Zar – 04/21/23

LC Egress SRAM Channel 1Q Params

(65536 * 16B)

QM0 Sched(13109 * 44B= 0x8CD1C)

QM1 Sched(13109 * 44B= 0x8CD1C)

•QM0 Freelist•(13109 * 4B = 0xCCD4)

•QM1 Freelist•(13109 * 4B = 0xCCD4)

QM0 & QM1 Port Rates(10 * 4B)

Unallocated

0x000000

0x100000

0x18CD1C

0x219A38

0x22670C

0x2333E0

0x233418

0x600000Unallocated

0x7FFFFF

39 - David M. Zar – 04/21/23

NPE/MR SRAM Channel 1Q Params

(65536 * 16B)

QM0 Sched(13109 * 44B= 0x8CD1C)

QM1 Sched(13109 * 44B= 0x8CD1C)

•QM0 Freelist•(13109 * 4B = 0xCCD4)

•QM1 Freelist•(13109 * 4B = 0xCCD4)

QM0 & QM1 Port Rates(10 * 4B)

Unallocated

0x000000

0x100000

0x18CD1C

0x219A38

0x22670C

0x2333E0

0x233418

0x600000Unallocated

0x7FFFFF

40 - David M. Zar – 04/21/23

LC Ingress SRAM Channel 1QM0 QParams

(16384 * 16B)

0x000000

0x040000 QM1 QParams(16384 * 16B)

QM2 QParams(16384 * 16B)

0x080000

0x0C0000 QM3 QParams(16384 * 16B)QM0 Sched

(3278 * 44B= 0x23368)0x123368

0x100000

0x1466D0

QM1 Sched(3278 * 44B= 0x23368)

QM2 Sched(3278 * 44B= 0x23368)

QM3 Sched(3278 * 44B= 0x23368)

0x169A38

0x18CDA0 QM0 Freelist(3278 * 4B= 0x3338)

QM1 Freelist(3278 * 4B= 0x3338)

QM2 Freelist(3278 * 4B= 0x3338)

QM3 Freelist(3278 * 4B= 0x3338)

0x1900D8

0x193410

0x196748 Unallocated

0x199A80

0x7FFFFF

QM0 Sched0 QParams(2048 * 16B)

0x000000

0x008000 QM0 Sched1 QParams(2048 * 16B)

QM0 Sched2 QParams(2048 * 16B)

QM0 Sched3 QParams(2048 * 16B)

QM0 Sched4 QParams(2048 * 16B)

Unused QParams(2048 * 16B)

Unused QParams(2048 * 16B)

Unused QParams(2048 * 16B)0x040000

0x010000

0x018000

0x020000

0x028000

0x030000

0x038000

QSCHED Params(Rate and Intfc) (128B)

0x199B000x199AFF

41 - David M. Zar – 04/21/23

LC Egress SRAM Channel 1QM0 QParams

(65536 * 16B)0x000000

0x100000 QM1 QParams(65536 * 16B)

QM2 QParams(65536 * 16B)

0x200000

0x300000 QM3 QParams(65536 * 16B)QM0 Sched

(13109 * 44B= 0x8CD1C)

0x48CD1C

0x400000

0x519A38

QM1 Sched(13109 * 44B= 0x8CD1C)

QM2 Sched(13109 * 44B= 0x8CD1C)

QM3 Sched(13109 * 44B= 0x8CD1C)

0x5A6754

0x633470 QM0 Freelist(13109 * 4B= 0xCCD4)

QM1 Freelist(13109 * 4B= 0xCCD4)

QM2 Freelist(13109 * 4B= 0xCCD4)

QM3 Freelist(13109 * 4B= 0xCCD4)

0x640344

0x64D018

0x659CEC Unallocated0x6669C00x7FFFFF

42 - David M. Zar – 04/21/23

NPE/MR SRAM Channel 1QM0 QParams

(16384 * 16B)

0x000000

0x040000 QM1 QParams(16384 * 16B)

QM2 QParams(16384 * 16B)

0x080000

0x0C0000 QM3 QParams(16384 * 16B)QM0 Sched

(3278 * 44B= 0x23368)0x123368

0x100000

0x1466D0

QM1 Sched(3278 * 44B= 0x23368)

QM2 Sched(3278 * 44B= 0x23368)

QM3 Sched(3278 * 44B= 0x23368)

0x169A38

0x18CDA0 QM0 Freelist(3278 * 4B= 0x3338)

QM1 Freelist(3278 * 4B= 0x3338)

QM2 Freelist(3278 * 4B= 0x3338)

QM3 Freelist(3278 * 4B= 0x3338)

0x1900D8

0x193410

0x196748 Unallocated

0x199A80

0x7FFFFF

QM0 Sched0 QParams(2048 * 16B)

0x000000

0x008000 QM0 Sched1 QParams(2048 * 16B)

QM0 Sched2 QParams(2048 * 16B)

QM0 Sched3 QParams(2048 * 16B)

QM0 Sched4 QParams(2048 * 16B)

Unused QParams(2048 * 16B)

Unused QParams(2048 * 16B)

Unused QParams(2048 * 16B)0x040000

0x010000

0x018000

0x020000

0x028000

0x030000

0x038000

QSCHED Params(Rate and Intfc) (128B)

0x199B000x199AFF

43 - David M. Zar – 04/21/23

NPE/MR SRAM Channel 1QM0 QParams

(16384 * 16B)

0x000000

0x040000 QM1 QParams(16384 * 16B)

QM2 QParams(16384 * 16B)

0x080000

0x0C0000 QM3 QParams(16384 * 16B)QM0 Sched

(3278 * 44B= 0x23368)0x123368

0x100000

0x1466D0

QM1 Sched(3278 * 44B= 0x23368)

QM2 Sched(3278 * 44B= 0x23368)

QM3 Sched(3278 * 44B= 0x23368)

0x169A38

0x18CDA0 QM0 Freelist(3278 * 4B= 0x3338)

QM1 Freelist(3278 * 4B= 0x3338)

QM2 Freelist(3278 * 4B= 0x3338)

QM3 Freelist(3278 * 4B= 0x3338)

0x1900D8

0x193410

0x196748 Unallocated

0x199A80

0x7FFFFF

QM0 Sched0 QParams(2048 * 16B)

0x000000

0x008000 QM0 Sched1 QParams(2048 * 16B)

QM0 Sched2 QParams(2048 * 16B)

QM0 Sched3 QParams(2048 * 16B)

QM0 Sched4 QParams(2048 * 16B)

Unused QParams(2048 * 16B)

Unused QParams(2048 * 16B)

Unused QParams(2048 * 16B)0x040000

0x010000

0x018000

0x020000

0x028000

0x030000

0x038000

QSCHED Params(Rate and Intfc) (128B)

0x199B000x199AFF

44 - David M. Zar – 04/21/23

NPE/MR SRAM Channel 1QM0 QParams

(65536 * 16B)0x000000

0x100000 QM1 QParams(65536 * 16B)

QM2 QParams(65536 * 16B)

0x200000

0x300000 QM3 QParams(65536 * 16B)QM0 Sched

(13109 * 44B= 0x8CD1C)

0x48CD1C

0x400000

0x519A38

QM1 Sched(13109 * 44B= 0x8CD1C)

QM2 Sched(13109 * 44B= 0x8CD1C)

QM3 Sched(13109 * 44B= 0x8CD1C)

0x5A6754

0x633470 QM0 Freelist(13109 * 4B= 0xCCD4)

QM1 Freelist(13109 * 4B= 0xCCD4)

QM2 Freelist(13109 * 4B= 0xCCD4)

QM3 Freelist(13109 * 4B= 0xCCD4)

0x640344

0x64D018

0x659CEC Unallocated0x6669C00x7FFFFF