Prolonged 500 °C Operation of 100+ Transistor Silicon ...€¦ · Prolonged 500 °C Operation of...

Prolonged500°COperationof100+TransistorSiliconCarbideIntegratedCircuits

DavidJ.Spry1,PhilipG.Neudeck1,DorothyLukco2,Liangyu Chen3,MichaelJ.Krasowski1,NormanF.Prokop1,CarlW.Chang2,GlennM.Beheim1

1NASAGlennResearchCenter2VantagePartnersLLC3OhioAerospaceInstitute

National Aeronautics and Space Administration

sic.grc.nasa.gov

https://ntrs.nasa.gov/search.jsp?R=20170010414 2020-04-26T12:12:04+00:00Z

Prolonged500°COperationof100+TransistorSiliconCarbideIntegratedCircuits

Intelligent Propulsion Systems

Hybrid Electric & Turbo Electric Aircraft

SiC Electronics Benefits to NASA Missions

NASAGRC’sinternalresearchefforthasbeentofocusedondurable/stableintegratedcircuit

operationat500°Cfor>1000hrs.

Venus Exploration

1T. Kremic, et al., 48th Lunar and Planetary Science, 2017, 2986.

LLISSE=Long-LifeIn-SituSolarSystemExplorer1

9.4Mpa =92.7XEarthpressure +460°C+chemical

compositionfound atthesurface of

Venus(CO2,N2,SO2,H20,CO,OCS,HCl,HF,and H2S)

Prolonged500°COperationof100+TransistorSiliconCarbideIntegratedCircuits 3

RecentAdvances• ProlongedsiliconcarbideintegratedcircuitoperationinVenussurfaceatmosphericconditions.Neudeck,etal.,AIPAdvances6(2016)125119.

• Demonstrationof4H-SiCDigitalIntegratedCircuitsAbove800°C,Neudeck,etal.,IEEEElectronDeviceLett.38(2016)1082-1085.

NASASiC JFETICoperationatT>900° C

NASASiC JFETICoperateddirectlyimmersedinVenussurfaceconditions(nopackage)for3weeks(didnotfail)

• Normally-on4H-SiCJFET(fabricatedatNASAGlenn)• ResistorsmadewithsameepiaschannelàmatchedTdependence• NegativethresholdvoltageVT à negativesignalvoltages(0to-10V)• 0V=Binary1(high) -10V=Binary0(low)

1M. J. Krasowski, US Patent 7,688,117 (2010).2P. G. Neudeck, D. J. Spry, and L. Chen, Proc. IMAPS High Temperature Electronics Conf., 2016, pp. 263-271.

N-channelJFETdesign1,2 “Version10.1”NOTLogicGateSchematic

JFETICWafer10.1vspastwork1-2• Aluminum FieldStopImplanttoimpedeparasiticfieldMOSFETs.• Heavily-implantedSiC contactregionswereformedusingphosphorusimplantprofilewithslightlylowerenergy&dose.

• Contactwasmadeusing50nmsputteredtitanium layer.

1D. J. Spry, et al., Mat. Sci. Forum 828 (2016) 908-912: “IC Wafer/Version 8.1”2D. J. Spry, et al., IEEE Electron Device Lett. 37 (2016) 625-628: “IC Wafer/Version 9.2”

High-Tpackaging1,2 (32pins)

1L. Chen, et al., Proc. IMAPS High Temperature Electronics Conference, 2016, pp. 66-72.2P. G. Neudeck, et al., IEEE Electron Device Lett. 38 (2016) 1082-1085.

• Packagedurabilityandleakagecharacterized.

4X4RandomAccessMemory(RAM)DemonstrationChip

AddressDecoder

4X4RAMCellArray

Bitline Read/WriteDriveCircuitrywithSenseAmplifiers

OutputBuffers

• 3mmx3mm4H-SiCJFETchipshownpriortopackaging.

• 195JFETs.• 6-TransistorstaticRAMcellapproach.

• Includesaddressdecoders,read/writebitline drivewithsenseamplifiers,outputbuffers.

÷2/÷4ClockDemonstrationChip

21-StageRingOscillatorClock+OutputBuffers

ActiveDFlip-Flops ÷2or÷4

SelectLogic

InactiveDFlip-Flop

HighFrequencyRingOsc.

• 3mmx3mm4H-SiCJFETchippriortopackaging.

• 175JFETs• 21-Stageringoscillatorprovidesbasefrequencyclocksignal

• SELECTdataline:• High(0V)à ÷4output• Low(-10V)à ÷2output

• IncludestwoD-typeflipflopsgovernedbyselectlogic

• 3rdflipflopisinactiveduetolayouterror.

• Optionalmodulationofhigh-fringoscillatorsignal

Wafer10.1ICFunctionalYieldat25°C

• Probe-testmeasurementsat25°Cpriortowaferdicingandcircuitpackaging.

• JFETthresholdvoltageVT ondependsondistancefromthecenterofthewaferr,duetoas-purchasedwaferepilayervariation(seeRef.1).

• TableI isforr <25mm(on38mmradiuswafer),thewaferregion where VT fallswithin circuit designspecifications of|VT|<10V.

1P. G. Neudeck, D. J. Spry, and L. Chen, Proc. IMAPS High TemperatureElectronics Conf., 2016, pp. 263-271.

Wafer10.1500°CPackagedICTests

• Measured 16-bit RAM waveforms showing read and writefunctionality of all bits at 5040 hours of a 500 °C oven test.

4X4RAM#2

• Measured waveforms showing operation of ÷2/÷4clock IC at 5200 hours of 500 °C oven testing.

÷2/÷4ClockChip#2

• Timeevolutionof÷2/÷4clockICoutputvoltagesandfrequencyfor5packagedchipssubjectedtoprolonged500°Coventesting.

• Afterinitialburn-in,outputcharacteristicschange<10%• 3of5chipsremainfunctioningunder500°Ctest.

÷2/÷4ClockChipsvsTimeat500° C

VenusEnvironmentDurabilityFIBFESEM

(a) Crack typical of prolonged T ≥ 500 °C testing in air (727 °C for this sample)• In Earth environment, the crack allows the top surface of the TaSi2 film to oxidize whichexacerbates failure.

(b) Crack in IC sample tested in Venus surface condition.• In Venus environment, the crack reaches the top of the TaSi2 but does not propagatethrough the TaSi2 and there is no observable evidence of TaSi2 film oxidation.

OthersamplesexposedtoVenus• PlatinumformsPlatinumSulfide.

• 200nmthickfilmscompletelyconverted.

• Manymorphologiesfounddependentonsurroundingmaterials.

• Transitionmetalsreacttoformsulfides.• TraceamountsofHCl at0.5ppmandHFat2.5ppbthatwerefoundasreactedproductsinsomesamples.

• Temperatureand/orpressurewithoutincludingthecompletechemistryisnotasufficientmeansofscreeningelectronicsforlong-termoperationintheVenusiansurfaceenvironment.

• SiC,SiO2,Al2O3 remainstable.

Summary• Thecomplexityof4H-SiCJFETIC’sprovendurablefor1000’sofhoursat500°Chasbeensubstantiallyincreasedfrom24transistorsto175+transistors.

• Testinginhigh-fidelityreproductionoftheVenussurfaceenvironmentisnecessarytocontinueelectronicsdevelopmentandqualificationtestingbuildingtowardslong-termVenussurfacemissions.

AcknowledgementsFundedbyNASATransformative

AeronauticsConceptsProgramHX5Sierra• KelleyMoses• JoseGonzalez• MichelleMrdenovich• ArianaMillerNASAGlennResearchCenter• GaryHunter• RobertButtler• RogerMeredithCaseWesternReserveUniversity• AmirAvishai

Prolonged500°COperationof100+TransistorSiliconCarbideIntegratedCircuitsYourTitleHere 18

STARC-ABL: Single-aisle Turboelectric AiRCraft with Aft Boundary Layer propulsion

TypicalCrackPropagationinEarthAir

• This sample was at 727 °C sample and a old (Version 9.2) design.Same kind of behavior when seen on some 500 °C samples.

• Cracks related to dicing, handling, design rules, and bonding.• Various degrees of oxidation and peeling seen.• Oxidation of TaSi2 surface can be many 10s of microns wide.

CrackatVenusSurfaceConditions

• Only one crack seen on entire sample exposed to Venus.• Found via optical microscope and then examined onSEM. Hard to find with FESEM.

• Very small (~ 75 nm) when viewed from the top.

AIAA-2013-0586, 51st AIAA Aerospace Sciences Meeting, Grapevine TX, Jan. 7-10 2013

G. Landis, "Robotic Exploration of the Surface and Atmosphere of Venus," Acta Astronautica, Vol. 59, 7, 517-580 (October 2006). Paper IAC-04-Q.2.A.08

Prolonged 500 °C Operation of 100+ Transistor Silicon ...€¦ · Prolonged 500 °C Operation of...

Documents

NPN SILICON RF TRANSISTOR NE68130 / 2SC4227 … · NPN SILICON RF TRANSISTOR NE68130 / 2SC4227 ... (408) 919-2500 • For a complete list of sales offices, representatives and distributors,

Valve & Transistor Data, pt 05 Silicon Transistors

Silicon Transistor NE97833 / 2SA1978 JEITA · Silicon Transistor NE97833 / 2SA1978 PNP EPITAXIAL SILICON TRANSISTOR MICROWAVE AMPLIFIER Document No. P11028EJ1V0DS00 …

A Silicon Nanocrystal Tunnel Field E ect Transistor - arXiv · A Silicon Nanocrystal Tunnel Field E ect Transistor Patrick Harvey-Collard,1,2,3, a) ... a low 30 pA/ m leakage current

Valve & Transistor Data, pt 09 Silicon Reference Diodes

A Single-Transistor Silicon Synapse · 2017-02-27 · 1972 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 11, NOVEMBER 1996 A Single-Transistor Silicon Synapse Chris Diorio,

Transistor-Based Ge/SOI Photodetector for Integrated ... · Transistor-Based Ge/SOI Photodetector for Integrated Silicon ... Transistor-Based Ge/SOI Photodetector for Integrated Silicon

Silicon Transistor NE97733 / 2SA1977 JEITA · Silicon Transistor NE97733 / 2SA1977 PNP EPITAXIAL SILICON TRANSISTOR ... Parameter Symbol Rating Unit ... Rank FB Marking T92

BFU550 NPN wideband silicon RF transistor - f6kgl-f5kff.frf6kgl-f5kff.fr/lessamedistechniques/bfu550.pdf · 1. Product profile 1.1 General description NPN silicon RF transistor for

Lateral bipolar junction transistor on a silicon photonics ... · Research Article Vol. 28, No. 8/13 April 2020/Optics Express 11692 Lateral bipolar junction transistor on a silicon

NPN Silicon RF Transistor BFQ 71€¦ · NPN Silicon RF Transistor BFQ 71 ESD : E lectro s tatic d ischarge sensitive device, observe handling precautions! Maximum Ratings Type Ordering

A Double Self-Aligned Silicon Bipolar Transistor Utilizing

NPN wideband silicon RF transistor

NPN SILICON RF TRANSISTOR NE851M13 / 2SC5801 Observe precautions when handling because these devices are sensitive to electrostatic discharge NPN SILICON RF TRANSISTOR NE851M13 / 2SC5801

A Single-Transistor Silicon Synapse · 2015-01-14 · 1972 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 11, NOVEMBER 1996 A Single-Transistor Silicon Synapse Chris Diorio,

BFU550A NPN wideband silicon RF transistor · NPN silicon RF transistor for high speed, low noise applications in a plastic, ... Download from the BFU550A product information page

SILICON TRANSISTOR NE85619 / 2SC5006 · SILICON TRANSISTOR Document No. P10385EJ2V0DS00 (2nd edition) (Previous No. TD-2399) Date Published July 1995 P NE85619 / 2SC5006 NPN SILICON

SILICON TRANSISTOR NE68033 · PDF filesilicon transistor ne68033 / 2sc3585 microwave low noise amplifier npn silicon epitaxial transisor data sheet ... total power dissipation pt 200

Selectively Grown Silicon Nano-Wires for Transistor Devices Abstract The goal of this project is to fabricate a transistor device using silicon nano-wires

NPN SILICON RF TRANSISTOR NE462M02 / 2SC5338 / 2SC5338 NPN SILICON RF TRANSISTOR FOR HIGH-FREQUENCY LOW DISTORTION AMPLIFIER 4-PIN POWER MINIMOLD The mark ’’’’ shows major