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PERANCANGAN SISTEM DIGITALPERANCANGAN SISTEM DIGITAL
Dosen :
TEKNIK ELEKTRO
Dosen :Andi Hasad
http://andihasad.wordpress.com
TEKNIK ELEKTROUNIVERSITAS ISLAM “45”
BEKASI
Topic 9 Slide 1PYKC 3-Mar-08 E3.05 Digital System Design
Topic 9
JTAG Boundary-Scan
Peter CheungDepartment of Electrical & Electronic Engineering
Imperial College London
(Based on Ben Bennetts’ Tutorial)
URL: www.ee.imperial.ac.uk/pcheung/E-mail: p.cheung@imperial.ac.uk
Topic 9 Slide 2PYKC 3-Mar-08 E3.05 Digital System Design
Sources & Background
JTAG Boundary Scan is from
IEEE Standard 1149.1Most of slides here are based on the document “Boundary Scan Tutorial” by Ben Bennetts, for ASSET InterTech Inc., ww.asset-intertech.com/pdfs/boundaryscan_tutorial.pdf
Topic 9 Slide 3PYKC 3-Mar-08 E3.05 Digital System Design
The old way
Topic 9 Slide 4PYKC 3-Mar-08 E3.05 Digital System Design
Problem with modern packaging styles
Topic 9 Slide 5PYKC 3-Mar-08 E3.05 Digital System Design
Problem with multi-layer PCB
Topic 9 Slide 6PYKC 3-Mar-08 E3.05 Digital System Design
Motivation of Boundary Scan
Topic 9 Slide 7PYKC 3-Mar-08 E3.05 Digital System Design
Principle of Boundary Scan
Topic 9 Slide 8PYKC 3-Mar-08 E3.05 Digital System Design
The Boundary Scan Path
Topic 9 Slide 9PYKC 3-Mar-08 E3.05 Digital System Design
Basic Boundary Scan Cell
Topic 9 Slide 10PYKC 3-Mar-08 E3.05 Digital System Design
Defect Coverage: Bed-of-nails
Topic 9 Slide 11PYKC 3-Mar-08 E3.05 Digital System Design
Defect Coverage: Extest
Topic 9 Slide 12PYKC 3-Mar-08 E3.05 Digital System Design
Defect Coverage: Intest
Topic 9 Slide 13PYKC 3-Mar-08 E3.05 Digital System Design
1149.1 Chip Architecture
Topic 9 Slide 14PYKC 3-Mar-08 E3.05 Digital System Design
Mandatory Instructions and Reset Modes
Topic 9 Slide 15PYKC 3-Mar-08 E3.05 Digital System Design
Target Register Modes
Topic 9 Slide 16PYKC 3-Mar-08 E3.05 Digital System Design
Open-Circuit TDI, TMS and TRST*?
Topic 9 Slide 17PYKC 3-Mar-08 E3.05 Digital System Design
Instruction Register
Topic 9 Slide 18PYKC 3-Mar-08 E3.05 Digital System Design
Standard Instructions
Topic 9 Slide 19PYKC 3-Mar-08 E3.05 Digital System Design
Extest Instructions
Topic 9 Slide 20PYKC 3-Mar-08 E3.05 Digital System Design
Bypass Instruction
Topic 9 Slide 21PYKC 3-Mar-08 E3.05 Digital System Design
Sample and Preload Instruction
Topic 9 Slide 22PYKC 3-Mar-08 E3.05 Digital System Design
Intest Instruction
Topic 9 Slide 23PYKC 3-Mar-08 E3.05 Digital System Design
Idcode Instruction
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Topic 9 Slide 24PYKC 3-Mar-08 E3.05 Digital System Design
Usercode Instruction
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Topic 9 Slide 25PYKC 3-Mar-08 E3.05 Digital System Design
RunBIST Instruction
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Topic 9 Slide 26PYKC 3-Mar-08 E3.05 Digital System Design
Clamp Instruction
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Topic 9 Slide 27PYKC 3-Mar-08 E3.05 Digital System Design
HighZ Instruction
Topic 9 Slide 28PYKC 3-Mar-08 E3.05 Digital System Design
Test Access Port (TAP)
Topic 9 Slide 29PYKC 3-Mar-08 E3.05 Digital System Design
TAP Controller
Topic 9 Slide 30PYKC 3-Mar-08 E3.05 Digital System Design
TAP Controller State Diagram
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Topic 9 Slide 31PYKC 3-Mar-08 E3.05 Digital System Design
Bypass Register
Topic 9 Slide 32PYKC 3-Mar-08 E3.05 Digital System Design
Identification Register
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Topic 9 Slide 33PYKC 3-Mar-08 E3.05 Digital System Design
Boundary Scan Register
Topic 9 Slide 34PYKC 3-Mar-08 E3.05 Digital System Design
Boundary Scan Cell OZ
Topic 9 Slide 35PYKC 3-Mar-08 E3.05 Digital System Design
Boundary Scan Cell IO
Topic 9 Slide 36PYKC 3-Mar-08 E3.05 Digital System Design
Application at Board Level
Topic 9 Slide 37PYKC 3-Mar-08 E3.05 Digital System Design
Board Defects
Topic 9 Slide 38PYKC 3-Mar-08 E3.05 Digital System Design
Example of faults
Topic 9 Slide 39PYKC 3-Mar-08 E3.05 Digital System Design
Generating Open and Short Test
Topic 9 Slide 40PYKC 3-Mar-08 E3.05 Digital System Design
How many tests are needed?
Topic 9 Slide 41PYKC 3-Mar-08 E3.05 Digital System Design
Building the tests
Topic 9 Slide 42PYKC 3-Mar-08 E3.05 Digital System Design
Number of Tests
Topic 9 Slide 43PYKC 3-Mar-08 E3.05 Digital System Design
Testing non-Boundary Scan cluster
Topic 9 Slide 44PYKC 3-Mar-08 E3.05 Digital System Design
Combining BS and Nails
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Topic 9 Slide 45PYKC 3-Mar-08 E3.05 Digital System Design
RAM Array Testing via Boundary Scan
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Topic 9 Slide 46PYKC 3-Mar-08 E3.05 Digital System Design
Tool Flow for Boundary Scan Tests
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Topic 9 Slide 47PYKC 3-Mar-08 E3.05 Digital System Design
Hardware Requirement
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Topic 9 Slide 48PYKC 3-Mar-08 E3.05 Digital System Design
Where are we today?
Topic 9 Slide 49PYKC 3-Mar-08 E3.05 Digital System Design
Spread of Design-for-Test (DFT)
ReferencesReferences
Davis Justin. 2006. High-Speed Digital System Design, Morgan &Claypool Publishers’ series, USA
Johnson, Graham. High-Speed Digital Design – A Handbook of BlackMagic, Prentice Hall, New Jersey, USAMagic, Prentice Hall, New Jersey, USA
Hasad Andi. 2011, Materi Kuliah Perancangan Sistem Digital, TeknikElektro, UNISMA, Bekasi
Wakerly John F. 2005. Digital Design, Principles & Practices, 4th Edition,Wakerly John F. 2005. Digital Design, Principles & Practices, 4th Edition,Prentice Hall, USA
Wolf Wayne. 2004. FPGA-Based System Design, Prentice-HallWolf Wayne. 2004. FPGA-Based System Design, Prentice-HallPublishers, Inc.
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