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3D IC Packaging
3D IC Integration
John H. Lau
ASM Pacific Technology
16-22 Kung Yip Street, Kwai Chung, Hong Kong
852-2619-2757, john.lau@asmpt.com
1 CPMT Distinguish Lecture, San Diego Chapter, February 23, 2015
Contents 3D IC Packaging (without TSV)
Stack Chips by Wire Bonding
Package-on-Package (PoP)
Chip-to-Chip Interconnects
Embedded Fan-Out Wafer Level Package (eWLP)
Infineon, Freescale, TSMC’s eWLP
Infineon, ASE, Amkor, STATSchippac, STMicroelectroinc’s 3D eWLP
3D IC Integration
Memory-Chip Stacking in Production
Hybrid Memory Cube (HMC)
Intel’s Knight’s Landing with HMC
Fujitsu’s Supercomputer with HMC
Altera’s FPGA with HMC
Wide I/O DRAM and Wide I/O 2
High Bandwidth Memory (HBM)
Samsung’s Widcon Technology for Mobile Products
2.5D IC Integration
Xilinx/TSMC’s Interposer
Altera/TSMC’s Interposer
ITRI’s Interposer for 3D IC Integration
Supply Chains and Ownerships for 2.5D/3D IC Integration
Recent Advances in Package Substrates
Coreless Substrates
Thin-Film Layer on Build-up Package Substrate
Embedded Interposer/Bridge
3D MEMS and IC Integration
3D CIS and IC Integration
Summary and Q&A
2
Technology
Ma
turi
ty
Basic/
Applied
R&D
Applied
R&D
Mass
Production
Commercia
-lization
Die
Stacking
with wire
bonds
Package
on
Package
(PoP)
Stacking
C2C, C2W,
W2W
Stacking
W2W
Stacking
Full swing production for memories.
Volume production for mobile
products.
Active applied R&D is
undertaken by Research
Institutes. TSV cost is the key. In
the phase of industrialization.
Still in upstream research,
technological challenges
such as KGD, yield & device
architecture and EDA are key
issues.
3D IC Packaging 3D IC Integration 3D Si Integration
3D Integration Technologies
Lau, IEEE-ECTC PDC , 2009
Don’t use TSV Use TSV technology
3
3D IC Packaging
(No TSV)
4
Memory Stacked with Wirebonds
Solder Bumped Flip Chip Assembly
Package-on-Package (PoP)
Chip-to-Chip Interconnects
Embedded Fan-Out Wafer Level
Package (eWLP)
5
Memory Stacked with
Wirebonds
6
Bevel or
Notch
Die attach
material
Bond
wires Memory
chips
Substrate
Chip 1
Chip 2
Chip 3
Memory chips stacking by die attach and wire
bonding [1994, nCHIP]
Samsung’s Eight-Stack Flash in Apple’s iPhone 4s
7
Wire bonding Nand
Flash chips
Molding
SK Hynix’s MLC (Multi Level Cell) 8GB (Gigabyte)
NAND Flash in Apple’s iPhone 5s
FBGA (Fine-pitch
Ball Grid Array)
Top
Chip
Bottom Chip
Substrate
Amkor’s 3D IC Packaging with Cu Wires
8
Cu
Wires
9
Package-on-Package
(PoP)
Elpida’s 1GB LPDDR3 Apple’s A7 processor
2-2-2 Build-up package substrate
10
PoP (Package-on-Package) Format
(Apple A7 Application Processor Chipset)
Top-View and Cross Section View of the PoP
(for Mobile DRAM and A8 Processor) inside iPhone 6 Plus
Elpida’s 1GB LPDDR3
(EDF8164A3PM-GD-F)
Apple’s application processor
(POXY99001) Not-to-scale
Package Substrate for LPDDR3
Package Substrate for A8 processor
Top-side of the bottom PoP (426-ball)
Application
Processor
Top-View and Cross Section View of the PoP
(for Mobile DRAM and Application Processor)
Elpida’s 1GB LPDDR3
(EDF8164A3PM-GD-F)
A8 application processor
fabricated by 20nm process Not-to-scale
Package Substrate for LPDDR3
Package Substrate for A8 processor
iPhone 6 Plus
2GB LPDDR4
A9 application processor
fabricated by 14/16nm Fin-FET process
Package Substrate for LPDDR4
Package Substrate for A9 processor
iPhone 6S
Flash chip-set
LPDDR3 Exynos
Microprocessor
Exynos
Microprocessor
ePoP
(Flash and LPDDR3
combination)
A 40% PCB saving!
Conventional
Solution
ePoP
Solution
Samsung’s Next Generation High-End Smartphones
ePoP
PCB
PCB
14
Chip-to-Chip
Interconnects
IME’s Stacked Silicon Module Attached on a Substrate
Chip-to-Chip and Face-to-Face
15
Daughter Chip
Mother Chip
Rigid or Flex Substrate
Heat spreader/sink (optional)
PCB
Microbump
Solder Ball
Solder Bump
Lim, Lau, et.al., “Process Development and Reliability of Microbumps”, IEEE/EPTC, 2008, pp. 367-372. Also,
IEEE Transactions on CPMT, 2010, pp. 747-753.
SONY's CXD53135GG used a 5-chip stack.
(Wire bonding and solder bump)
Solder
bumps
Wire bonds Face-to-face (Chip-to-chip)
Processor
Samsung 1-Gb wide I/O SDRAM
Samsung 2-Gb mobile DDR2 SDRAMs
Processor: 250μm. All the other chips:
100 to 125μm a spacer die
Samsung 2-Gb mobile DDR2 SDRAMs
16
Amkor’s POSSUM™ assembly where the daughter die (e.g.,
memory) is mounted face-to-face with the larger mother die (e.g.,
SoC). The mother die is then flip chip mounted onto a substrate
Daughter
Die
Cu Pillar
Micro-bumps
17
Amkor’s Double POSSUM™ multi-stacked die
configurations without the use of TSVs
Cu Pillar Micro-bumps
with SnAg solder caps Mother Die
Daughter Die
Grandma Die
Package
Substrate
PCB
Cu
SnAg
Sutanto, J., “POSSUMTM, “Die Design as a Low Cost 3D Packaging Alternative”, 3D Packaging, Issue No. 25, November 2012, pp. 16-18.
18
Amkor’s POSSUM Package showing Altera’s
FPGA and ASIC
FPGA
FPGA ASIC
Package Substrate ASIC
Heat spreader cap
FPGA ASIC 40μm-pitch Cu-pillar +
solder cap microbumps
Solder
balls
Package
Substrate
200μm-pitch Cu-
post + solder
Heat spreader cap
Solder balls
FPGA Package Substrate
ASIC
40μm-pitch Cu-pillar +
solder cap microbumps
200μm-pitch Cu-
post + solder
Package
Substrate
Xie, J., and D. Patterson, “Realizing 3D IC Integration with Face-to-Face Stacking”, Chip Scale Review, May-June Issue, 2013, pp. 16-19.
Lau
19
20
Embedded Fan-Out
Wafer Level Package
(eWLP)
Infineon’s Embedded Wafer-Level
Ball Grid Array (eWLB)
Chip
Fan-Out
Area (Mold) Redistribution
Layer (RDL)
Schematic process flow for a fan-out
wafer-level package
Molded reconfigured
wafer
Test for KGD
Brunnbauer, et.al., “An Embedded Device Technology Based on a Molded Reconfigured Wafer”, IEEE/ECTC, 2006, pp. 547-551.
21
a) Laminate Carrier, b) Pick and Place, c) Molding, d)
Release Tape, and e) Peal Tape
Chip face-down
2-side tape
Carrier
Molding
Peal tape
Infineon picked a
modified, commercially
available tape, which is
equipped with a thermo-
release layer. It is loosing
its adhesive properties
once it is heated above a
specific temperature,
which is higher than any
processing temperature
before.
ECTC2006 22
Infineon’s chip is a wireless baseband SoC with multiple integrated
functions (GPS, FM radio, BT…). The same eWLB product has also
been in production in Nokia handsets since 2010.
LGE (wireless baseband), Samsung (baseband modem), and Nokia
(baseband modem and RF transceiver) have used Infineon’s eWLB in
their cell phone products.
Infineon eWLB (wireless operation acquired by Intel in 2011)
Intel RF IC 5 mm x 5 mm x 0.67 mm with 139 I/Os and 0.4mm ball pitch
Intel LTE analog baseband
Infineon was the First Company to Commercialize its own eWLB
Packaging Technology in an LGE cell-phone in early 2009
Baseband SoC Mold
Solder ball
PCB
RDLs
23
Freescale’s Redistributed Chip Package (RCP)
Place die active side down on substrate and encapsulated
with a silica-filled epoxy molding compound
Remove substrate and turn the whole around
Redistribute signal, power and ground
Deposit BGA solder balls
Saw panel into individual package
200mm RCP panel with 82
17mmx17mm 208 I/O packages
A 208 I/O 13mmx13mm PBGA with 0.65mm pitch can
be shrunk to a 9mmx9mm RCP with 0.5mm pitch
Keser, et.al., “The Redistributed Chip Package: A Breakthrough for Advanced Packaging”, IEEE/ECTC, 2007, pp. 286-291.
24
Fan-Out eWLP (Embedded Wafer-Level Packaging)
Solder balls
Pads
RDLs KGD
25
Embedded Fan-Out Wafer Level Package (eWLP) vs.
PBGA (Plastic Ball Grid Array)
Eliminate solder bumps, underfill, and package substrate.
Lower Profile!
Substrate Underfill
Solder Bumps Solder Balls
Redistribution layer
(RDL)
Fan-out area
(Molded Compound)
Solder Balls
Molded Compound
Face-down Chip
Face-down Chip
26
Infineon’s Embedded Wafer-Level Ball Grid Array (eWLB)
Package licensed by ASE, STATS ChipPAC, NANIUM,
STMicroelectronics
Freescale’s Redistributed Chip Package (RCP) licensed by
NEPES
TSMC’s Integrated Fan-Out Wafer-Level Package (InFO-WLP)
ASE’s 3D Fan-Out Wafer-Level PoP (FOPOP)
AMKOR’s Wafer-Level Fan-Out (WLFO) Package
SPIL’s Panel Fan-out (P-FO) Package
STATSChipPAC’s Embedded Wafer Level PoP (eWLB-PoP)
PTI (NEPES)’ Fan-Out Wafer-Level Package (FOWLP (RCP)) J-DEVICES’ Wafer-Level Fan-Out Package (WFOP)
ADL Engineering’s Panel Wafer-Level BGA Package (pWLP) STMicroelectronics’ Embedded Wafer Level LGA (eWLL)
NANIUM’s Fan-Out Wafer-Level Package (FO-WLP)
DECA’s Fan-Out Wafer-Level Packaging (FOWLP)
Embedded Fan-Out Wafer-Level Package (eWLP)
Companies who are Manufacturing/Working on eWLP
27
28
TSMC InFO-WLP
(Integrated Fan-Out WLP)
At the TSMC Technology Symposium in San Jose, CA in April
2014, TSMC announced the latest InFO-WLP platforms:
8mm x 8mm is targeted at RF and WiFi chips
15mm x 15mm is targeted at application processor and baseband chips
25mm x 25mm could be applied to GPU and networking chips
High-Performance Integrated Fan-Out Wafer Level Packaging
(InFO-WLP): Technology and System Integration
Christianto C. Liu, Shuo-Mao Chen, Feng-Wei Kuo, Huan-Neng Chen, En-Hsiang Yeh,
Cheng-Chieh Hsieh, Li-Hsien Huang, Ming-Yen Chiu, John Yeh, Tsung-Shu Lin, Tzu-Jin Yeh,
Shang-Yun Hou, Jui-Pin Hung, Jing-Cheng Lin, Chewn-Pu Jou, Chuei-Tang Wang,
Shin-Puu Jeng, Douglas C.H. Yu
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan, Email: chris liu@tsmc.com
IEEE/IEDM2012
Thermal Management between PBGA and InFO-WLP of
Baseband Chip Set (TSMC Results)
PBGA
InFO-WLP
Baseband
Processor
Baseband
Processor
Tra
nsceiv
er
Tra
nsceiv
er
Not-to-Scale
First, omission of the substrate
layer in InFO-WLP reduces both
form factor and chip-to-board
thermal path, the latter especially
vital in applications without heat
sinks where heat primarily travels
towards the board.
Second, junction-to-ambient
thermal path is reduced with InFO-
WLP’s more efficient multi-chip
packaging.
Third, reduced die separation in
InFO-WLP improves lateral heat
spreading, as shown by the more
uniform heat distribution among the
dies.
Overall, thermal resistance of
InFO-WLP technology is about
14% better than conventional MCM
(28.0 versus 32.5 oC/W). Here, the
difference in thermal
resistance translates to a 9.0oC
reduction in maximum temperature.
Thermal Result between PBGA and InFO-WLP
PBGA
InFO-WLP
Max. Tem = 81.5oC
Max. Tem = 90.5oC
Thermal resistant = 32.5oC/W
Thermal resistant = 28.0oC/W
3D eWLB – Horizontal and Vertical Interconnects for
Integration of Passive Components
M. Wojnowski1, G. Sommer1, K. Pressel2, G. Beer2
1Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany
E-mail: maciej.wojnowski@infineon.com
2Infineon Technologies AG, Wernerwerkstraße 2, 93049 Regensburg, Germany
IEEE/ECTC2013
Through
Encapsulant
Via (TEV)
Chip Mold
Compound
RDLs Chip
32
Through
Encapsulant
Via (TEV)
Chip Mold
Compound
RDLs Chip
3D IC Packaging: PoP
33
Through Encapsulant Via (TEV)
Laser Drilled
Through Encapsulant Via
(100 - 150µm)
Sputter the Ti/Cu
+ Cu plating 34
STMicroelectronics’ 3D eWLB
Chip 3
Chip 2 Chip 1
Chip 1 Chip 2
35
ASE’s Double Sided 3D FOWLP –
Package on Package (FOPOP)
Top Package
Bottom
Package
Chip
Chip Through Mold
Via
RDLs
RDLs
MC
MC
SEMICON West 2013 36
AMKOR’s Wafer-Level Fan-Out (WLFO) Package
Chip
Memory Chips Wire Bonds
Redistribution
Layers
Through Mold Vias Substrate Solder
Bump 3D Packaging, November 2012
37
STATSChipPac’s 3D IC Packaging
38
Technology
Ma
turi
ty
Basic/
Applied
R&D
Applied
R&D
Mass
Production
Commercia
-lization
Die
Stacking
with wire
bonds
Package
on
Package
(PoP)
Stacking
C2C, C2W,
W2W
Stacking
W2W
Stacking
Full swing production for memories.
Volume production for mobile
products.
Active applied R&D is
undertaken by Research
Institutes. TSV cost is the key. In
the phase of industrialization.
Still in upstream research,
technological challenges
such as KGD, yield & device
architecture and EDA are key
issues.
3D IC Packaging 3D IC Integration 3D Si Integration
3D Integration Technologies
Lau, IEEE-ECTC PDC , 2009
Don’t use TSV Use TSV technology
39
TSV
(Through-Silicon Via)
40
William Shockley (co-invented the transistor) filed a patent, “Semiconductive
Wafer and Method of Making the Same” on October 23, 1958 and was granted
the US patent (3,044,909) on July 17, 1962.
Deep Pits (Holes),
We call TSV today
TSV (Through-Silicon Via)
William Shockley
(1956 Nobel laureate)
41
Intel’s TSV (Through-Silicon Via) for the
Shortest Chip-to-Chip Interconnects
A four stack
wire-bonded
die package
Wirebonds are replaced by TSVs
Microbumps
Thin chips
Advantages:
Smaller form-
factor
Low power
consumption
Wider bandwidth
Better
performance
Lau, Reliability of 3D IC Interconnects, 2011
Wirebonds
Wire → TSV
42
43
3D IC Integration
Memory chip stacking
Wide I/O DRAM, Wide I/O 2, or
Hybrid Memory Cube (HMC)
High Bandwidth Memory (HBM)
3D IC Integration (The right thing to do!)
Said the 1965 Nobel Physics laureate, Richard
Feynman at the Gakushuin University (Tokyo) in
1985:
“Another direction of improvement (of computing
power) is to make physical machines three
dimensional instead of all on a surface of a chip
(2D). That can be done in stages instead of all at
once – you can have several layers and then add
many more layers as time goes on.”
Thin
Chip
Micro
Bumps
TSV
44
3D IC Integration (The right thing to do!)
Thin
Chip
Micro
Bumps
TSV
TSVs straight through the same memory chips to: enlarge the memory capacity
lower the power consumption
increase the bandwidth
lower the latency (enhance electrical performance)
reduce the form factor
will be the major applications of 3D IC Integration!
45
Underfill is needed between the active/passive TSV interposer and the organic substrate
TSV-less chips on
a device-less
wafer (interposer)
with TSVs
Underfill is
needed between
chips and the
interposer
Wide I/O Interface
(2.5D IC Integration)
Wide I/O DRAM
(Hybrid Memory Cube)
DRAM stacking with
TSVs on Logic
Controller with TSVs
Over molding the
DRAMs
Memory-Chip
Stacking
DRAM or NAND
Flash stacking
with TSVs on
organic substrate
Over molding the
DRAMs or NAND
Flash
Organic Package Substrate
PCB
Potential Applications of 3D IC Integration
46
47
Memory chip stacking
TSV
Micro
bump
Thin Chip
Wafer before back-grinding8-stack chips (50μm each) connected
with TSV and microbumps
720μm560μm
Samsung’s 3D Stacking with
TSV (Through Silicon Via)
48
16Gb Flash
memory
(8 x 2Gb)
560μm
The 64GB DDR4 DRAM module consists of 36 DDR4 DRAM chips,
each of which consists of four 4-gigabit (Gb) DDR4 DRAM dies.
Use Samsung’s 20nm process technology and 3D TSV packaging
technology.
Perform twice as fast as a module that uses wire bonding
packaging, while consuming approximately half the power.
Server Farm
Samsung Mass-Produces Industry's First
TSV-based DDR4 DRAM (August 27, 2014)
Samsung 49
Underfill is needed between the active/passive TSV interposer and the organic substrate
TSV-less chips on
a device-less
wafer (interposer)
with TSVs
Underfill is
needed between
chips and the
interposer
Wide I/O Interface
(2.5D IC Integration)
Wide I/O DRAM
(Hybrid Memory Cube)
DRAM stacking with
TSVs on Logic
Controller with TSVs
Over molding the
DRAMs
Memory-Chip
Stacking
DRAM or NAND
Flash stacking
with TSVs on
organic substrate
Over molding the
DRAMs or NAND
Flash
Organic Package Substrate
PCB
Potential Applications of 3D IC Integration
50
51
Hybrid Memory Cube
(HMC)
DRAMs
Logic
Controller
Organic Substrate
Over-Mold
Microbump
TSV
TSV
Underfill
Hybrid Memory Cube (HMC)
Hybrid Memory Cube (HMC) The HMC consortium already has 8 members:
Micron
Samsung
Altera
ARM
IBM
Open-Silicon
SK Hynix
Xilinx
The SPEC was published on April 2, 2013 and is primarily targeted at:
HPC (high performance computing)
Networking
Energy,
Wireless communications
Transportation
Security
High-end servers
DRAM Layers
(Memory cube)
Logic Controller
53 More than 120 adopters!
Each DRAM die is divided into 16 "cores" and then stacked. The logic base is at
the bottom, with 16 different logic segments, each segment controlling four (or
eight) DRAMs that sit on top. This type of memory architecture supports more
DRAM I/O pins and, therefore, more bandwidth (as high as 400GB/s). According to
the Hybrid Memory Cube Consortium, a single HMC can deliver more than 15X the
performance of a DDR3 module and consume 70% less energy per bit than DDR3.
Hybrid Memory Cube (HMC) Architecture
2000+ TSVs on each DRAM
54
55
56
DRAM Layers
(Memory cube)
Logic
Controller
Hybrid Memory Cube
Micron fabricate
the memory cube
Hybrid Memory Cube
IBM fabricate the
Logic Controller
DRAM Layers
(Memory cube)
Logic
Controller
57
Micron’s First HMC Sample Shipped
in the Last Week of September 2013
58
The hybrid memory cube is a 4-
DRAM (each one with 2000+
TSVs) on a logic controller
(which size is slightly larger
than the DRAMs) with TSVs
The hybrid memory cube is on
an organic package substrate.
The TSV-DRAM is ~50-μm thick.
The TSV-DRAM is with 20-μm
(tall) Cu pillar + solder cap.
The memory cube is assembled
one DRAM at a time with
thermal compression bonding.
The heat dissipation is from
10W to 20W.
TSV diameter ~ 5 to 6-μm.
Volume production will be in
next summer.
DRAM Stack
Package Substrate
ATX Power Supply
Connector
ATX Form
Factor
Stratix V FPGA 10/100/1000 Ethernet Connectors
Hybrid Memory
Cube (HMC)
Altera’s Stratix V FPGA with Micron HMC
Altera White Paper, “Addressing Next-Generation Memory
Requirements Using Altera FPGAs and HMC Technology”, Altera
Corporation, January 2014.
By providing equivalent bandwidth of
greater than eight (8) DDR4-2400 DIMMs
using a single HMC device.
59
5X the bandwidth vs.
GDDR5
Up to 16GB
One-third the footprint
Half the energy per bit
Managed memory stack
for optimal levels of
reliability, availability and
serviceability
Hybrid Memory Cube (HMC)
Intel’s “Knight’s Landing” with 8 HMC
Fabricated by Micron (2015 production)
Rik Myslewski, “Intel teams with Micron on next-gen many-core Xeon Phi with 3D DRAM Introduces new 'fundamental building block
of HPC systems' with Intel Omni Scale Fabric”, Posted in HPC, June 2014.
60
61
Fujitsu’s Tofu2 integrated Components: SPARC64 Xifx
and CPU Memory Board
Hybrid Memory
Cube (HMC)
32 + 2 core CPU
Three CPUs
3 x 8 Hybrid Memory Cubes (HMCs)
CPU Memory
Board
SPARC64 Xifx
Yoshida, “SPARC64 Xifx: Fujitsu’s next generation processor for HPC”,
Hot Chips: A Symposium on High Performance Chips, August 11,
2014.
62
Wide I/O DRAM
Memory
Cube with
TSVs
SoC with TSVs
C4 Bumps Solder Balls
Contact Grid
Target: 10mmx10mm Max.
The minimum determined by contact grid Targ
et:
1m
m
(a)
TSVs
TSVs
Face-up
Face-down
(b)
Wide I/O Single Date Rate
JEDEC Standard (JESD229), December 2011
63
Micron’s
Suggestion
64
Wide I/O 2
40µm
40µm
2880µm
200µm 120µm
1000µm
JEDEC Standard - Wide I/O 2
(JESD229-2, Wide I/O 2, August 29, 2014)
66
HIGH Bandwidth
Memory
(HBM)
Underfill is needed between the interposer and the organic substrate. Also, underfill
is needed between the interposer and the GPU/CPU and the memory cube
GPU/CPU/SoC
Organic Package Substrate
PCB PCB
TSV/RDL
Interposer HBM Interface
HBM DRAM
Optional
Base Chip
TSV
Hynix’s
HMC
High Bandwidth Memory (HBM) DRAM (Mainly for Graphic applications)
JEDEC Standard (JESD235), October 2013
HBM is designed to support bandwidth from 128GB/s to 256GB/s
67
Memory
Structure
Bandwidth
(GBps)
Voltage
(V)
Standard Applications
RDIMMs 153.6 1.2 DDR4 Servers, Cloud, data
center, etc.
Wide IO 2 68.3 1.1 JESD229-2 High-end
smartphones
HMC 160 to 320 1.2 HMC SPEC High-end servers,
networking, graphics,
HPC, FPGA, etc.
HBM 128 to 256
1.2 JESD235 High-end graphics,
networking, HPC, etc.
Memory Stacking with TSVs
69
Samsung’s Widcon
(wide I/O connection)
Technology
Top-View and Cross Section View of the PoP
(for Mobile DRAM and A8 Processor) inside iPhone 6 Plus
Elpida’s 1GB LPDDR3
(EDF8164A3PM-GD-F)
Apple’s application processor
(POXY99001) Not-to-scale
Package Substrate for LPDDR3
Package Substrate for A8 processor
Top-side of the bottom PoP (426-ball)
Application
Processor
Mobile Application Processor (AP) Chip Set
(AP + LPDDR3)
(PoP vs. 3D IC Integration)
Package Substrate for LPDDR3
Package Substrate for AP Package Substrate for AP Chip Set
Wide I/O DRAMs
AP
TSV
PoP 3D IC Integration
Samsung’s Widcon Technology
Very low profile
Widest memory bandwidth
Lower power consumption
Microbump
Wide I/O DRAMs
AP
Samsung’s Widcon Technology vs. PoP
Samsung’s Widcon Technology vs. PoP
74
2.5D IC Integration
Underfill is needed between the active/passive TSV interposer and the organic substrate
TSV-less chips on
a device-less
wafer (interposer)
with TSVs
Underfill is
needed between
chips and the
interposer
Wide I/O Interface
(2.5D IC Integration)
Wide I/O DRAM
(Hybrid Memory Cube)
DRAM stacking with
TSVs on Logic
Controller with TSVs
Over molding the
DRAMs
Memory-Chip
Stacking
DRAM or NAND
Flash stacking
with TSVs on
organic substrate
Over molding the
DRAMs or NAND
Flash
Organic Package Substrate
PCB
Potential Applications of 3D IC Integration
75
76
On October 21, 2013 Xilinx and TSMC have jointly announced production release
of the Virtex-7 HT family, what the pair claims is the industry's first heterogeneous
3D ICs in production.
The Xilinx Virtex-7 HT FPGAs feature up to sixteen, 28Gbps and seventy-two,
13.1Gbps transceivers. In addition to the Virtex-7 HT FPGAs, two other
homogeneous devices in the 3D IC family have been in volume production since
early 2013 – Virtex-7 2000T and Virtex-7 X1140T series.
4 FPGAs
TSV/RDL Interposer
Organic Package Substrate
2FPGAs
Transceiver TSV/RDL Interposer
Organic Package Substrate
http://press.xilinx.com/2013-10-20-Xilinx-and-TSMC-Reach-Volume-Production-on-all-28nm-CoWoS-based-All-Programmable-3D-IC-Families
4RDLs
TS
V
Package
Substrate
Build-up
Layers
Interposer
Interposer
PT
H
Chip Chip
Cu
Pillar Solder
C4 Bumps
Solder
Balls
Si
Devices (Cannot see)
Metal
Layers Metal
Contacts
Micro
Bump
The package substrate is at least (5-2-5)
RDLs: 0.4μm-pitch line width and spacing
Each FPGA has >50,000 μbumps on 45μm pitch
Interposer is supporting >200,000 μbumps
Core
Xilinx/TSMC’s 2.5D IC Integration with FPGA
77
Xilinx’s Passive Interposers with TSV and
RDL for Wide I/O Interface in FPGA Products
Lau, IEEE/ECTC2011 3D IC Integration PDC Lau
For better manufacturing
yield (to save cost), a very
large SoC has been sliced
into 4 smaller chips (2011)
(10,000+)
With 4 RDLs
78
Package
Substrate
TS
V
RDLs
Interposer
Build-up Layers
Cu
Pillar Solder
Chip Interposer
C4 Bumps
Solder
Balls
4RDLs on top of
the interposer
and there isn’t
any at the bottom
Altera/TSMC’s 2.5D IC Integration with FPGA
The package substrate is at least (6-2-6)
79
Chip 1 Chip 2
Underfill
Solder
Cu Pillar
TSV
UBM
Si
Interposer
RDLs
(Redistribution
layers)
RDLs for lateral
communications
Solder Bumps
Underfill
Solder Balls Not-to-scale
UBM
Package Substrate Build-up
Layers
2.5D IC Integration (Interposers)
80
81
Thus, passive TSV/RDL
interposers are for extremely fine-
pitch, high-I/O, high-performance,
and high-density semiconductor
IC applications.
Recent Advances in
Package substrates
Coreless Substrates
Build-Up Package Substrates
83
Coreless Substrates
84
Conventional Build-up
Package substrate
Coreless Package
substrate
Build-up Layers
Build-up Layers
Chip
Underfill Bump
Core Build-up Layers Build-up Layers
Underfil
l Bump
Chip
Filled Micro Via
Filled Micro Via
Comparison between the Substrate with Build-up
Layers and Coreless Substrate
Low Profile: Good for mobile products
Advantages Disadvantages Lower cost by eliminating the
core
Larger warpage
(because of low rigidity)
Better electrical performance
(good high-speed transmission
characteristic)
New manufacturing
infrastructure is necessary
Higher wiring ability
(by eliminating the core)
Easier to have laminate
chipping
Smaller form factor Poor solder joint yield
85
Coreless Substrates
86
Build-up
Package Substrates
87
Development of Organic Multi Chip Package
for High Performance Application
N. Shimizu, W. Kaneda, H. Arisaka, M. Koizumi, S. Sunohara, A. Rokugawa,
and T. Koyama
Shinko Electric Industries Co., Ltd.
36 Kita Owaribe Nagano-shi, 381-0014, Japan
81-26263-4585, noriyoshi_shimizu@shinko.cp.jp
10μm stack via
50μm build-
up via
40μm pad pitch
2μm line width/spacing
100μm PTH
Shinko’s 4+(2-2-3) Thin-Film on Build-up Layer Test
Vehicle: 2μm Cu trace and 40μm pitch pad
10μm stack via
11.8μm thick pad 25μm (dia.) Cu pad
10μm stack via
2μm line width
1.9μm spacing
2μm thick Cu
88
Build-up
layers
Thin-Film
layers
Core
Future Package Substrates
In general, a package substrate with 8-build-up-layer (4-2-4) and 20μm
line-width and spacing is more than adequate to support most of the
chips. Thus, interposers are not needed.
Also, in the past 3 years, Substrate Houses have been developing
package substrates with high build-up layers (5-2-5) and fine (12-15μm)
line-width and spacing.
Recently, Shinko’s thin-film layers on build-up layers can make 2μm line
width and spacing and 40μm pad pitch.
All these activities are keeping interposers away from volume
production, except for very niche (such as extremely high-performance,
high-density, and fine-pitch) applications.
89
90
Embedded
Interposer/Bridge
The advantages of this design are: (1) Low profile and low cost (2) Free to use any Moore’s law chips without TSVs (3) RDLs allow chip - to - chip short interconnect (4) TSVs can be used for powers, grounds, and some signals
(5) Very reliable (because the stress relief gap reduces the thermal expansion mismatch between the embedded TSV interposer and the organic substrate/PCB
Underfill between the chips and TSV interposer and the chips and organic substrate/PCB is necessary
TSV
Multi-chips on a TSV interposer Semi-Embedded on
a Substrate/PCB with Stress Relief Gap
Lau, J. H., S. T. Wu, and H. C. Chien, “Nonlinear Analyses of Semi-Embedded Through-Silicon Via (TSV) Interposer with Stress Relief Gap Under Thermal Operating and Environmental Conditions”, IEEE EuroSime Proceedings, Chapter 11: Thermo-Mechanical Issues in Microelectronics, Lisbon, Portugal, April 2012, pp. 1/6 – 6/6.
ITRI/Unimicron’s Packaging Substrate Having
Embedded Interposer and Fabrication Method
Thereof (US2013/0032390A1) (Publication Date: Feb. 7, 2013, Filed Date: Aug. 3, 2012)
Intel’s Bridge Interconnect with Air Gap in Package
Assembly (US 2014/0070380A1) (Publication Date: Mar. 13, 2014, Filed Date: Sept. 11, 2012)
Chip Chip Chip Solder
Bumps
Solder Balls
Substrate
RDL Via Bridge
Solder Bumps Bridge RDL
Intel’s Bridge Interconnect with Air Gap in Package
Assembly (US 2014/0070380A1) Intel Newsroom on Aug 27, 2014
(Publication Date: Mar. 13, 2014, Filed Date: Sept. 11, 2012)
Embedded Multi-die Interconnect Bridge (EMIB)
Air Gap
95
3D MEMS and IC
Integration
96
TSV
Rx die Tx die
TSV TSV
CAP CAP
CAP
Au
TSV
Avago’s FBAR MEMS Filter with TSV
97
(a) Cap Wafer
TSV TSV
TSV
TSV
TSV
TSV
ICP
ICP
(b) FBAR Wafer
Pad
Pad
Pad
Pad
Pad
Pad
ICP
ICP
Photo images of the FBAR hermetic package. (a) Cap wafer
with IC device, TSVs, internal connections, and cavity for the
FBAR. (b) FBAR wafer with FBAR, pads, internal connections,
and cavity for IC device
98
FBAR
300µm
Circuit
TSV
Au Pads
IC Cap Wafer
Circuit FBAR
IC Cap Wafer
TS
V
TS
V
Au Pads
FBAR Wafer
FBAR Wafer
Au
Top: IC cap wafer to FBAR wafer Au-Au bonding. (b) Cross section
SEM image of the bonded FBAR MEMS package with IC cap
99
3D CIS and IC
Integration
Light
Color Filter
Micro Lens
Transistors
and Metal
Wiring
Line of receiving surface
Si-Substrate
PD
100
Front-illuminated (FI) CIS. Some of the
lights are blocked (reflected) by the
transistors and metal wirings
Micro Lens
Color Filter
PD
Light
PD
Transistors
and Metal
Wiring
Color Filter
Micro Lens Line of receiving
surface Backside
Backside Line of receiving
surface
Si-substrate
Si-substrate
101
(TOP) Schematic of Back-illuminated (BI) CIS. (Bottom) Cross section SEM image of a BI-CIS
Conventional BI-CIS New Stacked BI-CIS
Pixels Pixels
Circuits
Circuits
Supporting
Substrate (Si)
Logic Process
Substrate (Si)
102
SONY’s BI-CIS: conventional vs. new 3D stacking
103
3D CIS pixel chip and logic IC integration
BI-CIS
Process
Technology
Logic
Process
Technology
On chip color filter and micro lens
CIS (Si)
CIS (Insulator)
Logic (Insulator)
Logic (Si)
50µm
W2W
Bonding Surface
104
CIS (insulator) wafer to logic (insulator) wafer bonding
105
TSV
CIS (Si)
Logic (Si)
On chip color filter and micro lens
TSVs connecting the CIS pixel chip and the
logic circuit chip
106
SUMMARY AND RECOMMENDATION (3D IC Integration)
TSVs straight through the same memory chips to: enlarge the memory capacity
lower the power consumption
increase the bandwidth
lower the latency (enhance electrical performance)
reduce the form factor
will be the major applications of 3D IC Integration!
Memory chip stacking with TSV has been in production for servers by
Samsung.
The Hybrid Memory Cube (HMC) will be used by Intel, Altera, Fujitsu,
etc. this year for high performance products!
The High Bandwidth Memory (HBM) will be used by Hynix, AMD, Nvidia,
etc. for graphic applications.
107
SUMMARY AND RECOMMENDATION (2.5D IC Integration - Interposers)
In general, interposers are for extremely high-I/O, high-performance,
high-density, and fine-pitch semiconductor IC applications.
In general, the build-up package substrates are more than adequate
to support the semiconductor IC chips in high-end smartphones
and an interposer is not necessary.
Thin-film RDLs on top of the build-up package substrate invented
by Shinko is the right way to go. The industry should strive to
commercialize it.
Try not to use the interposer unless the build-up package
substrates are not adequate to support the very high I/O, high-
performance, high-density, and fine-pitch chips. Now, with the thin-
film RDLs on top of the build-up package substrate, the high-
volume production of interposer will be pushed out even further.
108
SUMMARY AND RECOMMENDATION (3D IC Packaging)
3D IC Packaging such as
Stacked dies with wire bonding
PoP
have been and will be used for mobile
products such as smartphones and tablets.
3D Chip-to-Chip and Face-to-Face will soon
be used for mid-range performance
applications.
SUMMARY AND RECOMMENDATION (eWLP)
eWLP is expected to grow substantially in the next few
years.
Most of the OSATs (the top 6) are developing their eWLP
technologies.
eWLP package is just right for smaller size of chip.
eWLP package is just right for smartphones, tablets, and
wearables because it is low profile, light weight, and low
cost.
eWLP package cannot house very large chips (e.g.,
15mm x 15mm) like the PBGA package.
eWLP package size cannot be too big (e.g., 45mm x
45mm like the PBGA package.
109
ACKNOWLEDGEMENTS
The author would like to thank his
colleagues at IME, HKUST, ITRI, ASM
and throughout the packaging
community for their useful help,
strong support, and stimulating
discussions.
110
Thank You Very Much for Your
Attention!
111
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