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Problem Statement Operating Environment Intended Use and Users Assumptions and Limitations End Product Accomplishments Approaches Research Design Implementation Testing Resources and Schedules Closing Materials Presentation Outline
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PC Based Spectrum Analyzer
April 29, 2003
May03-10
Faculty Advisor: Dr. DJ Chen
Michael Cain
Paul Heil
Eric Rasmussen
Aung Thuya
Client: Teradyne Inc.
Phase III
The team would like to thank:• Teradyne• Steve Miller• Dr. Degang Chen
Acknowledgements
Problem Statement
Operating Environment
Intended Use and Users
Assumptions and Limitations
End Product
Accomplishments
Approaches
Research
Design
Implementation
Testing
Resources and Schedules
Closing Materials
Presentation Outline
List of Definitions
DAC – digital to analog converter
DC offset – DC voltage in an AC signal
FPGA – field programmable gate array
Spectrum analyzer – measures magnitude of signal harmonics
THD – total harmonic distortion
• 100MHz high gain, low noise, low distortion
• Programmable DC offset and frequency response calibration
Amplifier for PC Based Spectrum Analyzer
Problem Statement
DC — 1kHz +/- 5 volts 6, 20, 40, 60 +/- 10 volts 0.05 dB < - 105 dB 1.5 nV/rtHz
> 1kHz - 20 kHz +/- 5 volts 6, 20, 40, 60 +/- 10 volts 0.05 dB < - 95 dB 1.5 nV/rtHz
> 20kHz - 100kHz +/- 2.5 volts 6, 20, 40 +/- 5 volts 0.10 dB < -85 dB 2.5 nV/rtHz
> 100kHz - 1MHz +/- 2.5 volts 6, 20, 40 +/- 5 volts 0.10 dB < - 80 dB 3.5 nV/rtHz
> 1MHz - 10MHz +/- 2.5 volts 6, 20, 40 +/- 5 volts 0.10 dB < - 70 dB 3.5 nV/rtHz
> 10MHz - 20MHz +/- 2.5 volts 6, 20 +/- 5 volts 0.10 dB < -65 dB 3.5 nV/rtHz
> 20MHz - 50MHz +/- 1.0 volts 6, 20 +/- 2.0 volts 0.10 dB < -50 dB 5.0 nV/rtHz> 50MHz - 100MHz +/- 1.0 volts 6, 20 +/- 2.0 volts 0.10 dB < -40 dB 5.0 nV/rtHz
Input Total
Input Voltage Available Max OutputFreq
Response Harmonic
Frequency RangeGain
Settings Voltage Flatness Distortion Noise
Range (Volts) (dB) (Volts) (dB) (dB) (nV/rtHz)
Problem Statement (cont’d.)
Normal lab conditions
Low humidity, room temperature
Operating Environment
Intended Users and Uses
Users will be Teradyne test engineers
Use will be preamplifier for PC Based spectrum analyzer
Users
• Teradyne test engineers are familiar with the operation of a spectrum analyzer
Requirements
• Specifications are attainable
Financial Budget
•Teradyne will cover project costs
Assumptions
Hardware
• Noise and distortion trade-off
• Must have a stable configuration
Software
• Simulation software limitations
Technical Knowledge
• No experience with PC board fabrication
Limitations
The end product will consist of the following deliverables:
• Analog amplifier design with embedded digital controls
• Software for the embedded digital controls
• Design and user documentation
End Product
• Research – 100% completed
• Analog amplifier design – 100% completed
• Digital controls – 100% completed
• Software controls – 100% completed
• Simulations – 100% completed
• Fabrication – 0% completed
• Testing – 0% completed
Present Accomplishments
Amplifier Topology
• Low noise amplifier (LNA)
• Operational amplifier in resistive feedback
Approaches Considered and Used
DC Offset Correction
• Clocked ping-pong structure
• Offset voltage referral
• Successive approximation scheme
Approaches Considered and Used (cont’d.)
Frequency Response Calibration
• Automatic
• Manual
Approaches Considered and Used (cont’d.)
Project Definition Activities
• Project scope was changed to a paper design
• Occurred after design was submitted for fabrication
• Will be completed by future team
• Amplifier Topologies
• Operational Amplifiers
• DACs
• FPGAs
• Digital Potentiometers
• Comparators
Research Activities
Amplifier Design
Design Activities
Design Activities (cont’d.)
Design Activities (cont’d.)
DC offset correction
Design Activities (cont’d.)
Design Activities (cont’d.)
Frequency response calibration
Design Activities (cont’d.)
Implementation Activities
Implementation was not necessary
PSpice simulations for analog design
Verilog simulations for digital state machine
Testing Activities
Other Significant Activities
User manual
Estimated performance analysis
Design vault on CD
Resource Requirements
0
50
100
150
200
250
Research Schematic /Simulation
Finalization Testing
Aung
Eric
Paul
Mike
Personal Effort
Resource Requirements (cont’d.)
Item Team Hours Other Hours Cost
Board Fabrication 0 0 $0
Components 0 0 $0
Project Poster 10 0 $48
Total 10 0 $48
Total Cost
Project Schedule
ScheduleTask Name DurationDevelop Project Plan 5 days
Define Project Scope 5 days
Research 22 daysResearch op-amp topology 16 days
Research Calibration Techniques 16 daysDC Offset Correction 16 days
Signal Level Flatness 16 days
Project Website 3 daysDevelop Layout 1 day
Develop Content 1 day
Revise 2 days
Project Poster 12 daysDefine Poster Content 2 days
Develop Poster Content 3 days
Layout Poster 2 days
Create Poster 3 days
Revise Poster 2 days
Design Phase 135 daysAmplifier Design Complete 0 days
Top-Level Schematic 20 days
Run Spice simulation 12 days
Verify against design requirement 22 days
Digital Design 8 days
Write software code 10 days
Final Design Review 0 days
Testing Phase 13 daysExamine FPGA waveform 5 days
Verify against requirements 8 days
Final Presentation Preparation 24 days
Final Presntation 0 days
Paul Heil,Eric Rasmussen,Aung Thuya,Mike Cain
Eric Rasmussen,Aung Thuya
Paul Heil,Mike Cain
Paul HeilPaul HeilPaul Heil
12/8Eric Rasmussen
Eric Rasmussen,Aung Thuya
Paul Heil,Mike CainPaul Heil,Mike Cain
3/12
Paul Heil,Mike CainAll
All4/29
B M E B M E B M E B M E B M E B M E B M E B M E B M E B M E B3rd Quarter 4th Quarter 1st Quarter 2nd Quarter 3rd Quarter
• Schematic level implementation – fully met
• Simulations – fully met
• Fabrication – not attempted
• Testing – not attempted
Project Evaluation
• Only one will be fabricated for testing purposes
• Will be a part of Teradyne’s Integra J750
• Cost of J750 starts at $99,000
Commercialization
• Meet low noise requirement
• Make frequency response calibration automatic
• Fabricate board
• Complete testing
Recommendations for Future Work
• Set up weekly meetings with client and team
• Do not procrastinate
• Make sure design tools are adequate
• Do not be too optimistic with scheduling
• Do not be too elaborate with complicated designs
Lessons Learned
• Losing a team member
• No available times for meetings
• Parts ordered on time
• Sending design to fabrication on time
Risk and Risk Management
Closing Summary
Learned a lot about amplifier topologiesTeam skills improvedUseful information passed to next group
Questions?
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