Expanded “Cookbook” Instructions for the Teradyne

Integra J750 Test System Final Report

Team May 07-12

Client

ECpE Department

Faculty Advisor Dr. Weber

Team Members

Murwan Abdelbasir, EE Brent Hewitt-Borde, EE

Jonathan Brown, EE Paul Jennings, EE

Robert Stolpman, EE

REPORT DISCLAIMER NOTICE

DISCLAIMER: This document was developed as a part of the requirements of an electrical and computer engineering course at Iowa State University, Ames, Iowa. This document does not constitute a professional engineering design or a professional land surveying document. Although the information is intended to be accurate, the associated students, faculty, and Iowa State University make no claims, promises, or guarantees about the accuracy, completeness, quality, or adequacy of the information. The user of this document shall ensure that any such use does not violate any laws with regard to professional licensing and certification requirements. This use includes any work resulting from this student prepared document that is required to be under the responsible charge of a licensed engineer or surveyor. This document is copyrighted by the students who produced this document and the associated faculty advisors. No part may be reproduced without the written permission of the senior design course coordinator.

Date Submitted 05/02/2007

Contents

1 Introductory material 11.1 Executive summary . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Project requirements . . . . . . . . . . . . . . . . . . . 11.1.2 Actual project activities . . . . . . . . . . . . . . . . . 21.1.3 Final results . . . . . . . . . . . . . . . . . . . . . . . . 31.1.4 Recommendations for follow-on work . . . . . . . . . . 3

1.2 Acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Problem statement and solution . . . . . . . . . . . . . . . . . 4

1.3.1 Problem statement . . . . . . . . . . . . . . . . . . . . 41.3.2 Problem solution . . . . . . . . . . . . . . . . . . . . . 5

1.4 Operational environment . . . . . . . . . . . . . . . . . . . . . 51.5 Intended user and intended use . . . . . . . . . . . . . . . . . 7

1.5.1 Intended user . . . . . . . . . . . . . . . . . . . . . . . 71.5.2 Intended use . . . . . . . . . . . . . . . . . . . . . . . . 7

1.6 Assumptions and limitations . . . . . . . . . . . . . . . . . . . 71.6.1 Assumptions . . . . . . . . . . . . . . . . . . . . . . . . 71.6.2 Limitations . . . . . . . . . . . . . . . . . . . . . . . . 9

1.7 Expected end-product and other deliverables . . . . . . . . . . 9

2 Approach and product design results 102.1 Approach used . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.1 Functional requirements . . . . . . . . . . . . . . . . . 102.1.2 Design constraints . . . . . . . . . . . . . . . . . . . . 112.1.3 Technical approach considerations and results . . . . . 112.1.4 Testing approach considerations . . . . . . . . . . . . . 14

2.2 Detailed design . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.1 Overview of the project design . . . . . . . . . . . . . . 142.2.2 IG-XL and Teradyne J750 functionality . . . . . . . . . 152.2.3 Device selection . . . . . . . . . . . . . . . . . . . . . . 19

2.3 Implementation process . . . . . . . . . . . . . . . . . . . . . . 222.3.1 Channel mapping and device mating . . . . . . . . . . 222.3.2 Template creation . . . . . . . . . . . . . . . . . . . . . 232.3.3 Cookbook maintenance and improvements . . . . . . . 23

2.4 End-product testing . . . . . . . . . . . . . . . . . . . . . . . 232.5 Project end results . . . . . . . . . . . . . . . . . . . . . . . . 26

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3 Resources and schedule 263.1 Personal effort requirements . . . . . . . . . . . . . . . . . . . 263.2 Other resource requirements . . . . . . . . . . . . . . . . . . . 273.3 Financial requirements . . . . . . . . . . . . . . . . . . . . . . 303.4 Project schedule . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4 Closure materials 354.1 Project evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.1 Project milestones for evaluation . . . . . . . . . . . . 354.1.2 Evaluation criteria . . . . . . . . . . . . . . . . . . . . 394.1.3 Project evaluation . . . . . . . . . . . . . . . . . . . . 39

4.2 Commercialization . . . . . . . . . . . . . . . . . . . . . . . . 424.2.1 Commercialization cost . . . . . . . . . . . . . . . . . . 424.2.2 Potential market . . . . . . . . . . . . . . . . . . . . . 42

4.3 Additional work . . . . . . . . . . . . . . . . . . . . . . . . . . 434.3.1 Ongoing Teradyne project . . . . . . . . . . . . . . . . 434.3.2 Additional sections for cookbook . . . . . . . . . . . . 43

4.4 Lessons learned . . . . . . . . . . . . . . . . . . . . . . . . . . 434.4.1 What went well . . . . . . . . . . . . . . . . . . . . . . 434.4.2 What did not go well . . . . . . . . . . . . . . . . . . . 444.4.3 Technical knowledge gained . . . . . . . . . . . . . . . 44

4.5 Non-technical knowledge gained . . . . . . . . . . . . . . . . . 454.6 Risk management . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.6.1 Predicted risks . . . . . . . . . . . . . . . . . . . . . . 454.6.2 Identified risks encountered . . . . . . . . . . . . . . . 464.6.3 Unidentified risks encountered . . . . . . . . . . . . . . 464.6.4 Changes in risk management as a result of unantici-

pated risks . . . . . . . . . . . . . . . . . . . . . . . . . 474.7 Project team information . . . . . . . . . . . . . . . . . . . . . 47

4.7.1 Client information . . . . . . . . . . . . . . . . . . . . 474.7.2 Faculty advisor information . . . . . . . . . . . . . . . 474.7.3 Team members' information . . . . . . . . . . . . . . . 48

4.8 Closing summary . . . . . . . . . . . . . . . . . . . . . . . . . 484.9 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

A Data sheet for AD823 50

B Data sheet for OP37 50

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C Data sheet for AD7892 50

D Data sheet for AD7470 50

E Data sheet for AD5440/AD5447 50

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List of Figures

1 Teradyne J750 tester . . . . . . . . . . . . . . . . . . . . . . . 12 ESD wristband . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Lock/Unlock switch on J750 tester . . . . . . . . . . . . . . . 64 ZIF DIP Socket . . . . . . . . . . . . . . . . . . . . . . . . . . 125 TSSOP to DIP socket converter . . . . . . . . . . . . . . . . . 136 Test procedures dialog . . . . . . . . . . . . . . . . . . . . . . 177 Test procedure flow chart dialog . . . . . . . . . . . . . . . . . 188 Teradyne pinout chart . . . . . . . . . . . . . . . . . . . . . . 249 Final TSSOP to ZIF converter . . . . . . . . . . . . . . . . . . 2510 Problem definition Gannt chart . . . . . . . . . . . . . . . . . 3111 Technology selection Gannt chart . . . . . . . . . . . . . . . . 3212 Project reporting Gannt chart . . . . . . . . . . . . . . . . . . 3313 End project deliverables Gannt chart . . . . . . . . . . . . . . 34

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List of Tables

1 Total personal efforts . . . . . . . . . . . . . . . . . . . . . . . 282 Estimated additional resources . . . . . . . . . . . . . . . . . . 293 Revised estimated additional resources . . . . . . . . . . . . . 294 Final revised project costs . . . . . . . . . . . . . . . . . . . . 305 Milestones and grading weights . . . . . . . . . . . . . . . . . 356 Estimated design evaluation functionality chart . . . . . . . . 407 Milestone completion scoring rationale . . . . . . . . . . . . . 408 Project evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 419 Commercialization Cost . . . . . . . . . . . . . . . . . . . . . 4210 Contact information . . . . . . . . . . . . . . . . . . . . . . . 48

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List of DefinitionsADC - Analog-to-digital converterASIO - Analog signal I/O boardCSG - Computer Support GroupDAC - Digital-to-analog converterDIB - Device interface boardDSIO - Digital signal I/O boardDSP - Digital signal processingDUT - Device under testECpE - Electrical and computer engineeringESD - Electrostatic dischargeGND GroundI/O - Input and outputIG-XL - A windows based software that utilizes Microsoft Excel and VisualBasic to develop programs for the Teradyne J750IMD - Inter-modulation distortionISU - Iowa State UniversityKbps Kilo-bits per second or 1000 bits per second.Mbps Mega-bits per second or 1000000 bits per second.MSPS Mega-samples per secondMHz Mega-HertzMSO - Mixed-signal option testing that uses analog and digital simultane-ouslyPSI - Pounds per square inch, a unit of measurement for pressure exertedon a known surface areaPLCC Plastic leadless chip carrierSNR - Signal to noise ratioTDR - Time domain reflectometryTSSOP Thin shrink small outline packageTeradyne J750 - A tester donated to ISU that is used for testing printedcircuit boards and integrated circuits as shown in the figure below.ZIF Zero insertion force

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Figure 1: Teradyne J750 tester

1 Introductory material

This section introduces the project, abstract, acknowledgements, problemstatement and solution, operating environment, intended users and uses, lim-itations and assumptions, expected end product and other deliverables.

1.1 Executive summary

This section gives a general overview of the project requirements, plans, andactivities.

1.1.1 Project requirements

The scope of this project is to expand upon previous Teradyne J750 cook-books of instructions, which are in a manual format for the ISU Departmentof Electrical and Computer Engineering. At present the current cookbook in-struction set is missing a mixed-signal option section and the present projectteam members fills this gap by reviewing, citing previous cookbooks to meetthe mixed-signal testing requirements requested by the ECpE departmentto create an extended cookbook. The team will setup and test a ten bit

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ADC, a twelve bit ADC, a ten bit DAC, a twelve bit DAC, and a 10 MHzor faster op-amp using the Teradyne J750 and document each scenario forsupport. The test scenarios and documentation have been used to create thismixed-signal cookbook.

1.1.2 Actual project activities

The project activities are outlined as follows for both semesters below.

Fall 2006:

• Problem Definition (completed)

• MSO labs with vocoder chip (completed)

• IG-XL software code development (not completed)

• Technology Selection (completed)

• Project Reporting (completed)

• Weekly Email Repots, Website Updates (completed)

• Project Plan Development, Design Report Development (completed)

Spring 2007:

• IG-XL code development for DAC (at present, de-bugging code)

• IG-XL code development for ADC (in-progress)

• IG-XL code development for 100 MHz Op-amp (in-progress)

• Poster (competed)

• Pin and channel maps for ADC's and DAC's (completed)

• Pin and channel map for 100 MHz op-amp (in-progress)

• DAC, ADC testing (in- progress)

• Overall project documentation (in-progress)

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1.1.3 Final results

The final results are the fulfillment of the requirements in terms of documen-tation that has been turned in to the senior design co-coordinator. The pinand channel mapping for the ADC's and DAC's has also been completedand documented. The DIB socket converter interface has be made for theADC and DAC. At present the DAC is mounted and undergoing test debug-ging. The project at present is stalled due to IG-XL licensing error that haslocked the software disabling any other code development. The issue beforethe present IG-XL issue was a bad circuit breaker from since last semesterwhich caused the computer motherboard to be replaced. At present a newair-conditioner was installed enabling testing at the required temperature toresume, once the computer is fully operational.

1.1.4 Recommendations for follow-on work

After consultation during our team meetings with Dr. Weber, Dr. Smith,and members of the Cyclone team at Teradyne, it was proposed to turn theTeradyne cookbook project into an ongoing project. This would take theform of a phase with outlined tasks with additional support in the form oftraining sessions for using the tester and IG-XL code development, to possiblyhave one or two students certified to do software and hardware upgrades tothe tester as well as the IG-XL software package.

One important recommendation the team would strongly want to seeimplemented is for the J750 tester and its supporting equipment to be movedto a reliable room of Dr. Weber's choice so as to prevent any damage due tothe ongoing construction and upgrade to the ECpE building which will enteranother phase very soon. At present, the construction has caused powerinterruptions, computer hardware failure and disruption to the operationalenvironment within the Teradyne lab.

1.2 Acknowledgement

The team members extend great appreciation and would like to this oppor-tunity to thank Dr. Robert Weber for the advisory role and being verycommitted to the team and this project through out its duration. The teamalso would like to acknowledge and thank Jason Boyd for the training andon site supervision for the first scheduled month after the initial meeting

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with Dr. Weber of the project as well as the Department of Electrical andComputer Engineering at Iowa State for use of the Teradyne J750 and theTeradyne Company for the J750 tester. Also the team would like to thankalso Dr. Smith for his assistance and guidance as well as the Cyclone teamat Teradyne, whose support is greatly appreciated. Lastly, the team wouldlike to acknowledge the previous senior design teams for the documentationthat is left in the lab to be used as a source of reference on this project.

1.3 Problem statement and solution

This section gives a general outline and an overview of the proposed problemsolution.

1.3.1 Problem statement

The success of any product for the market after the planning and fabrica-tion phases relies heavily on some form of testing and experimentation. Theproduct must undergo some form of rigorous tests for different scenarios be-fore release to ensure that it is functioning according to specifications andthe client expectations. Universities and colleges which are research orientedprovide a cost effective way of testing such products for companies and in-vestors.

Iowa State is no exception and with the donation of the Teradyne IntegraJ750 tester from the Teradyne Corporation, the Iowa State Department ofElectrical and Computer Engineering has the opportunity to achieve this costeffective way of testing and building devices.

This is important because the research conducted can create new methodsof testing and also increase or build upon the productivity of the equipmentdonated and the devices under test. The associated cost of obtaining afully functional tester is beyond the university's operating budget and thepresent Teradyne J750 does not have the capability at present to performmixed-signal testing.

The two past groups have already designed, tested and implemented dig-ital circuits as well as a wireless circuit for testing along with the originalfunction of the J750 to test analog circuits. The present team must test theserequired components of ten- and twelve-bit ADC's and DAC's as well as a10 MHz or greater op-amp via the Teradyne with the specific hardware andsoftware configuration to have the capability to test mixed-signal IC circuits.

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The results are to be included as another phase onto the existing Teradynecookbooks that past senior design groups have produced.

1.3.2 Problem solution

The team has created a way to interface the required mixed-signal com-ponents with the Teradyne J750 via a socket and software test templateswritten using the IG-XL software that is compatible with the three differenttypes of devices required to test: a DAC, ADC, and a high speed operationalamplifier. The testing procedures along with the results will then be broughttogether in one concise package to be added on to the current Teradyne J750cookbook and will show users how to setup and test mixed-signal devicesusing the machine with the documented support.

1.4 Operational environment

Operation of the circuits has to occur indoors within a temperature rangeof 27◦C to 33◦C because of the sensitivity to temperature of the TeradyneJ750. Since the equipment itself is worth over $500,000 US dollars, a preven-tative process needs to be followed before operating the machine. Thus, theDepartment of Electrical and Computer Engineering will only operate andtest the various circuits for mixed-signal in a temperature regulated room.

The presence of a human body presents the opportunity for the distribu-tion of charge and voltage to any form of circuitry (i.e. ESD electrostaticdischarge), which can have an adverse affect on the equipment, perhaps caus-ing permanent damage. It is required that every person that is present in theroom who is in direct contact with the Teradyne J750 wear ESD wrist bandswhen using the tester. This ESD wrist band is shown below in Figure 2.

The vacuum pump and the lock portion of the lock/unlock switch areto be activated as shown in Figure 3 below before any form of testing canbe done. The purpose of the vacuum pump is to hold the DIB and thetester surface together firmly with approximately four PSI of pressure. Thepressure ensures that both interfaces are locked together so the other devicesthat need to be mounted are held in a stable position for the process oftesting.

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Figure 2: ESD wristband

Figure 3: Lock/Unlock switch on J750 tester

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1.5 Intended user and intended use

This section defines who the intended users are and what the intended usesare for the project.

1.5.1 Intended user

The potential users for this project will be any student or faculty memberof the Department of Electrical and Computer Engineering who requires thetesting of the mixed-signal option devices. It can also be used as a laboratoryexperiment to re-enforce the concepts learned in various ECpE classes thatrelate to mixed-signal theory and industry applications.

The user must possess knowledge of IC circuits, digital logic, signals,and digital communication; and have an understanding of the operation theTeradyne J750 for conducting tests. The user must be able to synchronizethe frequency that controls clock cycle along with the rest of setup and beable to follow the reference manual developed by the design team.

1.5.2 Intended use

The intended use of the project is to allow mixed-signal testing using theTeradyne J750 tester and to develop and test various scenarios for two differ-ent ADC's and DAC's (one ten-bit and one twelve-bit in both instances) aswell as for a 10 MHz or greater op-amp. This mixed-signal option providesan innovative approach to these microcontroller mixed-signal devices simi-lar to the present industry testing capabilities and using the IG-XL softwareprovided is able to efficiently record the results from the tests so as to achievethe goals of the Electrical and Computer Engineering department.

1.6 Assumptions and limitations

This section outlines the expected assumptions and limitations for the end-product where any additional assumptions and limitations to be includedprior to team or advisor consultations about specifics of the project.

1.6.1 Assumptions

This section provides the relevant details of the user and system assumptions.

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1.6.1.1 User assumptions This section outlines the assumptions aboutthe intended user:

• Willing and can follow basic instructions during training to use theequipment so as to follow all necessary safety precautions.

• User has read and understood the Teradyne J750 instructional manual.

• A suitable background in electrical and/or computer engineering.

• Previous experience in circuit testing with the Teradyne J750.

• User is knowledgeable of the electrical hazards the equipment can dis-tribute and what the user is at risk of transferring to the machine.

• User treats and operates all equipment in a timely and professionalmanner.

• User is familiar with technical English as all documentation at presentis/will be written in English.

• User is knowledge about mixed-signal operation and concepts.

• User is able to tolerate the noise caused by the vacuum pumps.

1.6.1.2 System assumptions This section outlines the assumptions aboutthe overall system:

• All instruments are operational and calibrated.

• No expired licenses or copyright material that the team does not havepermission to use.

• Present IG-XL codes can be modified for the required objectives.

• The vacuum pumps are always operational.

• Testing of DUT's are limited to one at a time.

• Teradyne J750 can interface with the IC devices to be tested.

• Reliable building power supply.

• No computer hardware failure.

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1.6.2 Limitations

This section will provide details of the limitations identified with the project:

• The Teradyne J750 is sensitive to temperature fluctuations and mustoperate within ± 3◦C of the calibrated temperature. The current sys-tem is set for 30◦C.

• The IG-XL software shall be used in writing the test code for the Ter-adyne J750.

• User has undergone some form of industry standard training as pro-vided by Teradyne including the various training modules that are usedas reference materials.

• Modules on MSO are lengthy and can be regarded as a combinationof DSP, high speed testing, communication and signals, VLSI coursestaught presently at ISU all packed into one.

• Present IG-XL code exists for a 16-bit vocoder which is a combinedADC and DAC and no code exists for the required single ADC, DAC,and op-amp chips.

• Computer software issues with licensing for updated IG-XL software.

• Computer hardware problems issues due to failing components.

• Circuit breaker problems within the lab.

• Slow response time from CSG at ISU which introduces operationaldelay for testing the devices.

1.7 Expected end-product and other deliverables

This section outlines the details of the expected end-product and other deliv-erables. The team expects to meet some of the specific tasks required in theform of the Expanded Cookbook Instructions for the Teradyne Integra J750Test System. The system developed to test the chosen devices are presentlynot on schedule and a demonstration test of one device will be done via thedeveloped cookbook for future users to test.

At the conclusion of the spring 2007 semester, this project will produce:

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• An expanded Teradyne J750 cookbook which documents mixed-signalIC circuits.

• A demo test of the finished 10-bit and 12-bit DAC device using theTeradyne J750.

If the present computer software licensing issue is resolved this week, the10-bit and 12-bit ADC will also be added to the demo test.

2 Approach and product design results

The following section provides a detailed description of the end product de-sign, approach and design results.

2.1 Approach used

The following section contains details pertaining to the design objective,functional requirements, design constraints, technical approach considera-tions and results, and testing approach considerations.

2.1.1 Functional requirements

The following section describes the functional requirements of the end prod-uct.

• The cookbook will be written on a level that the uninformed test en-gineer can understand

• The testing instructions will address two ADCs, two DACs, and anOp-amp faster than 10 MHz.

• Only one DUT will be tested at a time.

• A test program will be developed for each of the devices using IG-XLand will allow new devices of similar constraints to be added.

• Upon successful testing and mating of the devices a cookbook will bemade to allow future users to test these devices.

• If the project fails, proper documentation will be provided such thatone can look over potential problems and issues.

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2.1.2 Design constraints

The following section describes the design constraints for the end product.

• Limited to one software type on the Teradyne J750. The Teradyne J750uses IG-XL, which is essentially a Visual Basic and Excel platform. Theteam is limited to drawing user interfaces only in Basic.

• The operating conditions are limited to 30◦C ± 3◦C. As per the speci-fication of the operating temperature, the lab temperature will be heldbetween 27◦C and 33◦C.

• The budget for the project is limited to $200.00.

• Since the cost of a new daughterboard is beyond the budget of thisproject, all the devices must fit in the 24-pin PDIP or 28-pin PLCCsockets currently available.

• The size of the daughterboard makes operation above 100 MHz highlysusceptible to capacitance and other transmission line effects.

• The Teradyne lab is only accessible by selected faculty members andstudents.

• Due to department rules and regulations, the team will only be ableto provide this product to selected faculty members and students whohave access to the Teradyne lab in 2129 Coover Hall.

• The user is aware of the Teradyne J750 and has used it prior to usingthis product. Also, the user will observe ESD precautions around theTeradyne J750 tester.

2.1.3 Technical approach considerations and results

The following section presents several possible technological alternatives ana-lyzed during the design of this system along with their respective advantagesand disadvantages. In addition to this, the following section presents thetechnology selected for the final design as well as the technology used anddevices constructed by the May07 team.

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Figure 4: ZIF DIP Socket

2.1.3.1 DIB mating The team has a daughter board with a 24-pin DIPsocket already wired in from a previous year's senior design team (Fig-ure 4). Additionally, there is a daughter board that was included with Ter-adyne's Mixed-Signal Option (MSO) training program outfitted with two28-pin PLCC sockets.

These daughter boards are used to mate the device under test to the DIB.Because of time and cost constraints, it was preferable to find a solutionusing the above devices. Listed below are some of the major advantages anddisadvantages of using the current daughter boards.

• The chips would be more expensive. This could become costly if a goodnumber of them burn out during tests.

• A great deal of time would be saved since there is no need for a newdaughter board or interface.

• One of the ZIF sockets is a 24-pin DIP. This configuration limits thechips to a maximum sampling rate of 700 MSBS, which might maketesting a slower process.

• The 28-pin PLCC socket enables much faster sampling rates, but mostof the devices in this package are obsolete, hard to obtain, and func-tionally limited.

• If a chip burns out it would be very easy to replace, thus saving time.

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If the package were not considered, there would be a very wide varietyof devices available for test. This would include devices with much fastersampling times and many other unique options. There were three mainoptions for making the device compatible with the ZIF:

Make a new daughter board Making a new daughter board wouldhave allowed much more flexibility in device selection. It would also haverequired a decent amount of time to assemble and would have cost signifi-cantly more than any of the other options. However, it is by far the cleanestand most durable choice.

Create a printed circuit board that mates with the ZIF De-pending on the design of the PCB it could have been very time consuming,but would have been cheaper than using a socket converter. De-solderingand re-soldering burned-out chips would have been a slow and potentiallydestructive process. However, a socket could have been used on the PCB,making switching chips easy. This option would not work with high-speeddevices because of design and manufacturing considerations for high-speedPCB's. There would have been almost absolute freedom in the choice ofdevices. This solution would not have worked with the PLCC sockets.

Use a socket converter The socket converter was the fast and easysolution. The expense was still within the team's budget and was bothcheaper than creating a new daughter board and less time consuming thancreating a new interface.

Figure 5: TSSOP to DIP socket converter

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A 24-pin TSSOP to DIP converter (Figure 5) was selected because almostall of the required devices were found in the 24-pin TSSOP package, thussimplifying testing and reducing the overall cost of the project. The twoop-amps that were found were compatible with the ZIF socket currentlyattached to a daughter board and the ADCs and DACs were all found in24-pin TSSOP packages. The only 24-pin TSSOP converter that could befound would only mate with a 600 mil ZIF socket and as a result, anotherZIF socket was purchased and installed on the double wide daughter board.

2.1.4 Testing approach considerations

The testing plan consisted of two different approaches. The ADC and DACcircuits were to be tested for simple signal conversion with single- and multi-tone signals. Additionally, additional tests were to be done for linearity.The results were to be compared to the information given on the data sheet.The op-amps were also to be tested against various statistics given on thedata sheet, including but not limited to the -3dB bandwidth, the outputsaturation voltage, and transient response.

Upon completion of the expanded cookbook, its effectiveness was to betested by allowing inexperienced undergraduate students to follow it to andperform a test on one of the devices. After this proof of usability, Dr. Weberwas to follow the cookbook and determine the effectiveness of the cookbook.The tests were all to be conducted in the Teradyne lab in Coover Hall.

2.2 Detailed design

The detailed design section of this report features a thorough description ofthe design of the IG-XL parameters, the DIB connections, and the deliverabledocumentation.

2.2.1 Overview of the project design

As previously stated, the purpose of this project was to create an expandedcookbook suitable for mixed signal testing, and to provide test scenariosand documentation for several common mixed signal devices. In order toaccomplish this, several specific design concepts were considered:

• IG-XL and Teradyne J750 functionality

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• Device selection

– Op-amp

– ADC

– DAC

• Deliverable documentation

2.2.2 IG-XL and Teradyne J750 functionality

The IG-XL software is used to issue input and output commands to theTeradyne J750, in addition to providing signal generation and processingfunctions. The entire process is complicated but can be broken down into aset of simpler procedures.

2.2.2.1 Channel and pin mapping Each of the pins on the DUT mustfirst be entered into the IG-XL software via the pin map worksheet. Eachpin must be given a name and assigned a type such as I/O, Analog, GND,or Power. This information can be found on the data sheet for each device.Descriptions of the pin types can be found in the Teradyne documentation.

Next, each pin must be mapped to the channel to which it is connectedso that IG-XL can send or receive the appropriate data. The correct channelfor a given pin is entirely dependent on the design of the daughterboard andthe way the DUT connects to it.

2.2.2.2 Specification sheets Each IG-XL program must have three dif-ferent specification sheets: global, DC, and AC. Each sheet declares variableswhich can be used throughout the program. The global spec sheet is gener-ally universal between devices and provides default voltage, current, and risetime values. The DC and AC spec sheets provide more device specific poweroutput and timing variables, respectively. The values for these specificationscan be found on the data sheet for each device.

2.2.2.3 Level sheets This sheet contains the device pin levels to be usedby the tester during test execution. Each pin has a set of parameters specifiedby the pin type, and each of these parameters can be set in the levels sheet.Again, this information can be found on the data sheet for each device.

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2.2.2.4 Time sets The time set worksheet is used to define the timingand edge set information, which is generally used for the clock signal gen-eration. Multiple sets can be defined, and each set has numerous optionsfor specifying the input and output timing for digital signals, including thetesting window and the clock behavior.

2.2.2.5 Patterns The pattern file is a complex set of instructions whichtells the Teradyne J750 to stimulate the digital control and interface pins andmonitor the response. In simple digital circuits, this essentially provides thebit sequence to be sent to the DUT given a previously defined time set. Inmixed signal operation, however, additional steps must be taken to properlytrigger and clock the signals.

Additionally, the pattern file controls the input and output shift registerrequired to test serial devices. The pattern file can be written either usinga text editor and the pattern compiler or the pattern tool, which provides agraphical interface and spreadsheet based construction capabilities.

2.2.2.6 Test instances The test instance worksheet (Figure 6) is usedto define and adapt specific tests which will be applied to the DUT. Theseinstances are generally templates created by Teradyne to perform specifictasks, or user defined procedures which are elaborated upon in the subsequentsection. The parameters of each test are specified in the instance editor(Figure 7).

2.2.2.7 Procedures Mixed signal testing typically requires the creationof a test procedure which is defined on the test procedure worksheet. Creat-ing a new procedure opens the test procedure development environment, agraphical interface wherein specific test elements can be strung together tocreate a functional instance (Figure 7).

Each of these elements has a variety of parameters which can be definedas a constant or a variable. Any unspecified variables will become inputparameters on the test instance editor when the procedure is completed.Each procedure must include the following elements in order: levels andtiming, pattern start, utility bits, interpose, pattern control, pattern results,and limits.

One of the more important test elements is DSPprocedure, which pro-cesses the captured signal and displays the results to the user. Several differ-

16

Figure 6: Test procedures dialog

17

Figure 7: Test procedure flow chart dialog

18

ent procedures are available, most notably ”ProcessWaveLim” which displaysthe both the generated spectrum and the captured signal. Additional proce-dures exist for various linearity displays.

2.2.2.8 Flow table sheet The final step in creating the IG-XL programis the flow table, which provides a simple way to create, debug, and maintainthe flow portion of the program. The flow table is used to execute instances,process the results, create conditional flows dependent on previous instances,and run the program stepwise for debug purposes.

2.2.3 Device selection

A total of six devices were selected for testing. These devices will supplementthe old cookbook by giving it mixed signal testing capabilities. The types ofmixed signal devices the team chose were:

• Two different 10- to 12-bit ADCs

• Two different 10- to 12-bit DACs

• Two different 10 MHz or greater op-amps

All of these parts were obtained as free samples, allowing the budget tobe spent on adaptors. The package type, sampling rate, speed of the de-vice, and overall functionality were the key factors taken into considerationwhen choosing devices. A brief summary of each device is included below.Datasheets for all of the devices are also included in the appendices, whichwill provide all of the device specifications and any extra information notincluded in the summaries. All of the devices selected are made by AnalogDevices. This single vendor option was chosen in order to keep the orderprocess simple, and because Analog Devices has a good reputation for deliv-ery of circuit packages and samples within three days with no extra shippingcharges.

2.2.3.1 Operational amplifiers The purpose of the operational ampli-fiers is to test the Teradyne system using a device which operates in ACmode at a frequency greater than 10 MHz. The two op-amps chosen areboth available in a DIP package and are fairly inexpensive. Because of theDIP package, these parts are supported by the preexisting daughter boards.The two models chosen for the project were the AD823 and the OP37.

19

AD823 Possessing very good AC and DC characteristics and the abil-ity to drive a very wide variety of loads, this device is an excellent all-aroundamplifier. It was chosen because an amp with such a wide range of applica-tions would be great to test and, since it can function in a wide variety ofsituations, it should simplify the process for testing other amplifiers in thefuture. Some key characteristics of this AD823 device are:

• The AD823 is a dual package, meaning it houses two amplifiers.

• It is a 16 MHz rail-to-rail FET amplifier.

• The device comes in an 8 lead PDIP package.

• The cost per package is $2.63 and free samples are available.

• It also can operate from a single or dual power supply.

• Direct loads drive capability of 500 pF.

OP37 An op-amp that operates at higher speeds and has very low noisecharacteristics such as this one should add an extra degree of challenge totesting. Combined with the AD823 amp it will allow users of the cookbookto be able to test an even larger variety of devices.

• Optimized for circuits gains higher than 5.

• Has a 2.7 Hz noise corner frequency.

• Has a 63 MHz gain bandwidth.

• Has a very high open loop gain of 1.8 million.

• Comes in 8-pin hermetic and epoxy mini DIP packages.

Some other devices considered but not chosen were the AD745 and theAD827. The AD745 was originally planned to be used, but was it was discov-ered that the PDIP package was discontinued. The AD827 was not chosenbecause it does not provide as good a variety as the other two devices. How-ever it would make an excellent backup device or a first choice for futureteams or other testing projects.

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2.2.3.2 Analog-to-digital converters Two different ADCs were cho-sen to be tested using the Teradyne J750. Since the requirements called for10- to 12-bit precision, one 10-bit ADC and one 12-bit ADC were chosen.One device has a parallel output while the other can be configured for eitherserial or parallel output. This could allow the cookbook to be more versatileand ultimately more useful. The two models chosen for the project were theAD7892 and the AD7470.

AD7892 A 12-bit ADC with an output that can be selected to beparallel or serial was chosen because of its wide versatility.

• Runs off of a single 5-volt supply.

• The AD7892-1 and AD7892-2 have sampling rates of 500 KSPS andthe AD7892-3 has a sampling rate of 600 KSPS.

• Has a conversion time of 1.47us.

• Has a signal to noise ratio of 70 dB.

• Is available in a 24 lead PDIP package at the cost of $15.45 per device.

AD7470 This chip has a 10-bit parallel output and was chosen to com-plement the AD7892 and to give a more comprehensive ADC section in thecookbook.

• Has a sampling rate of 1.75 MSPS.

• Uses a single 2.7 volt to 5.25 volt power supply.

• Comes in the 24-lead TSSOP package at the cost of $3.53 per device.

• Has a wide input bandwidth and no pipeline delay.

There was a very wide array of ADCs available for use, so future teamsor other projects should not have any problem finding alternative devices ifnecessary. In order for use to use the AD7470 the team created an adapterthat goes from 24-lead TSSOP to 24-pin DIP.

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2.2.3.3 Digital to analog converters The device requirements for theDACs are very similar to that of the ADCs. One 10-bit and one 12-bit DACwere chosen, both with parallel inputs. The two devices chosen for test werethe AD5440 and AD5447.

AD5440 This package has dual 10-bit high bandwidth multiplying DACswith a parallel interface. It was chosen because it is the only 10-bit DACavailable from the chosen parts vendor that meets the project requirements,including the 24-lead TSSOP package.

• Has an update rate of 21.3 MSPS and a settling time of 35ns.

• Good 4-quadrant multiplication characteristics.

• Has a 10 MHz multiplying bandwidth.

AD5447 This device is almost identical to the AD5440 with the onlymajor difference being that it is a 12-bit DAC instead of a 10-bit DAC.

If a future team or other project needs to select different DACs, anothervendor for replacements will be needed since these were the only two offeredby Analog Devices in the 24-lead TSSOP.

2.3 Implementation process

This section describes the steps taken to fulfill the design requirements.

2.3.1 Channel mapping and device mating

Before testing can take place, the devices need to be physically connectedto the tester and the channels need to be mapped in software. The physicalconnection involves determining which physical pin on the device connects towhich physical pin in the tester. Channel mapping involves taking the infor-mation about the physical connection and relating it to the IG-XL software.This information allows the test program to send a specific pattern of inputsignals to the chip and read the outputs from the chip.

The process for mating the device uses the pinout information providedby Teradyne and the datasheet of the device under test. The Teradynepinout (sample shown below) describes the physical layout of the connectorsand their internal connections to the tester. As described above, each pin

22

has a specific function. By matching the function of the tester pin to theappropriate pin on the device, a mating can be determined.

A major concern in device mating is physical damage to either the devicesunder test or the tester itself. Obviously damage to the tester is the highestconcern because of its high cost. Power pins and data pins need to be properlymapped so that the tester does not source or sink too much current throughthe wrong pin.

Device mating and channel mapping were completed for all of the partslisted above. The details for the channel mappings are contained within theIG-XL spreadsheets that were created to support the test procedures.

2.3.2 Template creation

After the devices had been mated and mapped, the next step was to createtest templates for each of the devices. These templates were to be usedin conjunction with the cookbook to run tests. Work was started on thisprocess, but technical problems prevented the completion of these templates.Creating the templates requires the use of the IG-XL software, which wasunavailable for a major portion of the design and testing phase. Channelmaps were created for all of the devices, while specification sheets and levelsheets were created for some of the devices.

2.3.3 Cookbook maintenance and improvements

Although the mixed-signal portion of the cookbook could not be added asa result of technical difficulties, the team identified areas were the previouscookbook could be improved. The cookbook should be a professional doc-ument that could be used by any competent student or engineer, within oroutside of Iowa State. Therefore, many formatting and appearance issuedwith the existing cookbook were fixed. A standard formatting and writingstyle was adopted in order to improve the coherency of the overall document.These changes will allow future teams to expand the cookbook with minimaleffort in document creation, allowing them to focus on technical issues.

2.4 End-product testing

Because of technical difficulties, it was not possible to test the templateson the tester itself. However, readability tests of the current documentation

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Figure 8: Teradyne pinout chart

24

Figure 9: Final TSSOP to ZIF converter

25

were performed with students in the department in order to identify areasthat could be improved in the future.

2.5 Project end results

The first major accomplishment of the project was device selection. In orderto physically connect the devices to the tester, appropriate parts must bechosen. Especially for an educational instruction manual, device selectionis vital. With the wrong devices, it would be very difficult for studentsto identify problems with test methodology and problems with the actualdevice. The research and reasoning behind the device selections will be usefulto students and future design teams.

The second major accomplishment was the device mating. Because of theconstraints imposed by the daughter board and the DIBs available, devicemating is a non-trivial task. Electrical connections between the DIB pinsand the devices have been verified. This information, along with the channelmapping, will save future groups time in setting up the physical environmentand allow them to focus directly on testing.

The final major accomplishment was improvements to the current cook-book. Because it was not possible to complete the tests itself, the teamshifted focus to improve the current cookbook as much as possible. This endproduct will be valuable both for students who wish to use it directly andalso to future design teams, since it will be easier to write new material forthe cookbook.

3 Resources and schedule

This section reflects the resource requirements, personal effort requirements,the project schedule and the financial requirements.

3.1 Personal effort requirements

The total contribution by each team member, in hours, is listed in the Ta-ble 1 below. The table is broken down into problem definition, technologyselection, end-product development, end-product testing, end-product doc-umentation, and project reporting. The project provided plenty of work

26

to keep the whole team involved and had enough flexibility for unforeseencircumstances.

The team was made up of five electrical engineers, who each had to putsome work into programming on the Teradyne. Brent was assigned to main-tain web page the due to prior experience. A good deal of time during thefirst phase of the project was dedicated to adapting to the Teradyne and set-ting up tests for the parts purchased. The purchase of parts was taken careof by Rob who had prior experience with the ordering of circuit components,leaving the rest of the team to play a supporting research role. The teamtook an active role in both the development and the end-product testingwith more coding time dedicated to Murwan and Jon who had taken moreprogramming classes and, thus, had more experience. These were the tasksassigned during the first phase of the project.

The latter phase of the project would primarily involve running tests,code development and de-bugging the test instances that are created to meetthe required objective as well as modifying the existing cookbook, all ofwhich require a larger time frame. Extra preparation during the first phasedefinitely reduced the amount of time spent during the second phase. Theaddition of Paul in the second semester with his testing experience with ICchips and programming knowledge has helped. At present, due to hard-ware and software failures, IG-XL code development problems have occurredand computer hardware and software down-time have pushed the project offschedule.

The problem definition has been facilitated by the project plan and withthe technology considerations being one of the important factors within theproject, product research evaluation was done with reference and guidancefrom Dr. Weber. The end-product development (IG-XL code) and testinghas and will continue to consume a large portion of the time on this project.To meet the ongoing deadline, the present action plan as being implementedis that Brent, Jon and Paul will focus on the ADC's and DAC's IG-XLcode development with Rob focusing on just the 100 MHz op-amp, whichhas to be developed without any form of previous IG-XL documentation ortutorials.

3.2 Other resource requirements

The Teradyne J750 tester was already in the possession of Iowa State Uni-versity in the form of a donation and was available to the team free of charge.

27

Table 1: Total personal efforts

Personnel Pro

ble

mdefi

nit

ion

Tec

hnolo

gy

sele

ctio

n

End-p

roduct

dev

elopm

ent

End-p

roduct

test

ing

End-p

roduct

docu

men

tation

Pro

ject

report

ing

Est

.to

tal

Abdelbasir, Murwan 56 37 79 55 36 27 290Brown, Jon 32 69 78 58 38 26 301Hewitt-Borde, Brent 40 63 75 56 37 25 296Jennings, Paul 0 0 52 45 42 31 170Stolpman, Rob 36 72 79 57 35 26 305Total 164 241 363 271 188 135 1362

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It should be noted that the actual cost of the J750 tester if purchased wouldhave cost Iowa State University approximately $500,000. A project posterwas created and the costs associated with the poster are included. A sum-mary of the initial resources are listed in Table 2 below.

Table 2: Estimated additional resources

Item Team hours Other hours CostADC IC chip 0 0 $40.00DAC IC chip 0 0 $40.00

Printing of project poster 15 0 $35.00Teradyne Integra J750 Test System 0 0 Donated

Operational Amplifier 0 0 $10.00Total 15 0 $125.00

Upon periodic consultation with Dr. Weber and doing some of the labmodules in the tutorial as outlined by Teradyne, it was concluded that extraparts had to be purchased. This change in resources can be viewed in Table 3below.

Table 3: Revised estimated additional resources

Item Team hours Other hours Cost(2) two ADC IC chips 0 0 $20.00(2) two DAC IC chips 0 0 $20.00

Printing of project poster 15 0 $35.00Teradyne Integra J750 Test System 0 0 Donated

(2) two operational amplifiers 0 0 $12.0024-pin ZIF socket 0 0 $10.00

TSSOP to DIB adapter 0 0 $75.00Total 15 0 $172.00

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3.3 Financial requirements

The final cost estimate for the project can be seen in Table 4 below. Thiscalculation is based off the hourly wage of $11.50/hr.

Table 4: Final revised project costs

Item Parts and laborParts and materials:Printing of project poster $35.00Teradyne Integra J750 Test System DonatedDAC IC (2x) $40.00ADC IC (2x) $40.00Operational amplifier (2x) $12.0024-pin ZIF socket $10.00TSSOP to DIB adapter $75.00Subtotal $172.00Labor at $11.50 per hour:Abdelbasir, Murwan $3335.00Brown, Jon $3461.50Hewitt-Borde, Brent $3404.00Jennings, Paul $1955.00Stolpman, Rob $3507.50Subtotal $13,708.00Total $13,880.00

3.4 Project schedule

A Gantt chart was created to show the schedule throughout the durationof the project. The deliverables and accomplishments for each previouslydefined task and subtask are presented in the Gantt chart below. The chartsinclude the date of completion and the amount of time spent on each task.

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Fig

ure

10:

Pro

ble

mdefi

nit

ion

Gan

ntch

art

31

Fig

ure

11:

Tec

hnol

ogy

sele

ctio

nG

annt

char

t

32

Fig

ure

12:

Pro

ject

repor

ting

Gan

ntch

art

33

Fig

ure

13:

End

pro

ject

del

iver

able

sG

annt

char

t

34

4 Closure materials

This section will provide project evaluation with respect to the current progress,commercialization possibilities, recommendations for additional work, lessonslearned, risk and management, project team information and finally a closingsummary.

4.1 Project evaluation

The success of the project will depend on the team's goals laid out in theGantt chart as well as the milestones criteria as shown in the Table 5 below.

4.1.1 Project milestones for evaluation

Table 5: Milestones and grading weights

Milestone (%)Project definition 10Device selection and usage 10IG-XL code development 20End-product design 10End-product implementation 10End-product testing 10End-product documentation 10End-product demonstration 10Project reporting 10Total 100

4.1.1.1

• Milestone: Project Definition

• Description: The project should be defined and outlined so that theteam has a precise and uniform vision of the project's direction. Awell laid out project definition guides the team to work as a cohesiveunit.

35

• Evaluated By: Client and faculty advisors

• Evaluation Criteria: Evaluators weigh the project definition withthe expected results that they deem fit for the scope of the project andassign a score based on the table of milestones and grading weights.

• Weight: 10%

4.1.1.2

• Milestone: Device Selection and Usage

• Description: An integral part of the project depends on the appro-priate selection of devices. The types of ADC, DAC, Op-amp chips aswell as the socket/converters and their compatibility with the daughterboard of the Teradyne J750 tester are all important components to thesuccessful completion of this project.

• Evaluated By: Team members

• Evaluation Criteria: Compatibility with J750 tester interface, thecost, and documentation of research.

• Weight: 10%

4.1.1.3

• Milestone: IG-XL code development

• Description: IG-XL test instances for each device should include rel-evant documentation as outlined with part specifications sheets.

• Evaluated By: Team members and faculty advisors

• Evaluation Criteria: Evaluators will look at the code functionalityand to see if it runs successfully with minimal bugs.

• Weight: 20%

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4.1.1.4

• Milestone: End-Product Design

• Description: This project design should incorporate all the relevantinterface designs with layouts (mapping), part specifications and testinstances.

• Evaluated By: Team members and faculty advisors

• Evaluation Criteria: Evaluators will look at the design and reviewfor compatibility, redundancy, IG-XL test instances functionality aswell as overall understandability of the parts selected.

• Weight: 10%

4.1.1.5

• Milestone: End-Product Implementation

• Description: The final end-product implementation provided by theteam

• Evaluated By: Team members and faculty advisors

• Evaluation Criteria: The correlation between the design and imple-mentation, the ability of the team to adjust appropriately for non-idealconditions, and finally the resourcefulness of the team at modifyingexisting components, code and external hardware with little or no vari-ation to disrupt existing operations.

• Weight: 10%

4.1.1.6

• Milestone: End-Product Testing

• Description: Testing determines how reliable and ready a product isfor the market. Comprehensive device testing is the key to a successfulproject.

• Evaluated By: Team members

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• Evaluation Criteria: Tests should be conducted efficiently and shouldrepresent the possible industry standard results. Evaluation criteriashould be based on how well this is done.

• Weight: 10%

4.1.1.7

• Milestone: End-Product Documentation

• Description: Addition existing Teradyne cookbook manual. It willinclude an instruction set on how to do MSO testing with the devicesselected.

• Evaluated By: Faculty advisors

• Evaluation Criteria: How well does the manual: cover the scope ofthe project, fit with the preceding manual (cookbook), and meet theneeds of the client.

• Weight: 10%

4.1.1.8

• Milestone: End-Product Demonstration

• Description: A demonstration on the process of testing the deviceswill be presented to the Faculty advisor.

• Evaluated By: Faculty advisor

• Evaluation Criteria: How well the final implementation and docu-mentation compare to the overall project definition as well as the teamknowledge of the project.

• Weight: 10%

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4.1.1.9

• Milestone: Project Reporting

• Description: The accumulation of each semester weekly reports, web-site updates, project plan, design report, project poster and final re-port.

• Evaluated By: Faculty advisors

• Evaluation Criteria: Reporting should be evaluated on quality, pro-fessionalism, and understandability as well as usefulness and subjectrelevance.

• Weight: 10%

4.1.2 Evaluation criteria

Project success is determined by the total score which is based on the weightsof given milestones with the Table 6 below showing the scoring protocol foreach milestone. A successful project will earn a total score of no less than80% as stated in the initial project plan.

Estimated required passing percentage: 80%

4.1.3 Project evaluation

The table below is an evaluation of the project based on the progress of theproject. This evaluation takes into account the milestones that currently arescheduled in progress. A conclusive project evaluation for the in progressoption should hold weight on the criterion that the team should have com-pleted excluding any external unaccounted circumstances that was beyondthe control of the team. Resultantly, a clear and compulsive evaluation ofthe project and its current status may only take a portion of the projectmilestones into account. The final evaluation criterion is summarized in Ta-ble 8 where maintaining a 75% score for a successful project means that asuccessful project attains a score of no less than 74.5

The final project evaluation score as illustrated by the total score above,gives a project evaluation score of 82 which succeeds the design evaluationfunctionality score as well as the general project score set at 75.

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Table 6: Estimated design evaluation functionality chart

Functionality Rel

ativ

eim

por

tance

Eva

luat

ion

scor

e

Res

ult

ant

scor

e

ADC testing 10% 100 10DAC testing 10% 100 10Op-amp testing 15% 90 13.50Cookbook interpretation and ease of use 20% 100 20Cookbook integration 10% 100 10Compatibility with previous cookbookMixed signal option testing 15% 90 13.50IG-XL code implementation 20% 80 15Total 100 92.0%

Table 7: Milestone completion scoring rationale

Progress numerical score (%)Greatly exceeded criteria 100Exceeded criteria 100Met criteria 100Partially met criteria 80Did not meet criteria 40Did not attempt 0

40

Table 8: Project evaluation

Milestone Curr

ent

pro

gres

s(%

)

Sch

edule

dpro

gres

s(%

)

Eva

luat

edst

atus

Eva

luat

ion

scor

e(%

)

Wei

ght

Tot

al

Project definition 100 100 Exceeded 100 10 10Device selection and usage 100 100 Exceeded 100 10 10IG-XL code development 25 75 Not met 40 20 8End-product design 100 100 Partially met 80 10 8End-product implementation 50 90 Partially met 80 10 8End-product testing 25 50 Partially met 80 10 8End-product documentation 90 70 Exceeded 100 10 10End-product demonstration 20 20 Exceeded 100 10 10Project reporting 90 85 Exceeded 100 10 10Total 100 82

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4.2 Commercialization

There are currently no plans to commercialize this product. This sectionwill discuss that decision and possible markets if the product were to becommercialized in the future.

4.2.1 Commercialization cost

Because of the cost of the Teradyne J750 tester itself, it is unlikely that therewould be many customers for this product who do not already own the tester(or at least plan to purchase it). Table 9 provides a cost breakdown of theproduct, both with and without the tester included.

Table 9: Commercialization Cost

Item CostParts and materials:DAC IC (2x) $40.00ADC IC (2x) $40.00Operational amplifier (2x) $12.0024-pin ZIF socket $10.00TSSOP to DIB adapter $75.00Subtotal without J750 $177.00Teradyne J750 Test System $500,000Total with J750 $500,177

Given a 20% markup on parts, the product could be sold for $212.40each. However, the true value of this product is not the physical parts, butthe intellectual property contained in the cookbook. Therefore, a higherselling cost might be selected to reflect the value of the information.

4.2.2 Potential market

Since the cookbook is educational material, it could potentially be sold toanyone who wishes to learn to used the J750 tester. The most obvious cus-tomers would be other universities who wish to do the same things thatIowa State wants to do with the tester. It is also conceivable that a com-pany would want to purchase the cookbook and related materials in order to

42

train its employees. However, Teradyne itself provides training material andtraining courses for many companies.

4.3 Additional work

This section will describe suggestions for assignments for future senior designteams. Because of the high value of the tester and the value of the skillsacquired by the students using the tester, it is important to increase its usein the department.

4.3.1 Ongoing Teradyne project

One suggestion that the team discussed was converting the traditional yearlyTeradyne projects into an ongoing project. The team feels that this wouldbe an advantage because it would help the new people to get up to speedmore quickly, since there would be experienced J750 users on hand to givedemonstrations and answer questions. It would also mitigate risks like theones encountered on this project with hardware failure because the teamwould continue into the next semester.

4.3.2 Additional sections for cookbook

With the cookbook structure, it is always possible to add new experimentsand new labs. There are a multitude of parts that could be tested on theJ750, many of which would flesh out the cookbook. These sections could beespecially useful for courses such as E E 418 and E E 510, which deal withhigh-speed testing.

4.4 Lessons learned

This section will describe the lessons learned by the team during the courseof the project.

4.4.1 What went well

Part selection The parts selected represent a good match for all of therequirements set forth by the project. Considering the vast array of partsavailable, finding appropriate devices to test is not a trivial task. Future

43

design teams will be able to use the ideas developed in this project to selecttheir own devices.

Physical device interface Although one of the criteria for part selectionwas selecting parts that physically work with the tester, adapters to fit theparts to the machine were still required. The devices were successfully matedand the project stayed within the budget because of good research.

Adaptability Even though the project ran into technical difficulties, theteam still accomplished at least some of its goals. When it was not possibleto continue with testing, the team moved to other areas where the cookbookcould be improved for future students.

4.4.2 What did not go well

Hardware Possibly because of power fluctuations in Coover Hall becauseof weather and construction, the tester was unavailable for approximatelyfour weeks during our primary implementation and testing phase. Since thetester is located in a secure environment, the proper channels had to be usedin order to repair the tester. In some cases, CSG was slow to respond toinquiries on the status of the machine. In other cases, there was a lack ofcommunication amongst the group on who should drive the issue.

4.4.3 Technical knowledge gained

Device characteristics Although the group was at least familiar with thetypes of devices that would be tested prior to the start of the project, everymember of the team gained in-depth experience in the specifications andcharacteristics of the devices.

Test methodology Through working with the sample labs and creatingtest procedures of our own, the team gained familiarity with standard testmethodology. That knowledge will continue to be useful in industry.

Teradyne J750 In addition to the general testing knowledge gained, theteam also learned the details of the Teradyne J750 system. That knowledgewill be specifically useful for operating the J750 tester, and is also generaliz-able to other testing systems.

44

4.5 Non-technical knowledge gained

Communication All of the team members improved their communicationskills throughout the project. The incidents of hardware failure actuallyenhanced this point by forcing the team to hand off the tasks for the day toeach other, based on who was available.

4.6 Risk management

All projects face risk. This section describes the predicted risks, the encoun-tered risks, and risk management.

4.6.1 Predicted risks

This section discusses the risks identified at the beginning of the project andproposals to avoid them.

• Risk: Developing the (10) ten- to (12) twelve-bit ADC's to be testedmight fail to give accurate results.

• Management: (10) ten- to (12) twelve-bits ADC are pretty high res-olutions. To avoid digital noise on the analog signals, the addition ofa separate voltage supply (about +5V) devoted just to the ADC andthe photodiodes used as inputs. The ground for all of the above couldbe tied into one point where the power came into the regulator. Withminimal bypass capacitors on the ADC inputs that might easily getstable readings.

• Risk: In developing the (10) ten MHz Op amp to be tested, the desiredfrequency might not be generated accurately due to misinterpreting ofthe external RC model of the circuit which can cause op-amp instability.

• Management: Reducing the resistance value that makes up the RCcircuit reduces the effect of the capacitance; this effect leads to the ruleof thumb that high frequencies and low resistance go together. Inputcapacitance is easily compensated by adding a feedback capacitor intothe circuit. The value of the feedback capacitor should be just largeenough to achieve the desired overshoot response, because larger valuescause a loss of high-frequency performance.

45

• Risk: The team might lose or misplace some of the documentations.

• Management: Hard disks and hard copies will be used to limit the risksof losing any of the documentations. Also, the team will make sure thatevery member of the team has a copy of all the documents in case ofemergencies where one of the members is not available for any reason.

• Risk: Failure to meet the client (Iowa State) expectations.

• Management: The team agreed on having regular informal meetingsto review the requirements and the work accomplished thus far so asto meet these requirements. Also, to discuss any further improvementsthat could be added even if it was beyond the requirements to maintainhigh project efficiency.

• Risk: Facing possible learning and understanding difficulties.

• Management: Trying to assign different design aspects to each memberof the team to achieve his/her own expertise in that area along withgeneral understanding of all design aspects by the whole team. Thisway the team can guarantee to extend the limit of coverage of all aspectsof the design conflicts.

4.6.2 Identified risks encountered

The project failed to meet all of the client's expectations. This was at leastpartially a result of circumstances beyond the team's control. However, theteam did fall back on the plan to work on further improvements when thetechnical problems occurred.

4.6.3 Unidentified risks encountered

• Risk: Failure of the computer controlling the tester

• Management: Since the computer is so vital to finishing this projectsuccessfully, this was a very difficult risk to manage. One group memberwas assigned to drive the issue with Teradyne and CSG. Unfortunatelythere was still an extended period of time during which it was notpossible to develop or run tests. As a secondary risk managementstrategy, other parts of the cookbook were improved without the useof the tester.

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• Risk: Problems with proprietary software

• Management: Secondary to the hardware problems with the computer,there were licensing issues with the IG-XL software. In order to managethis risk, Teradyne was contacted to get a new license file as soon aspossible and CSG was contacted to get the new file installed.

4.6.4 Changes in risk management as a result of unanticipatedrisks

Our risk management strategy shifted from managing failed tests to manag-ing failed equipment. In order to manage that risk, we assigned one groupmember to work with CSG and Teradyne to get the problems fixed as soonas possible. We assigned another group member to make improvements tothe existing cookbook where possible.

4.7 Project team information

This section lists the project team, client, and faculty advisor contact infor-mation.

4.7.1 Client information

Department of Electrical and Computer EngineeringCollege of EngineeringIowa State University2215 Coover HallAmes, IA 50011

4.7.2 Faculty advisor information

Dr. Robert J Weber301 DurhamAmes, IA 50011Office: (515) 294-8723Fax: 515-294-1152weber@iastate.edu

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4.7.3 Team members' information

The contact information for the members of the project team is shown in thetable below.

Table 10: Contact information

Murwan Abdelbasir Jon Brown Brent Hewitt-Borde3426 Orion Drive 225 N Hyland 3426 Orion DriveApt #210 Apt #4 Apt #210Ames, IA 50010 Ames, IA 50014 Ames, IA 50010(515) 441-1316 (319) 651-4834 (515) 232-9112murwan82@iastate.edu trebnoj@iastate.edu brentvp@iastate.eduPaul Jennings Rob Stolpman515 N Hyland 4305 MaricopaApt #3 Apt #3Ames, IA 50014 Ames, IA 50014(712) 348-4208 (612) 741-2723poj@iastate.edu stolpman@iastate.edu

4.8 Closing summary

The Teradyne J50 can be a very powerful device given the right amount offunding. The members of this senior design team presented a low cost so-lution for testing mixed signal devices by utilizing some of the instrumentsalready available at ISU. The best way to do this was by expanding the cur-rent cookbook for the Teradyne J750, which in turn will allow ISU studentsand faculty the ability to use this tester more efficiently.

A mixed-signal option will increase the number of avenues for testingthese devices. It is the vision of the team and its advisor, Dr. Weber, thatthis guide will be beneficial to future students and research at ISU and thatthey will be able to follow suit in the future by using the developed guide tokeep the tester up to date with expanding technology.

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4.9 References

• Senior Design Team Spring 2005, ”Teradyne J750 Tester Cookbook.”February 2004.

• Senior Design Team May 2005, ”Final Report.” April 2005.

• Teradyne, ”Teradyne J750 software manual,” 2003.

• Teradyne, User manual, 2003.

• Teradyne, Mixed-signal option tutorial, 2003.

• Teradyne, Teradyne J750, September 22, 2006. http://www.teradyne.com.

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A Data sheet for AD823

B Data sheet for OP37

C Data sheet for AD7892

D Data sheet for AD7470

E Data sheet for AD5440/AD5447

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