Lecture 8 Transistors Topics Review: Combinational Circuits Decoders Multiplexers Breadboards, LEDs...

Lecture 8Transistors

Lecture 8Transistors

TopicsTopics Review:

Combinational CircuitsDecodersMultiplexers

Breadboards, LEDs Components on integrated circuit (ICs) Transistors CMOS

Readings 5.4, 5.7Readings 5.4, 5.7

September 29, 2014

CSCE 211 Digital Design

– 2 – CSCE 211H Fall 2014

Hot BatteriesHot Batteries

You should regularly check your batteries “slightly You should regularly check your batteries “slightly warm” is OK but hot indicates that your circuit has a warm” is OK but hot indicates that your circuit has a short circuit.short circuit.

Unplug quickly and check.Unplug quickly and check.1. Look for direct lines Vcc to GND.

2. Remember you need 330 ohm resistors in series with LEDs and that includes segments of the seven segment display.

3. Recheck sections of the breadboard.

– 3 – CSCE 211H Fall 2014

Transistor: Water Flow ModelTransistor: Water Flow ModelWater flow in B raises the plunger so that water can flow from C to E.

Small flow turns on and off bigger flow.

Put signal on B, transfer signal C to E

Reference: http://www.satcure-focus.com/tutor/page4.htm

– 4 – CSCE 211H Fall 2014

Transistor TerminologyTransistor Terminology

Conductor – electrons easily passed from one atom to Conductor – electrons easily passed from one atom to next (copper every atom has loose electron)next (copper every atom has loose electron)

Insulator – electrons tightly tied down to atoms, no flowInsulator – electrons tightly tied down to atoms, no flow

Semiconductor – by adding impurities (doping) can be Semiconductor – by adding impurities (doping) can be changed to increase conductivitychanged to increase conductivity

Silicon wafer – used for IC circuitsSilicon wafer – used for IC circuits

N-type - silicon doped with boron (excess electrons)N-type - silicon doped with boron (excess electrons)

P-ype - silicon doped with phosphorous (excess P-ype - silicon doped with phosphorous (excess “holes” lack of electrons)“holes” lack of electrons)

– 5 – CSCE 211H Fall 2014

TransistorTransistor

Reference: http://www.intel.com/education/transworks/

– 6 – CSCE 211H Fall 2014

TransistorTransistor

Reference: http://www.intel.com/education/transworks/

– 7 – CSCE 211H Fall 2014

TransistorTransistor

Reference: http://www.intel.com/education/transworks/

Put Positive charge on gate.

This attracts electrons into gap.

This allows electrons to pass freely through the gap.

– 8 – CSCE 211H Fall 2014

TransistorTransistor

Reference: http://www.intel.com/education/transworks/

– 9 – CSCE 211H Fall 2014

TransistorTransistor

Reference: http://www.intel.com/education/transworks/

Take positive charge offGate

This stops attractingelectrons.

This shuts off the flow.

– 10 – CSCE 211H Fall 2014

N channel transitorN channel transitor

– 11 – CSCE 211H Fall 2014

P channel TransistorP channel Transistor

– 12 – CSCE 211H Fall 2014

CMOS InverterCMOS Inverter

– 13 – CSCE 211H Fall 2014

CMOS NANDCMOS NAND

– 14 – CSCE 211H Fall 2014

What’s This?What’s This?

– 15 – CSCE 211H Fall 2014

– 16 – CSCE 211H Fall 2014

High impedanceHigh impedance

High impedance is the state of an output terminal which High impedance is the state of an output terminal which is not currently driven by the circuit; neither high nor is not currently driven by the circuit; neither high nor lowlow

Like an unconnected wireLike an unconnected wire

It is also known as hi-Z, tri-stated, or floatingIt is also known as hi-Z, tri-stated, or floating

http://en.wikipedia.org/wiki/High_impedance

– 17 – CSCE 211H Fall 2014

Tri-state BufferTri-state Buffer

http://en.wikipedia.org/wiki/Three-state_logic

In the tri-state buffer the enable input (B) acts as a In the tri-state buffer the enable input (B) acts as a switchswitch

Note if B is enabled then C=A and if B is not enabled Note if B is enabled then C=A and if B is not enabled then C = High-impedancethen C = High-impedance

– 18 – CSCE 211H Fall 2014

Tri-state Buffer ImplementationTri-state Buffer Implementation

.. En A B C D Q1 Q2 OUT

L L

L H

H L

H H

– 19 – CSCE 211H Fall 2014

Transmission Gates (Fig 3.45)Transmission Gates (Fig 3.45)

En En_L A B

0 1 0

0 1 1

1 0 0

1 0 1

A is the input; B the outputA is the input; B the output

– 20 – CSCE 211H Fall 2014

2-to-1 Mux from transmission gates2-to-1 Mux from transmission gates

..

– 21 – CSCE 211H Fall 2014