High Endurance Last Level Hybrid Cache Design

High Endurance Hybrid Cache Design with Access Aware

policies and Dynamic Cache Partitioning By Thallam Keerthi

Under Guidance of Mrs.Namitha PalechaRVCE VLSI Design and Embedded systems

OverviewOverview

Problem Description Introduction to STT-RAM Local Bank Hybrid Cache Architecture Access Aware Policies STT-RAM Write Management Policy (Algorithm) SRAM Read Management Policy (Algorithm) Dynamic Cache Partitioning (Algorithm) Performance Analysis Conclusion

Problem DescriptionProblem Description

Increasing frequency of operations on one core-increases the heat Dissipation

CMP – Chip Multiprocessors solves the issue without increasing the frequency of each core

Last level cache(LLC) – Shared memory for cores – Usually composed of SRAM’s – High leakage power

Problem DescriptionProblem Description

SRAM STT-RAM

Density 1X 4X

Read Time Very fast Fast

Write Time Very fast Slow

Read Energy Low Low

Write Energy Low High

Leakage Energy High Low

Endurance 10^16 4*10^12

SRAM has high leakage power and STT-RAM requires high write energy and write latency is more

Hybrid Cache ArchitectureHybrid Cache Architecture

Problem: Local Bank suffers from more write counts and wears out fast.

Non-Uniform distribution of workload among different memory banks

Hybrid Cache ArchitectureHybrid Cache Architecture

Part of local bank consists of SRAM cells and remaining part consists of STT-RAM cellsThis decreases the write pressure on the local bank

(Banks)

(Write count)

Showing the unequal workload

Hybrid Cache ArchitectureHybrid Cache Architecture

All writes on non-hybrid local bank are redirected to SRAM bank and only few writes of local hybrid bank are redirected to SRAM cell

Access Aware PoliciesAccess Aware Policies

STT-RAM Write Management Policy

Access Aware PoliciesAccess Aware Policies

SRAM Read Management Policy (Increases Write Utilization of SRAM)

Access Aware PoliciesAccess Aware Policies

Dynamic Cache Partitioning

1) Which Partition size needs to be changed2) Which region in a partition needs to be changed

• Ideally WPSW should be high•WPNW should be minimum or less

Access Aware PoliciesAccess Aware Policies

Cache Partitioning Algorithm

Performance AnalysisPerformance Analysis

Unbalanced Write distribution on different banks

Performance AnalysisPerformance Analysis

Improved Write counts on local and non-local banks with Hybrid Cache

Performance AnalysisPerformance Analysis

Increase of lifetime with Hybrid cache Write counts on STT-RAM

Performance Analysis Performance Analysis

Variations with respect to changes in the SRAM size in Local Hybrid Bank

ConclusionConclusion

CMP Architecture – No. of operations can be increased working with same frequency

Hybrid Cache – Balances the write distribution among the banks

Access Aware Policies – increases the write utilization of SRAM and decreases the endurance problem of STT-RAM cells

Dynamic Cache Partitioning – Decreases the hit latency, decreases the cache miss rate.

Thank you

Any Questions?