From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... ·...

Computer ArchitecturePaul Mellies

From transistors to digital logic

000 1 1

The digital abstraction

Every light bulb is either ON or OFF

The digital abstraction

Every light bulb is either ON or OFF

1 0 1 0 0 1 0 0

1 0 0 1 10 1 1

1 0000 1 1 0

Additional idea : transistors are switches !

source

gate = 0 gate = 1

source

gateNMOS

source

gate = 0 gate = 1

source

gateNMOS

source

good for 0’sbad for 1’s

source

gate = 0 gate = 1

source

gateNMOS

source

Fine, but what does that mean exactly ?

source of electrons

drain of electrons

source of holes

drain of holes

N-channel MOSFETenhancement mode

P-channel MOSFETenhancement mode

nt �

Enhancement-mode MOSFET transistors

The device is OFF at rest.A positive voltage must then be applied to the gate

wrt. the source in order to switch the device ON.

The device is OFF at rest.A negative voltage must be applied to the gatewrt. the source in order to switch the device ON.

source of electrons

drain of electrons

source of holes

drain of holes

N-channel MOSFETenhancement mode

P-channel MOSFETenhancement mode

nt �

Enhancement-mode MOSFET transistors

The device is OFF at rest.A positive voltage must then be applied to the gate

wrt. the source in order to switch the device ON.

The device is OFF at rest.A negative voltage must be applied to the gatewrt. the source in order to switch the device ON.

body body

A 3D picture of an NMOS transistor

Picture reproduced from the excellent book by Jaeger and Blalock : Microelectronic -- Circuit Design ( Mac Graw Hill, fourth edition )

The three operation modesof a NMOS transistor

CUT-OFF

source

gateGSV

TNwhere V denotes the threshold voltage

Here, Kn denotes the transductance parameter of the NMOS transistor

The three operation modesof a NMOS transistor

LINEAR OR TRIODE

≥ ≥ GSV+

source

DSVGSV

VTNVGS 2DSV

nK DSV--D = I

The linear or triode operation mode

Drain-source voltage ( V )

source

( μA )

00 0.2

GSV = 5 V

GSV = 4 V

GSV = 3 V

GSV = 2 V

0.4 0.6 0.8

Exercise :

For this speci�c NMOS transistor, can you give for each Gate-Source Voltage :

2 V 3 V 4 V 5 V

an approximation of the Drain-Source resistance at the origin ?

pMOS transistors work in just the opposite fashion, as might be guessedfrom the bubble on their symbol shown in Figure 1.31. The substrate is tiedtoVDD. When the gate is also atVDD, the pMOS transistor is OFF.When thegate is at GND, the channel inverts to p-type and the pMOS transistor is ON.

Unfortunately, MOSFETs are not perfect switches. In particular,nMOS transistors pass 0’s well but pass 1’s poorly. Specifically, whenthe gate of an nMOS transistor is at VDD, the drain will only swingbetween 0 and VDD−Vt. Similarly, pMOS transistors pass 1’s well but0’s poorly. However, we will see that it is possible to build logic gates thatuse transistors only in their good mode.

nMOS transistors need a p-type substrate, and pMOS transistorsneed an n-type substrate. To build both flavors of transistors on the samechip, manufacturing processes typically start with a p-type wafer, thenimplant n-type regions called wells where the pMOS transistors shouldgo. These processes that provide both flavors of transistors are calledComplementary MOS or CMOS. CMOS processes are used to build thevast majority of all transistors fabricated today.

In summary, CMOS processes give us two types of electricallycontrolled switches, as shown in Figure 1.31. The voltage at the gate (g)regulates the flow of current between the source (s) and drain (d). nMOStransistors are OFF when the gate is 0 and ON when the gate is 1. pMOS

gatesource drain

substrate

(a)GND

gatesource drain

substrate

- - - - - - -

channel

+++++++

Figure 1.30 nMOS transistor operation

Gordon Moore, 1929–. Born in SanFrancisco. Received a B.S. inchemistry from UC Berkeley anda Ph.D. in chemistry and physicsfrom Caltech. Cofounded Intelin 1968 with Robert Noyce.Observed in 1965 that thenumber of transistors on acomputer chip doubles everyyear. This trend has becomeknown as Moore’s Law. Since1975, transistor counts havedoubled every two years.

A corollary of Moore’sLaw is that microprocessorperformance doubles every 18to 24 months. Semiconductorsales have also increasedexponentially. Unfortunately,power consumption hasincreased exponentially as well(© 2006, Intel Corporation.Reproduced by permission).

Figure 1.31 Switch models ofMOSFETs

30 CHAPTER ONE From Zero to OneThe two switching positions of an NMOS transistor

switched OFF switched ON

Threshold voltage : voltage required to turn on a transistor

Note : the MOS terminal which is acting as the drain is determined by the potentials.

Here, just as before, Kn denotes the transductance parameter of the NMOS transistor

source

VTN ≥ ≥ DSV GSV 0-

The three operation modesof a NMOS transistors

SATURATION

VTNVGS2nK

-D = I2

VoltageGate-Source

VoltageDrain-Source

Summary :the three modes of an NMOS transistor

cut-o� saturation

linear

VoltageGate-Source

VoltageDrain-Source

cut-o� saturation

linear

VTNVGS2nK

-D = I2

VTNVGS 2DSV

nK DSV--D = I

V + DS

VoltageGate-Source

VoltageDrain-Source

cut-o�

saturation

linear

V + DS

VoltageGate-Source

VoltageDrain-Source

cut-o�

saturation

linear

VTNVGS2nK

-D = I

VTNVGS 2DSV

nK DSV--D = I

V + DS

VoltageGate-Source

VoltageDrain-Source

cut-o�

saturation

linear

VTNVGS 2DSV

nK DSV--D = I

VTNVGS2nK

-D = I2

VDS2nK

D = I 2

Characteristics of the NMOS transistor

source

( μA )

LinearRegion

20406080

100120140160180200220

0 2 4 6 8 10 12

GSV = 5 V

Linear region

Pinch-o� locus

Saturation region

GSV = 4 V

GSV = 3 V

GSV = 2 V

GSV ≤ 1 V

Three-dimensional representationof the characteristic curves

Voltage of A

VDDV /2DD

Voltage of Y

Exercise :Using a transistor and an NMOS resistor

can you construct a circuit with the following ( idealized ) transfer curve ?

Inverter

Note : such a circuit is called an inverter

An NMOS inverter with resistor-load

pull-up resistor

NMOS transistor

Voltage of A

VDDV /2DD

Voltage of Y

Ideal characteristic transfer curve

Voltage of A

Voltage of Y

Real characteristic transfer curve

Voltage of A

Voltage of Y

Exercise :

Describe in which mode the NMOS transistoroperates at each position of the curve

Voltage of A

Voltage of Y

Solution

VTNcut-o�saturation

linear

Voltage of A

Voltage of Y

Solution

VTNcut-o�saturation

linear

transition point

( μA )

20406080

100120140160180200220

0 1 2 3 4 V = 5 V

GSV = 5 V

GSV = 4 V

GSV = 3 V

GSV = 2 V

How to compute the transition point ?

load line

transition point

Exercise

resistor R

resistor r

Give an explicit formula for the voltage V with parameters V and the values of the two resistors R and r in the schematics below/

Explain why the resistor R should be as high as possiblecompared to the resistance r of the NMOS transistorat linear mode with gate-source voltage V equal to V .GS DD

Exercise

resistor R

More generally, how would you compare the characteristictransfer curves of two inverters with resistor load constructed with the same NMOS transistorbut with pull-up resistors R and R of di�erent values ?1 2

V =IL VIH

Voltage of A

VDDV /2DD

Voltage of Y

Ideal characteristic transfer curve

VIL VIH

Voltage of A

Voltage of Y

Unity Gain Pointwith slope = -1

Real characteristic transfer curve

Logic levels and noise margins

ForbiddenZone

Logic HighOutput Range

Logic LowOutput Range

Logic HighInput Range

Logic LowInput Range

VDDOutput characteristics Input characteristics

Driver Receiver

Exercise

Driver Receiver

Can you draw a ( qualitative ) picture of the characteristic transfer curveof the following circuit, constructed by composing two inverters:

What can this circuit be useful for ?

Logic levels of 5 V and 3.3 V logic families

TTL = Transistor - Transistor Logic

LVTTL = Low Voltage TTL Logic LVCMOS = Low Voltage CMOS Logic

CMOS = Complementary Metal - Oxide Semiconductor

An NMOS inverter with resistor-load

such a resistor would be far too largeto implement on an integrated circuit

The NMOS saturated inverter

pull-up transistoreither in cut-o� orin saturation mode

enhancement-mode load=DSV GSV

pull-up transistoralways in cut-o� orin saturation mode

enhancement-mode load=DSV GSV

The NMOS saturated inverter

( μA )

20406080

100120140160180200220

0 1 2 3 4 V = 5 V

GSV = 5 V

GSV = 4 V

GSV = 3 V

GSV = 2 V

Resistor vs. enhancement vs. depletion loads

load line

source of electrons

drain of electrons

source of holes

drain of holes

N-channel MOSFETdepletion mode

P-channel MOSFETdepletion mode

nt �

Depletion-mode MOSFET transistors

The device is ON at rest.A negative voltage must then be applied to the gate

wrt. the source in order to switch the device OFF.

The device is ON at rest.A positive voltage must then be applied to the gate

wrt. the source in order to switch the device OFF.

Characteristics of an NMOS transistorin depletion-mode

source

( μA )

LinearRegion

20406080

100120140160180200220

0 2 4 6 8 10 12

GSV = 5 V

Linear region

Pinch-o� locus

Saturation region

GSV = 2 V

GSV = 0 V

GSV = -1 V

GSV ≤ -2 V

A depletion-load NMOS inverter

depletion-mode loadpull-up transistoralways switched on

at gate-source voltageequal to zero

Further reading : Toshiaki Masuhara’s PhD thesis ( Sept. 1976 )

A depletion-load NMOS inverter

depletion-mode loadGND

Further reading : Toshiaki Masuhara’s PhD thesis ( Sept. 1976 )

pull-up transistoralways switched on

at gate-source voltageequal to zero

( μA )

20406080

100120140160180200220

0 1 2 3 4 V = 5 V

GSV = 5 V

GSV = 4 V

GSV = 3 V

GSV = 2 V

Depletion load inverter

load line

0 1 2 3 4 V = 5 V

Resistor-load vs. enhancement-load vs. depletion-load

depletion

resistor

enhancement

On the other hand, the output fall time 1 0 is almost independent of the pullup device

The output rise time 0 1 depends on the pullup deviceDepletion-load is faster than enhancement-load because of the weaker resistance of the pullup device

An NMOS NAND gate with resistor load

a resistor would be far too largeto implement on an integrated circuit

A saturated NMOS NAND gate

enhancement-mode loadpull-up transistoreither in cut-o� orin saturation mode

A depletion-load NMOS NAND gate

pull-up transistoralways switched onwith voltage gate-sourceequal to zero

depletion-mode load

PMOS = NMOSthrough the looking glass

Characteristics of the PMOS transistor

( μA )

source

nt ( μ

- 50+2 0 - 2 - 4 - 6 - 8 - 10 - 12

GSV = - 5 V

GSV = - 4 V

GSV = - 3 V

GSV = - 2 V

GSV ≥ - 1 V

Voltage of A

VDDV /2DD

Voltage of Y

Exercise :Using a PMOS transistor and a resistor

can you construct a circuit with the following ( idealized ) transfer curve ?

Inverter

Trick : use symmetry !!!

Solution : PMOS inverter with resistor-load

pull-down resistor

PMOS transistor

Order of apparition in history

NMOSenhancement-load

NMOSdepletion-load

• 1971 : Intel 4004 ≈ 2250 PMOS transistors• 1972 : Intel 8008 ≈ 3500 PMOS transistors• 1975 : Rockwell PPS-8

• 1973 : NEC μCOM 4 ≈ 2500 NMOS transistors• 1974 : Intel 8080 ≈ 6000 NMOS transistors• 1974 : Toshiba TLCS-12• 1974 : Motorola 6800 ≈ 4100 NMOS transistors

• 1975 : Zilog Z80 ≈ 8500 NMOS transistors• 1975 : MOS Technology 6502 ≈ 3510 NMOS transistors• 1977 : Intel 8085 ≈ 6500 NMOS transistors• 1978 : Intel 8086 ≈ 29000 NMOS transistors

• 1963 : invented by Frank Wanlass at Fairchild Semiconductor• 1975 : Intersil 6100 ≈ 4000 NMOS transistors• 1976 : RCA 1802 or COSMAC• 1981 : Hitachi HD6301 CMOS version of the Motorola 6801• 1982 : Western Design 65C02 which is a CMOS version of the 6502

A CMOS inverter

NMOS transistor

PMOS transistor

The �ve modes of the CMOS inverter

0 V 0.5 V 1.0 V 1.5 VVoltage of A

Voltage of Y

2.0 V 2.5 V

NMOS saturatedPMOS saturated

NMOS saturatedPMOS linear

NMOS linearPMOS saturated

NMOS o�

PMOS o�

Voltage of Y

2.0 V 2.5 V

NMOS o�

PMOS o�

NMOS transistor

PMOS transistor

cuto�

linear

Voltage of Y

2.0 V 2.5 V

NMOS o�

PMOS o�

NMOS transistor

PMOS transistor

saturated

linear

Voltage of Y

2.0 V 2.5 V

NMOS o�

PMOS o�

NMOS transistor

PMOS transistor

saturated

Voltage of Y

2.0 V 2.5 V

NMOS o�

PMOS o�

NMOS transistor

PMOS transistor

linear

saturated

Voltage of Y

2.0 V 2.5 V

NMOS o�

PMOS o�

NMOS transistor

PMOS transistor

cut-o�

linear

CMOS NAND gate

CMOS NOR gate

Source

Insulator

Latest technology : the FinFet transistors

Latest technology : Through-Silicon Via ( TSV )

Readings

Exercices

Harris and Harris, Chapter 1.

Harris and Harris : 1.86, 1.87, 1.88, 1.89, 1.90. Build the corresponding schematics in CircuitLab and test them.

Do the exercises in Recitation 2.

Instruction Set ArchitectureStudy the instruction set which you were assigned between

• LC-3 • MIPS • x86

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