EUVL readiness for 7nm - Ultravioleteuvlsymposium.lbl.gov/pdf/2015/Oral_Monday/Session1_EUV...

EUVL readiness for 7nm Mark Phillips, Britt Turkot

Intel Corporation

EUVL Symposium, 5 October 2015, Maastricht, The Netherlands

After ~30 years of hard work…

EUVL Symposium, 5 October 2015, Maastricht, The Netherlands

H. Kinoshita et al., JVST B 7, 1648 (1989)

Two years of solid progress and momentum towards HVM

Mark Phillips / Intel EUVL Symposium, 5 October 2015, Maastricht, The Netherlands

Outline

• Trajectory over last two years

• Remaining gaps

• EUVL infrastructure

• High NA

EUVL Symposium, 5 October 2015, Maastricht, The Netherlands Mark Phillips / Intel

Source power roadmap has lost credibility

Tool lead time

As presented at 2013 Source Workshop

Conclusions

• Realization of 40~80W stable MOPA+PP sources in the field linked to NXE:3300B scanners over next two quarters looks feasible

• This would enable meaningful integrated process development with 0.33 NA EUVL and re-establish confidence in a source power roadmap to HVM levels

• Need to re-invigorate EUVL infrastructure development, especially:

− Exposure source power scaling beyond 250W with dramatically improved COO

− Actinic metrology source development to meet performance, productivity, COO and schedule

− Commercial EUV pellicle infrastructure

Two years of solid progress on source power

Worldwide fleet 40-80W

Slide courtesy ASML

As of PMJ in April

Now six months later…

Slide courtesy ASML / Alberto Pirati, 2015 EUVL Symposium

• Technology Development requires rapid information turns

− Availability: tool must be up to run TD wafers without delay

• HVM requires reasonable COO and predictability, driven by:

− Productivity (mostly source power)

− Availability (mostly source availability)

− OpEx (mostly source consumables)

What about exposure tool performance gates committing a process node to EUV?

• Technology Development requires rapid information turns

− Availability: tool must be up to run TD wafers without delay – This is the critical, gating concern today

• HVM requires reasonable COO and predictability, driven by:

− Productivity (mostly source power) – Good progress versus HVM need date

− Availability (mostly source availability) – Long way to go, but making progress and have some time

− OpEx (mostly source consumables) – Long way to go, but making progress and have some time

What about exposure tool performance gates committing a process node to EUV?

Scored as of today

However…

Availability and predictability are still poor

As of 2015 EUVL Workshop (June)

Extended demo of availability and predictability

• 21hrs/day wafer cycling with mix of test-chip wafers (CDs, overlay, in-line defects, e-test) and bare silicon

• 3-hr daily Intel engineering window (no tool work)

• Availability counted 24hrs/day. Wafer output targets set for 21hrs/day in 40W config.

• Only good wafers (meeting dose control specs) counted

• Goal: demonstrate tool can run as advertised for 40W config today, including imaging and overlay

Presented at 2015 Litho Workshop (June)

Demo cumulative wafers per week Presented at 2015 Litho Workshop (June)

Demo overlay trend

Time (4 weeks), each point is one wafer; each cluster is one lot

Green = NXE (EUV) to NXT (193i) Red = NXT to NXT (MMO)

• OK. No overlay penalty for EUV-193i versus 193i-193i MMO.

Presented at 2015 Litho Workshop (June)

Demo availability (4 weeks)

• Far from OK for production, but better than expected for current 40W config

NXE:3300 (40W config) availability trend

• 80W config vs 40W previously

• 1 quarter vs 4 weeks

• More integrated wafers and metrology

• Expanded comparison to 193i baseline

• Higher goals

Current demo activity

• Example of one of many availability improvement projects

• Most are difficult to develop, qualify and proliferate to field 19

New DG is a significant improvement…

Slide courtesy ASML / Alberto Pirati, 2015 EUVL Symposium

Outline

• Remaining gaps

• High NA

Conclusions

• Solid progress in last year, with realization of 40~80W stable MOPA+PP sources in the field

• Availability is not adequate for process development and needs substantial improvement over next two quarters

• In situ collector cleaning looks promising, but needs to be delivered to field to gain confidence in OpEx and stable productivity

• Continued progress on source power per roadmap is required to build confidence in long-term productivity targets and COO

• EUV infrastructure is now lagging scanner and source, and needs increased focus

Summary of EUVL status

• Two years of solid progress on EUVL

— Eight 0.33NA systems shipped, generally meeting all performance specs not related to source power

— 80W config proliferating quickly, and 100W (@IF) MOPA/PP demonstrated in the field

— ~500wpd, then ~1000wpd in short-term (1-2 day) demonstrations

— 4 week demonstration of availability and output consistent with 40W tool configuration, and stable imaging and overlay performance

• Introduction in production is a question of “when” rather than “if”

— Availability, stability and operating cost are still concerns

— Need to ensure infrastructure does not gate HVM

See this presentation for full report on impressive EUV mask progress in 2015:

EUV Infrastructure Readiness Snapshot EUV infrastructure has 8 key programs

2 are ready or near-ready now, 4 are in development, 2 have significant gaps

E-beam Mask Inspection: HVM capable tool exists

Actinic Blank Inspection (ABI): EIDEC-led tool development program

EUV resist QC: Industry-wide QC center finalizing definition

AIMS Mask Inspection: SEMATECH-led tool development program

EUV blank quality: Process and yield improvements ongoing

Pellicle: ASML commercializing

Blank multi-layer deposition tool: Improving defect results. Multiple deposition techniques being evaluated to define HVM tool approach.

Post-pellicle mask inspection: APMI not on timeline for insertion. Need other options.

As of PMJ in April

Updated EUV Infrastructure Readiness Snapshot

EUV infrastructure has 8 key programs

2 are ready or near-ready now, 5 are in development, 1 has significant gaps

E-beam Mask Inspection: In use for low volume production. Need TPT increase.

Actinic Blank Inspection (ABI): Transitioning to a QC center in 2016

EUV resist QC: QC center at IMEC expected online in 2017

AIMS Mask Inspection: Imaging demonstrated

Pellicle: ASML commercializing – production phase in 2H 2016

Post-pellicle mask inspection: High resolution PWI for fab. Still need actinic inspection in mask shop.

Bottom line: N7 mask with no printing defects

Slide from Ted Liang, 2015 BACUS

Updated EUV Infrastructure Readiness Snapshot

EUV infrastructure has 8 key programs

2 are ready or near-ready now, 5 are in development, 1 has significant gaps

E-beam Mask Inspection: In use for low volume production. Need TPT increase.

Actinic Blank Inspection (ABI): Transitioning to a QC center in 2016

EUV resist QC: QC center at IMEC expected online in 2017

AIMS Mask Inspection: Imaging demonstrated

Pellicle: ASML commercializing – production phase in 2H 2016

Post-pellicle mask inspection: High resolution PWI for fab. Still need actinic inspection in mask shop.

Remarkable progress in last 2 years

Slide courtesy ASML / Carmen Zoldesi, 2015 BACUS

Commercialization timeline tight but OK

• Reticle front side defect-free solution

• protects reticle front side from fall-on defects

• particle free material combination and mounting technology to prevent particle generation

• additional particle suppression towards pattern area

• Designed for use in NXE scanner

• pump down/vent cycles compatible

• vacuum and H2 environment compatible

• meets outgassing requirements

• no overlay impact, distortion-free mounting

• Compatible with standard EUV mask flow

• concept supports any type of pattern mask inspection: optical, e-beam, and actinic; both at mask shop and fab

• allows for reticle repel cycle

Key features Slide 30

Reticle interface (stud)

Pellicle frame + membrane

Flexures

Interchangeable NXE Pellicle concept

Allowing multiple inspection schemes

Slide courtesy ASML.

1. Pellicle frame is not sealed. 200um

gap needed for pump-down

2. ASML simulation predicts 1/200

attenuation of small particles

3. Critical to verify!

As presented at PMJ 2015

Gap verification in process…

Especially reticles, for example:

N7 via mask with no printing defects

Improved pod qualified, and modified to support pelliclized masks

ABI tool supporting blank manufacturers and mask shops

First fully integrated pellicle, and commercialization plan

RBI qualification

AIMS imaging demonstrated

Champion blanks with no large defects and ~10 small defects (allows pattern shift mitigation)

Good progress on infrastructure in last year

Outline

• Remaining gaps

• High NA

• ~2014 designs not attractive (e.g. limited NA, QF, 9” ret, low TPT)

• HF 0.55NA anamorphic optics, higher transmission, fast stages, offer attractive wafer cost / process simplification proposition

Solid progress on High NA design proposal in last year

Slide courtesy ASML / Jan van Schoot, BACUS 2015

• Ability to use to use full resolution of proposed High NA tools will require Total EPE budget ~1/3 the feature size

As presented at 2013 ASML Technology Symposium

• Resolution potential of 0.55NA tool should allow at least two 0.33NA masks to be replaced with one 0.55NA mask, assuming an adequate Total EPE budget

• Higher dose target (60mJ/cm2) makes sense to manage stochastics of small features, but actual requirement with resists available in ~2020 is not known

• Wafer cost benefit and process simplification (elimination of mask splits) is attractive at ASML target performance

• Many areas of EUVL infrastructure will need further development

− E.g. 500W pellicles, reticle inspection, high-resolution resists, AIMS

High NA conclusions

Conclusions

• Two years of solid progress on source power have debunked claims that EUVL can never achieve high productivity

• Availability, stability and predictability of source are still a problem, but are gradually improving

• Performance of NXE:3300s in field has reinvigorated progress on EUV infrastructure

• High NA proposal has come a long way in the last year, offering attractive wafer cost / process simplification proposition at targeted performance

Acknowledgements Frank Abboud (Intel) Steve Carson (Intel) Tim Crimmins (Intel) Jeff Farnsworth (Intel) Steve Johnston (Intel) Sang Lee (Intel) Ted Liang (Intel) Brian McCool (Intel) Rajesh Nagpal (Intel) Sam Sivakumar (Intel) Eric Stenehjem (Intel) Guojing Zhang (Intel) Dan Smith (ASML) Alberto Pirati (ASML) Jan van Schoot Carmen Zoldesi (ASML)

EUVL readiness for 7nm - Ultravioleteuvlsymposium.lbl.gov/pdf/2015/Oral_Monday/Session1_EUV...

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