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Embedded System Design Embedded System Design Modeling, Synthesis, Verification
Daniel D. Gajski, Samar Abdi, Andreas Gerstlauer, Gunar Schirner
9/29/2011
Chapter 4: System Synthesis
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 2 Chapter 4: System Synthesis
Outline
• System design trends
• Model-based synthesis
• Transaction level model generation
• Application to platform mapping
• Platform generation
• Cycle-accurate model generation
2
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 3 Chapter 4: System Synthesis
Traditional System Design
Platform HW Dev. SW Dev. App. Dev. Prototype Board
+ BSP
Board
3
• Hardware first approach
• Platform is defined by architect or based on legacy
• Designers develop and verify RTL model of platform
• Slow error prone process
• SW development after HW is finalized
• Debugging is complicated on the board due to limited observablity
• HW errors found during SW development are difficult to rectify
• Application is ported after system SW is finalized
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 4 Chapter 4: System Synthesis
Virtual Platform based System Design
HW Dev.
Platform Platform
Modeling
Virtual
Platform Board
+ BSP
SW Dev.
App. Dev.
VP
Prototype
4
• Virtual platform (VP) is a fast model of the HW platform
• Typically an instruction set simulator or C/C++ model of the processor
• Peripherals are modeled as remotely callable functions
• Executes several orders of magnitude faster than RTL
• SW and HW development are concurrent
• VP serves as the golden model for both SW and HW development
• SW development can start earlier
• HW designers can use SW for realistic test bench for RTL
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 5 Chapter 4: System Synthesis
Model-based System Design
TLM
Gen. TLM
ASIC/
FPGA
Tools
Board
+ BSP
+ App
SW Gen.
HW Gen.
Prototype
Platform
C/MoC
Application
Developer
SW Decisions
HW Decisions
5
• Model based design gives control to application developers
• Application is captured as high level C/C++/UML specification
• Transaction level model (TLM) is used to verify and evaluate the design
• System synthesis
• The best platform for given application can be synthesized automatically
• For legacy platforms, application mapping can be generated automatically
• Cycle accurate SW/HW can be generated from TLM for implementation
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 6 Chapter 4: System Synthesis
Outline
• System design trends
• Model-based synthesis
• Transaction level model generation
• Application to platform mapping
• Platform generation
• Cycle-accurate model generation
6
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 7 Chapter 4: System Synthesis
Model Based Synthesis
System Synthesis
Cycle-accurate SW/HW Synthesis
TLM
CAM
Specification
TLM TLMs
Component
Models
Component
Library
• Synthesis of cycle-accurate model (CAM) from specification
• Process may be divided into several steps
• Specification is defined as application model and design constraints
• Several intermediate models, such as TLMs, may be used
• Platform component models are needed for TLM generation
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 8 Chapter 4: System Synthesis
System Synthesis Inputs and Output
• Inputs
• Application Model
– Purely functional model
– Specified in a given model of computation (Stateflow, dataflow, CSP, MP)
• Component Models
– Data models of configurability and metrics
– Functional models of component services
– Examples: HW IP models (Processor, Peripheral, Bus), SW IP models
(RTOS, Drivers)
• Constraints
– Bounds on metrics (Performance, area, power, reliability, security)
– Optimization goal as a cost function of metrics
• Output
• TLM of application mapped to HW/SW platform
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 9 Chapter 4: System Synthesis
Three Models with Respect to OSI (Ref. Chapter 3)
Cycle Accurate Model
Transaction Level Model
Specification Model
7 . Application
6 . Presentation
5 . Session
4 . Transport
3 . Network
2 b . Link + Stream
2 a . Media Access Ctrl
2 a . Protocol
1 . Physical
7 . Application
6 . Presentation
5 . Session
4 . Transport
3 . Network
2 b . Link + Stream
2 a . Media Access Ctrl
2 a . Protocol
1 . Physical
Address lines
Data lines
Control lines
TLMs
Spec
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 10 Chapter 4: System Synthesis
Outline
• System design trends
• Model-based synthesis
• Transaction level model generation
• Application to platform mapping
• Platform generation
• Cycle-accurate model generation
10
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 11 Chapter 4: System Synthesis
Synthesis Case 1: Fixed Platform and Mapping
• Initial platform and mapping are given
• Optimization tools may modify spec under given constraints
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 12 Chapter 4: System Synthesis
Tool support for Synthesis Case 1
• GUI for application specification
• GUI for platform specification
• GUI for application to platform mapping
• TLM generation tool
• TLM-based metric estimation tools
• Constraint-based spec optimization tools
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 13 Chapter 4: System Synthesis
Input: Application Model
v1
C1
P1 P2
P3 P4
C2
13
• Application model consists of • Processes for computation (eg. P1, P2, P3, P4)
• Channels for communication (eg. C1 between P1 and P3)
• Variables for storage (eg. v1)
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 14 Chapter 4: System Synthesis
Application Model Objects
• Processes • Symbolic representation of computation
• Contain C/C++ code imported from reference
• Process ports • Symbolic representation of communication
services required by processes
• Provide object orientation by allowing processes to connect to different channels
• Channels • Symbolic representation of inter-process
communication
• Implement communication services such as blocking, non-blocking, handshake, FIFO etc.
• Encapsulation for communication functions
• Variables • Symbolic representation of data storage
14
v1
C1
P1 P2
P3 P4
C2
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 15 Chapter 4: System Synthesis
Input: Platform Architecture
TX
CPU1 Mem
HW CPU2
Arb
iter
Bus1 Bus2
OS2
OS1
15
• Platform consists of • Hardware: PEs (eg. CPU1, HW), Buses (eg. Bus1), Memories
(eg. Mem), Interfaces (eg. Transducer)
• Software: Operating systems (eg. OS1) on SW PEs
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 16 Chapter 4: System Synthesis
Platform Objects
• Processing element (PE) • Symbolic representation of computation resources
• Different types such as SW processors, HW IPs etc.
• Bus • Symbolic representation of communication media
• Types include shared, point-to-point, link, crossbar etc.
• Memory • Symbolic representation of physical storage
• May contain shared variables or SW program/data
• Transducer • For protocol conversion and store-forward routing
• Necessary for PEs with different bus protocols
• Operating system (OS) • Software platform for individual PEs
• Needed for scheduling multiple processes on a PE
16
TX
CPU1 Mem
HW CPU2
Arb
iter
Bus1 Bus2
OS2
OS1
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 17 Chapter 4: System Synthesis
Input: Mapping
TX
v1
C1
P1 P2
CPU1 Mem
HW IP
P3
CPU2
P4
C2
Arb
ite
r
Bus1 Bus2
OS
OS
17
• Processes PEs
• Channels Routes
• Variables Memories
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 18 Chapter 4: System Synthesis
Mapping Rules
• Processes to PEs • Each process in the application must be mapped to a PE
• Multiple processes may be mapped to SW PE with OS support
• Example: P1, P2 CPU1
• Channels to Routes • All channels between processes mapped to different PEs are
mapped to routes in the platform
• Route consists of bus segments and interfaces
• Channel on each bus segment is assigned a unique address
• Variables to Memories • Variables accessed by processes mapped to different PEs are
mapped to shared memories
• All variables are assigned an address range depending on size
18
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 19 Chapter 4: System Synthesis
Computation Timing Estimation
• Stochastic memory delay model
• DFG scheduling to compute basic block delay [DATE 08]
• RTOS model added for PEs with multiple processes
Timing Estimation
Timed Process
Processor Model
const
status
RF
OR
ALUAR
MemDR
offset
CMem
CW
PC
AG P
bL
Sum
Add
aL
Mul
wait(t1)
BB1
If
If Y N
Y N
BB2 BB3
wait(t2) wait(t3)
Process CDFG
BB1
If
If Y N
Y N
BB2 BB3
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 20 Chapter 4: System Synthesis
Stochastic Memory Delay Model
Mem. Overhead= 4.1 Branch Delay= 1.2
• Assumption • Cache and branch prediction hit rate available in data model
• Delay Estimation • Operation access overhead = N
op * ((1.0 – HR
i) * (CD + L
mem))
• Data access overhead = Nld * ((1.0 – HR
d) * (CD + L
mem))
• Branch prediction miss penalty = MPrate
* Penalty
Cache
D-Mapped
16K
Icache: 97.79%
Dcache: 69.96%
Delay : 1
Memory
Delay: 8
BrPredictPolicy: Taken
Penalty : 260.00%
Memory/Branch Model
Mem./Br. Delay Calcutation
1: a = $i - 1 2: t1 = a + 2 3: t2 = $n * $m 4: t3 = t1 - t2 5: load b 6: t4 = b / 10 7: jmp
LLVM Bytecode
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 21 Chapter 4: System Synthesis
Pipeline Scheduling
1: a = $i - 1 2: t1 = a + 2 3: t2 = $n * $m 4: t3 = t1 - t2 5: load b 6: t4 = b / 10 7: jmp 8: wait 47*CT
• Assumptions • In-order, single issue processor
• Optimistic during scheduling (100% cache hit)
Operations Datapath
Processor Data Model
Add
IF
ID
EX: int-ALU IntAdd
Sub
IF
ID
EX: int-ALU IntSub
Int-ALU
Qty: 1
IntAdd IntSubLat: 1 Lat: 1
Processor Timing Estimation
LLVM Bytecode
Operation delay= 42
Total BB delay=
Op.+Mem.+Br. =
47.3 cycles
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 22 Chapter 4: System Synthesis
Communication Timing Estimation
PE1 p1 p2
Tx1
PE3
Tx3
PE4
Application + Platform
Untimed Bus1
Protocol Model
Estim
atio
n E
ng
ine
Timed Bus1
Bus1
PE2
Bus2
Tx2
Bu
s3
• Protocol model used to estimate synchronization, arbitration and transfer
• Timing is annotated in bus channel
Write( ) {
Get_Bus( );
Transfer( );
Release_Bus( );
}
Write( ) {
Get_Bus( );
wait (t1);
Transfer( );
wait (t2);
Release_Bus( );
wait (t3);
}
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 23 Chapter 4: System Synthesis
Output: SystemC Timed TLM
Bus1
P1 P2
OS
CP
U1
Mem
CPU2
P3
HW IP
Bus2
TX
TLM Generation Technique
• Application code sc_thread
• Processing element sc_module
• OS Model sc_module
• Bus sc_channel
• Memory Array inside sc_module
• Interface FIFO channel+sc_process
P4
OS
23
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 24 Chapter 4: System Synthesis
Outline
• System design trends
• Model-based synthesis
• Transaction level model generation
• Application to platform mapping
• Platform generation
• Cycle-accurate model generation
24
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 25 Chapter 4: System Synthesis
Application to Platform Mapping
• Mapping is derived from Application and Platform
• Optimization loop is driven by estimation results and constraints
Chapter 4 System Synthesis
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 26 Chapter 4: System Synthesis
Application Example
Encoder
Update
Codebook
Search
Closed-loop
Pitch search
Open LoopLP_Analysis
2 s
ub
fra
me
s2x p
er
fra
me
• GSM Encoder
• Compresses raw speech data frame-by-frame
• Over 10K lines of C code in specification
• 5 top level functions: LP, OP, CL, CB, UP
• Contains if-then-else and loop control flow
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 27 Chapter 4: System Synthesis
Profiling
• Given input MoC, profile application for:
• Computation
– Number of operations (size)
– Operations type per data type and frequency
of use
– Concurrency between modules and
dependency
• Communication
– Volume, frequency of communication between
modules
– Timing dependency
– Latency requirements
• Storage
– Instruction size
– Variable size
Profiling
Profiled App.
Simulation
Instr. Appl
Static Analysis
Basic Block
Counters
Instrumentation
Application
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 28 Chapter 4: System Synthesis
Profiled Statistics
(*, int),
46.20%
(+, int),
33.50%
(/, int),
9.10%
others,
4.10%
Encoder
8,802
272
79,544
69,112
0
163
Update
43.6MOp
Codebook
646.5MOp
Closed-loop
478.7MOp
Open Loop
337.1MOp
LP_Analysis
377.0MOp
2 s
ub
fra
me
s2x p
er
fra
me
31
5,5
68
• Profiling helps select the appropriate components for
implementation
• All fixed point ops No need for processors with floating point units
• Large number of multiplications Processor with HW multiplier is ideal
• CB is most computationally intensive Ideal for custom HW mapping
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 29 Chapter 4: System Synthesis
Application Graph
LP
377
OP
337
CL
479
UP
44
CB
647
8.8
69
80
0.16
0.27
320
Encoder
8,802
272
79,544
69,112
0
163
Update
43.6MOp
Codebook
646.5MOp
Closed-loop
478.7MOp
Open Loop
337.1MOp
LP_Analysis
377.0MOp
2 s
ub
fra
me
s2x p
er
fra
me
31
5,5
68
• Profile information is abstracted into a simplified graphical
representation for synthesis algorithms
• Node tags = number of operations in the process (#ops) in millions
• Edge tags = kilobytes transferred between the processes
• Control dependencies are excluded for simplicity
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 30 Chapter 4: System Synthesis
Platform Connectivity Graph
Inte
rfa
ce
CPU Mem
HW IP DSP
Arb
ite
r
Bus1 Bus2
M
M
S
S S
CPU
150
HW
200
DSP
100
• Platform architecture is abstracted into a connectivity graph
showing possibility of inter-PE communication
• Node label = PE name
• Node tag = estimated computation speed of the PE in Million of
Operations per second (Mops)
• Edge implies a communication path between PEs
• No edge between HW IP and DSP due to missing DMA on Bus1
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 31 Chapter 4: System Synthesis
Load Balancing (LB) Algorithm
• Greedy heuristic to map processes to least busy PEs
• PE load = total time PE will be busy executing the mapped
processes
• Defined as ∑#ops(p) / Speed (PE), for all p mapped to PE
• Does not account for any communication time!
• Feasibility list defined for each process
• The set of PEs to which a process can be mapped such that the process’
communication requirements are not violated
• Let processes p & q are have an edge in the application graph
• Let q be already mapped to PE’
• PE is in feasible(p) if there exists edge (PE, PE’) in platform graph
• Basic idea
• Map processes to least loaded feasible PE in decreasing order of #ops
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 32 Chapter 4: System Synthesis
LB Algorithm in Action
LP
377
OP
337
CL
479
UP
44
CB
647
8.8
69
80
0.16
0.27
320
(a) Application graph
(b) Platform connectivity graph w/ mapping
CPU
150
HW
200
DSP
100 CB,UP
CL, LP
OP
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 33 Chapter 4: System Synthesis
Longest Processing Time (LPT) Algorithm
• Drawbacks of LB
• Does not account for communication
• May not terminate with a mapping if feasibility list is empty
• LPT accounts for communication and always produces a mapping
• Fully connected platform
• DMA is added to allow HW peripherals to communicate with
processes and memories
• No need to evaluate feasibility of mapping
• Cost of mapping process to PE is defined
• Includes both communication and computation time
• Basic idea
• Map processes to least cost PE in decreasing order of #ops
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 34 Chapter 4: System Synthesis
LPT Cost Function
• E(p, PE): Estimated time for running p on PE
• Mops(p) / Speed (PE) + time to send data to mapped processes
• C(p, PE) = T(PE) + E(p, PE) – SystemEndTime
• PE with lowest execution time may not have the lowest cost
• E(p, PE3) > E(p, PE2), but C(p, PE3) < C(p, PE2)
= max (T(PE), for all PEs)
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 35 Chapter 4: System Synthesis
New Connectivity Graph of Updated Platform
• Platform architecture is abstracted into a connectivity graph
• Node label= PE name, Node tag= estimated PE speed in Mops
• Edge = Connectivity between PEs
• Edge label = effective transaction speed between PEs in Kilobytes per
second (Kbps): added for LPT algorithm
Inte
rfa
ce
CPU Mem
HW DSP
Arb
ite
r
Bus1 Bus2
M
M
S
S S
CPU
150
HW
200
DSP
100
300 200
100
DMA
M
Edge possible due to DMA
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 36 Chapter 4: System Synthesis
LPT Algorithm in Action
LP
377
OP
337
CL
479
UP
44
CB
647
8.8
69
80
0.16
0.27
320
(a) Application graph
(b) Platform connectivity graph w/ mapping
CPU
150
HW
200
DSP
100
CL, UP
LP
300 200
100 CB
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 37 Chapter 4: System Synthesis
Outline
• System design trends
• Model-based synthesis
• Transaction level model generation
• Application to platform mapping
• Platform generation
• Cycle-accurate model generation
37
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 38 Chapter 4: System Synthesis
Platform Generation
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 39 Chapter 4: System Synthesis
Component Database
PE Type Cost Speed Capacity
(Speed *6 sec)
CPU 2 100 600
DSP 1 50 300
HW 5 200 1200
• Timing constraint: Application must complete in <6 seconds.
• Database of processing elements used for component selection
• Characterized by type, cost and speed
• Cost includes IP licensing, development, manufacturing etc.
• PE Computation Capacity = PE speed (in Mops) * timing constraint
• Indicates number of operations (in millions) that may be mapped to a
PE while still meeting the timing constraints
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 40 Chapter 4: System Synthesis
Platform Generation Algorithm
• Greedy heuristic to minimize cost and meet timing constraint
• PE slack
• Capacity remaining on the PE
• Slack(PE) = Capacity(PE) – (∑#ops(p), for all p mapped to PE)
• Closeness factor of a process p to a PE
• Total communication data between p and all processes mapped to PE
• C(p, PE) = ∑ (Edge-weight(p, q) in app. graph), for all q mapped to PE
• Basic idea
• Iterate over processes (p) with in decreasing order of #ops
• Update slacks of allocated PEs
• Map p to closest PE with Slack(PE) ≥ #ops(p)
• Allocate least cost PE with Capacity ≥ #ops(p) if mapping fails
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 41 Chapter 4: System Synthesis
Platform Generation Algorithm in Action
LP
377
OP
337
CL
479
UP
44
CB
647
8.8
69
80
0.16
0.27
320
(a) Application graph
(b) Generated Platform w/ mapping
HW
200
CPU
100
DSP
50
CB,CL, UP
LP
OP
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 42 Chapter 4: System Synthesis
Outline
• System design trends
• Model-based synthesis
• Transaction level model generation
• Application to platform mapping
• Platform generation
• Cycle-accurate model generation
42
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 43 Chapter 4: System Synthesis
CAM Generation
SystemC TLM
CRTL SW/RTOS
Library
Interface
Synthesis
SW
Synthesis
RTL IP
Library
Binary HW RTL IF RTL
OR Bus
Library
Pin/Cycle Accurate Model (PCAM)
Generator
C/Verilog CAM FPGA
Tools
Prototype
CA Sim.
Tools
43
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 44 Chapter 4: System Synthesis
P4
OS RTOS/
Driver
Synthesis
Compile
Cycle-Accurate Software Synthesis (Chapter 5)
Bus1
CP
U1
HW IP CPU2
Bus2
Compile
RTOS/
Driver
Synthesis
HAL RTOS
EXE P2
OS
HAL TX
Program
P1
HAL RTOS
EXE
Program
44
• Processes Compiled App.
• OS model Real OS
• HAL model Real HAL
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 45 Chapter 4: System Synthesis
Cycle-Accurate Hardware Synthesis (Chapter 6)
Bus1
CP
U1
Mem
Processes in C HW IP (RTL)
Cycle-
accurate
Synthesis
Bus2
CPU2
P3
TX
45
• Process Synthesizable RTL
• High level synthesis for custom
• Replacement for HW IP
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 46 Chapter 4: System Synthesis
Cycle-Accurate Interface Synthesis (Chapter 7)
CPU1 Mem
TX
HW IP
Interface Synthesis
CPU2
Arbiter
IC
46
• Sync. Model Interrupts
• Bus channel Arbiter + Signals
• Interface model RTL
• Channel access PE interface
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 47 Chapter 4: System Synthesis
Cycle-Accurate Model
CP
U1
Mem
Interface
HW IP
Arbiter
HAL RTOS
EXE
PCAM is downloaded
automatically for fast
prototyping with FPGAs or
simulated using validation tools
IC
Program
HAL RTOS
EXE
Program
CPU2
47
Embedded System Design © 2009: Gajski, Abdi, Gerstlauer, Schirner
9/29/2011 48 Chapter 4: System Synthesis
Summary
• Emergence of model-based system design
• Virtual platforms replace prototypes for early SW development
• Increasing adoption of TLMs for SW/HW design
• Challenges for synthesis of large system designs
• Manual model development is time consuming and error-prone
• Different platforms are needed for different application domains
• Mapping application to a multi-core platform is complicated
• Need for well defined model semantics is needed at TLM and cycle-accurate levels
• Enables automatic TLM generation
• System synthesis becomes possible
• Future of system synthesis
• Based on formalized system level models such as TLM
• Automatic mapping of application to platform
• Automatic generation of application specific platforms
48
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