Embedded System Design - Lecture 6

8/6/2019 Embedded System Design - Lecture 6

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Lecture 6


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F ree-Run Timer TMR0

Physically, TMR0 timer is a register whose value iscontinually increasing to 255, and then it starts all over again. 0, 1, 2, 3, 4...255....0,1, 2, 3......etc.After each count up to 255, TMR0 resets its value tozero and starts with a new cycle of counting to 255.During each transition from 255 to zero, T0IF bit inINTCOM register is setIf interrupts are allowed to occur, this can be taken

advantage of in generating interrupts and in processinginterrupt routineIt is up to programmer to reset T0IF bit in interruptroutine, so that new interrupt, or new overflow could bedetected


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TMR0 Timing

TMR0 is readable and writableMOVF TMR0,0

MOVWF TMR0

If TMR0 register is written, the increment isinhibited for the following two cycles


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TMR0 Clock Source

Beside the internal oscillator clock, timer statuscan also be increased by the external clock onRA4/TOCKI pin.

This is done by setting the T0CS bit(OPTION_REG).


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Rising or Fa lling Edge Triggering

If external clock on RA4/TOCKI pin is used, it is possible to define the edge of a signal (rising or falling), on which timer would increase its value.

The edge is determined by T0 source edge select bit, T0SE (OPTION_REG)Clearing bit T0SE selects the rising edge


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Exercise

W rite a program to sent a 0xFF to Port B after every 1s. Assume that you have a 250Hz clock atRA4/TOCKI pin.


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P resc a ler

The 8- bit Prescaler divides oscillator clock before it will reach logic that increases timer status

The highest divisor is 25 6 . This actually meansthat only at every 25 6 th clock, timer value wouldincrease by one

For example, if the TMR0 prescaler is set todivide - by - 4 and the PIC is running at 4 MHz, the prescaler will send a 250 KHz clock to theTMR0 register.


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P S2: P S0

The prescaler is not readable or writable.The prescale value is defined through first three bits inOPTION register


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P resc a ler Assignment

The prescaler is shared between TMR0 andW DTIt is mutually exclusive between TMR0 and

W DT A prescaler assignment for TMR0 means that there is

no prescaler for W DT, and vice - versa

The prescaler assignment is controlled by control bit PSA (OPTION_REG)


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Cle a ring P resc a ler

W hen assigned to TMR0, all instructions writingto TMR0 (e.g., CLRF 1, MOV W F 1, BSF 1,x....etc.) will clear the prescaler.

W hen assigned to W DT, a CLR W DT instructionwill clear the prescaler along with W DT


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TMR0 Ex a mple

Example showing how to initialize timer to signalfalling edges from external clock source with a prescaler 1:4.


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TMR0 Interrupt

TMR0 interrupt is generated when the TMR0register overflows from 0xff to 0x00This overflow sets the T0IF bit (INTCON).

The interrupt can be masked by clearing enable bit T0IE (INTCON).The T0IF bit must be cleared by the TMR0interrupt service routine before re - enabling this

interrupt.TMR0 interrupt cannot wake the processor upfrom SLEEP since the timer is shut off duringSLEEP.


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Ex a mple

Example showing how to initialize timer tosignal falling edges from external clock sourcewith a prescaler 1:4


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Interrupts


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P olling

There are 2 main ways for external I/O devices tocommunicate with the u controller Polling andInterruptIn polling, the u controller periodically queryinput devices to see if data is available The u controller first stops processing its main

program and enters the polling routine The I/O device is then queried for data. If there is data, the service routine is executed W hen the device has been serviced, the u controller

resumes its main program


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P olling

Polling can effectivelyassign priorities amonginput devices by querying

the highest priority devicefirst


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Exercise

Given that 3 devices (A, B and C) are connectedto RB0, RB1 and RB2, write a program to pollthe devices. If any of the devices is activated, call

the XYZ subroutine. The priority for the devicesare A, B then C.


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Interrupts

For the interrupt method, I/O devices issue asignal (interrupt) to the u controller when thedevice needs to be servicedThe interrupt request can come at any timeduring the execution of a programThe interrupt forces a call to the servicesubroutine which is usually referred to as an

interrupt service routineOn interrupt, the processor saves the returnaddress on the stack and program control isredirected to the interrupt service routine


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Interrupts

An interrupt in its simplest form is like ahardware triggered subroutine.

INT

16 F8 4

Main Program

InterruptInterrupt Service

Routine

retfie


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P eripher a l Interrupt Vector

The microcontroller needs to be told where the interruptservice routine is locatedIt does this by looking to the

peripheral interrupt vector (0x0004).This location informs theCPU where the interruptservice routine is located.Reset directs program flowto location 000HInterrupt direct program

flow to location 004H


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P rogr a m using Interrupts

A program using interrupts is usually structured asfollows:

org 000H ;Reset directs program to here

goto MAINorg 004H ;Interrupt directs program to heregoto INT_SERV

MAIN: ; Your main program

INT_SERV:; Your interrupt service routine


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Sav ing Register D a taW

hen an interrupt occurs (it can happen at any time), itis wise to save the contents of both the STATUS and theW register This is trickier than it might appear.Note that instruction MOV W F does not affect any status

bits. Thus, the W register is easily saved; MOVWF W_SAVE

But, saving STATUS involves moving it to W andunfortunately, MOVF STATUS, W will change status

bits.However, S W APF STATUS, W doesn't. Thus, theSTATUS register may be saved.

SWAPF STATUS, W

MOVWF STATUS_SAVE


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Sav ing a nd Restoring W


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Sources of Interrupts

PIC16 F8 4 has 4 sources of interrupt: External interrupt RB0/INT pin Timer overflow interrupt

Port B interrupt on change (pins RB7

:RB4) EEPROM write complete interrupt

These interrupts are disabled/enabled through theinterrupt control register (INTCON)


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The Interrupt Control Register

The interrupt control register (INTCON) Contains the individual and global interrupt enable

bits Records individual interrupt requests in flag bits.

The global interrupt enable bit (GIE)enables/disables all interrupts

B SF INTCON, GIE ; enable all interruptB CF INTCON, GIE ; disable all interrupt

On RESET, the GIE bit is cleared


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Indi v idu a l Interrupt En ab le Bits

Individual interrupts can also be enabled or disabledthrough their corresponding enable bitsB SF INTCON, INTE ;enable R B 0/INT interruptB SF INTCON, R B IE ;enable R B 4-7 change interruptB SF INTCON, TOIE ;enable timer interrupt

Any of these may be used alone, or several sources may be enabled, depending on your application.At any time in the program, the user may turn any of thesources off by clearing these mask bits;

B CF INTCON, INTEB CF INTCON, R B IEB CF INTCON, TOIE

On RESET, these bits are cleared.


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Interrupts (INTCON) Register 76


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Interrupt F la g Bit

On interrupt, a flag bit associated with the type of interrupt is set by the processor.These flag bits are used to determine the source of the interruptand perform the appropriate action


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Interrupt P rocedure

W hen an interrupt occurs: GIE bit is cleared to disable any further interrupt. Return address is pushed onto the stack.

Program counter is loaded with 0x0004 Once in the interrupt service routine, the source(s) of

the interrupt can be determined by polling theinterrupt flag bits

The GIE bit is again set on execution of the returnfrom interrupts (RETFIE)


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Interrupt P rocedure

The occurrence of an interrupt event sets the flag bit (if GIE and the mask bit are set)It is the user's responsibility to clear the flag bit withinthe service routine

B CF INTCON, INTF ; clear external INT flagB CF INTCON, R B IF ; clear R B 4 - R B 7 interrupt flagB CF INTCON, TOIF ; clear timeout flag

Failure to clear the flag bit is interpreted by the processor as "a previous interrupt occurred, but the user has yet to service the interrupt".Thus, although an interrupt event may occur, GIE may

be enabled and a mask bit may be set, the actualinterrupt will not occur unless the corresponding flag bitis clear


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Interrupt Ex a mple 7 9


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INT Interrupts

The INT interrupt is an external interrupt on RB0/INT pinIt is edge triggered: either rising if INTEDG bit(OPTION< 6 >) is set or falling if INTEDG is clear W hen a valid edge appears on the RB0/INT pin theINTF bit (INTCON) is setThis interrupt can be disabled by clearing control bit

INTE (INTCON)The INT interrupt can wake the processor from SLEEPonly if the INTE bit was set prior to going into SLEEP.


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Exercise

W rite a program to count the number of positivetransitions on input RB0/INT. Display the lasttwo bits of the count on 2 LEDS connected toRB 6 and RB 7 .


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Ex a mple: Cont.INT_SERV:

INCF COUNTER, F

B TFSS COUNTER, 0B CF PORT B , 6B TFSC COUNTER, 0B

SF PORTB

, 6B TFSS COUNTER, 1B CF PORT B , 7B TFSC COUNTER, 1B SF PORT B , 7B CF INTCON, INTF ; clear the appropriate flagRETFIE ; this also set global interrupt enable

END


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TMR0 Interrupts

The TMR0 interrupt is triggered by an overflow(0xff to 0x00) in TMR0The overflow sets the flag bit TOIF

(INTCON)The interrupt can be enabled/disabled bysetting/clearing enable bit TOIE (INTCON).


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Exercise

Using interrupt, write a program to sent 0xFF toPort B after approximately 1s. Assume that youhave a 1KHz clock at RA4/TOCKI pin.


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P ORT RB Interrupts

PORT RB Interrupt is triggered by input changeson portb< 7 :4>The interrupt sets the flag bit RBIF

(INTCON)The interrupt can be enabled/disabled bysetting/clearing enable bit RBIE (INTCON).

This interrupt is useful for a keypad interface.

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Embedded System Design - Lecture 6