Embedded System Design-Presentation

8/3/2019 Embedded System Design-Presentation

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Embedded System Design

By

Dr K A Radhakrishna RaoProf in E & C Engg


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Typical Embedded System

Memory (EmbeddedFirmware)

Communication

System Core

(MP,MC,DSP,ASIC,PLD,

COTS)

Interface (USB,RS232)

O/P

Ports(Actuators)

Other supporting Ics,

Subsystems

I/P Ports

(sensors)


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System core

Microprocessor (Intel 8085)

Microcontroller(AT89C51) x nx

Spartan)

Digital Signal Processor (DSP) (Blackfin processors)

Application Specific Integrated Circuit (ASIC)/Application Specific Standard Product (ASSP)

(ADE7760 Single phase Energy Metering IC)


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Embedded system viewed as REACTIVE system

REACTIVE system is one which responds to an input.

Embedded systems are basically designed to regulate a

physical variable or to manipulate the state of some

devices by sending some control signals to the Actuators

or devices connected to the O/p ports of the system, in

response to the input signals provided by the end users

or the sensors which are connected to the I/p port.


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Common User Interface (I/O ports):

Input devices Key boards, push-button switches

Output devices Buzzers, LED, LCD

Not allNot allNot allNot all iiii/p and o/p devices are used with any/p and o/p devices are used with any/p and o/p devices are used with any/p and o/p devices are used with anyembedded system, it is only application dependent.embedded system, it is only application dependent.embedded system, it is only application dependent.embedded system, it is only application dependent.

egegegeg. Mobile applications requires keyboard & screen. Mobile applications requires keyboard & screen. Mobile applications requires keyboard & screen. Mobile applications requires keyboard & screen

Embedded systems could be automaticEmbedded systems could be automaticEmbedded systems could be automaticEmbedded systems could be automatic i.ei.ei.ei.e wholewholewholewholeprocess of control and monitoring could beprocess of control and monitoring could beprocess of control and monitoring could beprocess of control and monitoring could beautomated.automated.automated.automated.


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Communication Interface: Serial and parallel devices such as USB, DB9, parallel

port and RS 232.

Communication interface devices providesconnect v ty w t ot er ev ces or systems.

Memory: Responsible for holding control algorithm and other

configuration details Typical memory types are OTP, PROM, UVPROM,

EEPROM and FLASH


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Core of the Embedded System

1. General purpose and Domain Specific Processors Microprocessors

Microcontrollers

Digital Signal Processors

2. Application Specific Integrated Circuits (ASIC)

3. Programmable Logic Devices (PLDs)

4. Commercial off-the- shelf Components(COTS)


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General purpose and Domain Specific Processors Microprocessors typically consists of CPU which internally contains

ALU, control unit and working registers.

It requires supporting chips to be fully functional

Intel 4004 (4-bit processor) , Intel 4040 (advanced features incomparison to 4004),Intel 8008(similar to 4040 but with 14 bit PC),

-, - ,version additional instructions, interrupts, power supply of +5V) ,Z80(concept of register banking by doubling register set)

16, 32 and 64 bit processors, clock speed drastically raised, morecompetitors in the market, low cost and low power issues addressed)

Intel, AMD, Freescale, IBM, TI, Cyrix, Hitachi, NEC, LSI logic are keyplayers

Harvard and Von-Neumann are the two common architectures forprocessor design


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General Purpose Processor (GPP) vs Application Specific Instruction Set Processor (ASIP)

GPP meant for general computational tasks (Pentium 4/AMD

Athlon, etc) Produced in lar e uantit

ASIP are processors with architecture and instruction setoptimized to specific-domain/application requirements likenetwork processing, automotive, telecom, mediaapplications, DSP, control applications

ASIP fill the architectural spectrum between general purposeprocessors and ASICs.

Most of the Embedded systems are built around ASIPs


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Microcontrollers: Highly integrated containing CPU, scratch pad RAM, special and general

purpose register arrays,on chip ROM/FLASH memory for program storage,timer and interrupt control units and dedicated I/O ports.

Super set of microprocessors

More suitable for Embedded systems Cheap, cost effective and readily available

TI 1000 rst m crocontro er , Inte MCS-48 am y(8038HL,8039HL,8040HL,8048HL,8049AH)

8051 most popular MC. PIC form Microchip Technologies is equally popular. Itis a high performance RISC microcontroller complementing CISC features of8051.

ARM 11 series provides solution to applications requiring hardware

acceleration and high processing capability. Freescale, NEC, Zilog, Hitachi, Mitsubishi, Infineon, ST Electronics, National, TI,

Toshibha, Philips, Microchip. Analog Devices, Daewoo, Intel, Maxim, Sharp,Silicon Laboratories, TDK, Triscend, Winbond, Atmel are the key players inMicrocontroller market.


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Digital Signal Processors:

Dedicated hardware to address signal processing tasks

Speed not just dependent on clock used but on the specific

hardware u p y ccumu a on n one c oc cyc e

Harvard architecture (separate Data and Program memory)

Audio video signal processing, telecommunication and

multimedia applications are typical examples where DP is

involved.

Blackfin from Analog Devices and TMS series from TI are

typical DSPs.


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RISC or CISC

RISC (Reduced Instruction Set Computer)

CISC (Complex Instruction Set Computer)

having only 32 instructions

Example of CISC: AT89C51 having 255 instuctions

Note: It is not just number of instructions whichdetermine the processor to be RISC or CISC, thereare many other criteria.


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RISC CISC

Lesser no. of instructions Greater no. of instructions

Instruction pipelining and execution

speed

Generally no instruction pipelining feature

Orthogonal instruction set Non-orthogonal instruction set

Operations are performed on registers

only, memory operations restricted to

load and store

Operations are performed on registers

and memory depending on instruction

A large number of registers are available Limited no. of general purpose registers

Longer code length to execute a task Shorter code length to execute a taskSingle, fixed length instructions Variable length instructions

Less silicon usage and pin count More silicon usage

Harvard architecture Can be Harvard or Von-Neumann


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Harvard vs Von-Neumann

I/O CPU Memory

Single shared bus

Program

Memory CPUData

Memory


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Harvard Architecture Von-Neumann Architecture

Separate buses for instructions and data

fetching

Single shared bus for instructions and

data fetching

Easier to pipeline thus high performance Low performance

No memory alignment problems Allows self modifying codesSelf-modifying code is a code/instruction which modifies itself

while execution

No chances for accidental corruption of

PM as it is separate from DM

Chances of corruption of PM


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Big Endian vs Little-Endian Processors/Controllers

Endianness specifies the order in which the data isstored in the memory by processor operations in a

multi byte system, Two ways of doing this are e n an: ower-or er y e o e a a s s ore n

memory at the lowest address, and the higher orderbyte at the highest address (The little end comes first)

Base Address +0 Byte 0 Byte 0 0x20000(Base Addr)

Base Address +1 Byte 1 Byte 1 0x20001(Base Addr+1)

Base Address + 2 Byte 2 Byte 2 0x20002(Base Addr + 2)

Base Address +3 Byte 3 Byte 3 0x20003(Base Addr + 3)


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Big Endian: Higher order byte of the data is stored

in memory at the lowest address, and the lower-

order byte at the highest address (The big end comes

first)

Base Address +0 Byte 3 Byte 3 0x20000(Base Addr)

Base Address +1 Byte 2 Byte 2 0x20001(Base Addr+1)Base Address + 2 Byte 1 Byte 1 0x20002(Base Addr + 2)

Base Address +3 Byte 0 Byte 0 0x20003(Base Addr + 3)


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Load Store Operation and Instruction

Pipelining

Load Store ArchitectureR1 R2 R3

ALU

xyz


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Load R1, x

Load R2,y

Load R3, R1, R2

Store R3, z

fetch-decode-execute

While decode-execute stage, next fetch can beoverlapped as memory address bus is free.

Fetch will go waste in case of present executeinstruction is branch or jump

Multiple levels of pipelining is possible.


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Application-Specific Integrated Circuits (ASICs) A microchip designed to perform a specific or unique application

Integrates several functions into a single chip and there bt=y reduces the systemdevelopment cost

Most of them are Proprietary products

As a single chip, ASIC consumes a very small area in the total system and therbyhelps design of smaller systems with high capabilities/functionalities

Pre-fabricated or custom fabricated using re-usable building block library ofcomponents for a particular customer application.

Profitable only in case of large volume commercial productions.

Non-refundable initial investment required Non Recurring Engineering Charge(NRE)

If NRE is borne by third party then ASIC is made openly available in the market,the ASIC is then referred to as Application Specific Standard Product (ASSP). TheADE 7760 Energy meter is one example.

Generally internal details of the chip are not revealed.


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Programmable Logic Devices

Logic devices performs specific logical functions

Logic devices are broadly classified as fixed and Programmble

PLDs offer customers a wide range of logic capacity, features, speed andvolatage-characteristics

These devices can be re-configured to perform any number of functions at.

PLD designers make use of inexpensive software tools to quickly develop,simulate, and test their designs. (eg., network router, a DSL modem, aDVD player, or an automotive navigation system)

There is no NRE costs and the final design is completed much faster than

that of a custom, fixed logic device Customers can change the circuitry as often during the design phase until

it operates to their satisfaction. This mainly due to its programmablenature on re-writable memory.


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Twp major types of PLDs are CPLDs and FPGAs.

FPGAs offers highest amount of logic density, the mostfeatures and the highest performance.

(ex. Xilinx Virtex line of devices, provides eight millionsystem gates)

These devices also offers features such as built-inhardwired processors, substantial amounts of memory,clock management systems and suport for many latest,very fast device-to-device signaling technologies.

FPGA are used in data processing and storage,instrumentation, telecommunication and signalprocessing applications.


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CPLDs offer much smaller amounts of logic-up

about 10,000 gates.

They offer very predictable timing

critical control applications. Ex., Xilinx

CoolRunner series

Low amounts of power, inexpensive.


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Advantages of PLD

More flexibility during design cycle

Do not require long-lead times for prototypes or

production parts

No large NRE charges on customers

Customer can order just the number of parts theyneed, when they need them, allowing them to

control inventory PLDs can be reprogrammed even after a piece of

equipment is shipped to a customer.


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Commercial Off-the-Shelf Components(COTS)

COTS product is one which is used as-is

These are designed in a such a way to provide easy integration andinteroperability with existing system components.

COTS component itself can be developed around a general purpose or

domain specific processor or an ASIC or a PLD.. , ,

plug-in module (WIZnet, Freescale, Dynolog)

Major advantage is that they are available in the market, cheap anddeveloper can cut his cost

Identifying proper COTS is the task and provide the plug-in option on the

board. There is no operational and manufacturing standards among the vendors

Major disadvantage is that manufacturer withdraws the COTS componentany time.


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MEMORY

On-Chip , Off-chip and working Memory

Program Storage memory (ROM)

Different types of ROM used in storing program

codes are Flash, NVRAM,PROM(OTP), Masked

ROM (MROM), EPROM, EEROM

Program storage memory is non-volatile


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Masked ROM (MROM): It is a one-time programmable device

Makes use of hardwired technology for storing the data. Device isfactory programmed by masking and metallisation process at the timeof production itself.

It is low cost for high volume production ec an sms use w mas ng process

Creation of an enhancement or depletion mode transistor through channelimplant

By creating the memory cell either using a standard transistor or a highthreshold transistor. In the high threshold mode, the supply voltage requiredto turn ON the transistor is above the normal ROM IC operating voltage. This

ensures that the transistor is always off and the memory cell stores alwayslogic 0.

Major disadvantage is that there is no flexibility in modifying thefirmware once programmed.


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PROM:

Can be programmed by end user.

This memory has nichrome or polysilicon wirees. .

Programming the PROM is by selective

burning/blowing the fuses

Fuse not blown/burnt represent logic 1.Defaultlogic is 1

OTP can be programmed only once.


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EPROM: Flexible as it can be erased and reprogrammed

EPROM stores the bit information by charging the floating gate of anFET. EPROM programmer are used to store bit-information

High voltage is used to charge the floating gate.

Erasing is done by exposing quartz crystal window to UV rays. Entirememory s erase w en expose o rays or xe ura on

Erasing is a tedious and time-consuming process as it requires chip tobe taken out and exposed to UV rays for 20-30 mins.

EEPROM uses electrical signals at the register/Byte level to alter

They can be erased and reprogrammed in-circuit

Very flexible in terms of erasing and reprogramming Disadvantage is that it has limited capacity compared to standard

ROM


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FLASH Latest and most popular ROM technology

Variation of EEPROM technology

It combines the re-programmability of EEPROM and the high capacity ofstandard ROMs

FLASH memory is organised as sectors (blocks) or pages and storesinformation in an array of floating gate MOSFET transistors.

Erasing of memory can be done at sector or page level and should be donebefore re-programming

The typical erasable capacity of FLASH is 1000 cycles

W27C512 from WINBOND is an example of 64KB FLASH memory

NVRAM

Non Volatile RAM is random access memory with battery back-up. Contains static RAM and a minute battery for providing supply to the memory

in the absence of external power supply. Both are packed together in a singlepackage.

Life span is typically 10years.DS1644 from Maxim/Dallas is 32KB NVRAM


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Read-Write Memory/Random Access

Memory(RAM)

RAM is used as data or working memory. Both

.

accessing is random.

Static RAM (SRAM), Dynamic RAM (DRAM) and

Non-Volatile RAM (NVRAM) are major types.


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SRAM This stores data in the form of voltage and they are made

up of flip-flops.

This is fastest among the types of RAM.

In a typical implementation, a SRAM cell (storing one bitn orma on s rea se us ng s x rans s ors or

MOSFETs).

Four of the transistors are used for building the latch partof the memory and two for controlling the access.

SRAM is fast in operation due to its resistive networkingand switching capabilities.

Major disadvantage of SRAM are low-capacity and highcost.


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DRAM

Stores data in the form of charge.

It is made up of MOS transistor gates.

Since it is stored in the form of charge, it faces

leakage problem and calls for periodic refreshing.

Special DRAM controllers are used for periodicrefreshing (in milliseconds interval).


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Memory according to the Type of Interface

Parallel Interface(parallel data lines of processor

connected to data lines of memory)

2 -

Serial peripheral interface(SPI) [ 2+n line interface

where n stands for the total number of SPI bus

devices in the system] Single wire interconnection(ex Dallas 1-Wire

interface)


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Memory Shadowing Execution of program or configuration reading from ROM is generally slower

compared with that of RAM due to difference in memory accessing timings.

Memory shadowing is used to enhance program executing or configurationsetting.

Basic Input Output configuration ROM or simply BIOS is used to holdimportant hardware configuration setting of a system.

Data in the BIOS is usually read in the beginning and system is configuredaccordingly, it is time consuming process.

RAM is included behind the logical layer of BIOS at its same address as ashadow to the BIOS.

First step that happens during the boot up is copying the BIOS to theshadowed RAM and write protecting the RAM then disabling BIOS reading.

Non-volatile nature of RAM requires data to be in ROM and high accessingspeed of RAM helps one to speed up the process.


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Memory Selection for Embedded Systems No general rule

Application and situation dependent

Many factors influence while deciding on size and type of memory (Cost,mobility, power conservation)

Real time applications need separate consideration (RTOS selection, RAM andROM share, keeping image of Program in ROM while running the codes fromRAM)

Normally the binary code for RTOS kernel containing all the services is storedin a non-volatile memory (like FLASH) as either compressed or non-compressed data. During boot- up of the device the RTOS files are copied fromthe program storage memory and then loaded to the RAM for execution.

Always have buffer (extra) memory

Memory comes in definite sizes and near closest on higher end is chosen.

Choose total amount of memory based on address bus size.

NAND and NOR flash


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Sensors and Actuators Sensors are means of collecting physical status of the system and they are the

input to Embedded system

Actuators are the means of driving the control mechanism which itself iscontrolled by output of the embedded system .

Sensors and Actuators are not mandatory, it depends on the application

If the system is only designed for monitoring then there is no necessity ofactuators.

Sensor is a transducer that converts energy from one form to another for anymeasurement or control purpose.

Actuator is a form of transducer (mechanical or electrical) which convertssignals to corresponding physical action (motion).

Both sensors and actuators constitute part of I/O subsytem.

Both sensors and actuators are not directly connected to embedded system ,it is generally done through I/O interface which takes care of signal matchingetc..


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Light Emitting Diode(LED) It is a p-n junction diode

LED can be driven by Logic 0 or 1 level of the processor(source /sink option)

7-segment LED Display Contains 8 light emitting diode arranged in a special form

7 LEDs are used for displaying alpha numeric charactersand 1 used for decimal point display.

Common anode and common cathode LED display


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Optocoupler

It is a solid state device to isolate two parts of acircuit.

It combines LED and photo-transistor in a single

.

It is used in electronic circuits for suppressinginterference in data communication, circuit isolation,high voltage separation, simulataneous separation

and signal intensification An example for a optocoupler is MCT2M from

Fairchild semiconductors.


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Stepper Motor It is an Electro-mechanical device which generates

discrete displacement (motion) in response to dcelectrical signals.

Different in operation in comparison to normal dcmotor

It is continuous rotation in case of normal dc motorwhere as it discrete rotation for the applied dc inputin case of stepper motor.

Widely used in industrial embedded applications,robotics control systems, consumer electronicproducts.


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Based on the coil winding arrangements , a two-phasestepper motor is classified into: Unipolar

Bipolar

Unipolar has two windings per phase

The direction of rotation (clockwise or anticlockwise) iscontrolled by changing the direction of current flow

Current in one direction flows through one coil and

opposite in other coil Direction is changed by switching the terminals to which

the coils are connected


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A,B,C and D represent coils

Coils A and C carry current in opposite directions for

phase 1 (only one of them will be carrying current at

a time), similarly, B and D carry current in oppositedirections for phase 2.


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Bipolar

It has single winding per pahse

For reversing the motor rotation the current flow

Complex circuitry is required for current flow

reversal.


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The stepping of stepper motor can be

implemented in different ways by changing

the sequence of activation of the stator

.

Full step: Out of the two windings, only one

winding of a phase in energised at a time

Step Coil A Coil B Coil C Coil D

1 H H L L

2 L H H L

3 L L H H

4 H L L H


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Wave Step: Only one phase is energised at a

time and each coils of the phase is energised

alternatively


1 H L L L

2 L H L L

3 L L H L

4 L L L H


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Half Step: It sues combination of wave and full

step. It has the highest torque and stability.


1 H L L L

2 H H L L

3 L H L L

4 L H H L

5 L L H L

6 L L H H

7 L L L H

8 H L L H


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Two-phase unipolar stepper motors arepopular choise

Port pins of Microprocessor/microcontroller

ma not be able to drive the motors

Voltage requirement is in the range of 5 to 24volts

Drivers are needed, ULN2803 is a octalperipheral driver array available from ONsemiconductors and ST microelectronics


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Relays: It is a Electro-mechanical device

Dynamic path selector for signals and power

Magnetic field generated due to current flow attracts armature core

Most of the industrial relays are bulky and requires high voltage to

operate. Reed relays use low voltage DC which is used with ES


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A free-wheeling diode is used for free-wheeling the voltageproduced in the opposite direction when the relay coil is de-energised. The free wheeling diode is essential for protecting therelay and the transistor .


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Piezo Buffer It is a piezoelectric device for generating audio indications in

embedded application.

It contains piezoelectric diaphragm which produces audiblesound in response to the voltage applied to it.

Self drivin and External drivin are the two t es.

Self driving has all the necessary components to generatepredefined tone

External driving supports generation of different tones.

Tone can be varied by applying a variable pulse train to the

piezoelectric buffer. This can be directly interfaced to the port pin o fthe processor

Transistor drive circuit can be used in case of higher driverequirement.


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Push Button Switch Input device, Push to Make and Push to break are two types

Configured to used with LOW or HIGH

Key Board

Array of keys arranged in matrix form reat y re uces num er o nter ace connect ons ex to connect

16 keys, we need 16 port pins where as if it is arranged as 4x4then only 8 pins are needed)

Scanning technique is used to identify key pressing.

Rows are o/p ports and columns are i/p port. Sequentially each

row is pulled down and columns are scanned. De-bouncing is a standard problem. Hardware and Software

solutions are possible.


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Programmable Peripheral Interface (PPI)

Supports 24 I/O pins (I/O, Handshake, BSR modes)

Either used as three 8-bit I/O ports or two 8 bit

8 individual I/O pins

Two 4-bit ports

Control word defines roles of ports/pins


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Communication Interface

Communication interface is essential for

communicating with various subsystems of the

embedded s stem and with the external world

Two perspectives of communication interface with

embedded systems

Onboard communication interface (connecting onboard

components)

External communication interface(connecting outside

embedded system)


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Examples of Onboard communication interface are I2C, SPI, UART 1-Wire

External communication interface is responsible for data transferbetween the embedded system and other devices or modules. Thiscan be either wired or wireless media and it can be serial or

parallel. (ex Mobile communication equipment) n rare , ue oo , re ess - , a o requency

waves (RF), GPRS are exaples of wireless communication interface.

RS-232C/RS-422/RS-485, USB, Ethernet IEEE 1394 port, Parallelport, CF-II interface, SDIO, PCMCIA are examples for wiredinterfaces.

It is not mandatory that embedded system should contain anexternal communication initerface.


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Onboard Communication Interfaces Inter Integrated Circuit (I2C) Bus:

Synchronous bi directional half duplex two wire serial interface bus.

Developed by Philips Semiconductors in the early 1980s to be usedwith connecting Microprocessor and peripheral chips in television sets

Has two bus lines; Serial Clock-SCL and Serial Data SDA. SCL line is responsible for generating synchronisation clock pulses and

SDA is responsible to carry serial data.

I2C is a shared bus to which many devices can be connected. Devicescan be Master or Slave. Master take responsibility of sendingsynchronizing clocks and serial data.

Master and Slave devices can act as either transmitter or receiver.Master either as transmitter or receiver is responsible for sendingsynchronizing clock pulses.

I2C supports multi masters on the same bus.


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I2C bus interface is built around an input bufferand an open drain/collector transistor.

When the bus is in the idle state, the open drain

/collector transistor will be in the floating stateand the output lines SDA and SCL switch to theHigh Impedance state. For proper operation ofthe bus, both the bus lines should be pulled to

the voltage using pull-up resistors. With pull-upresistors, the output lines of the bus in the idlestate will be HIGH


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Sequence of operations for communicating with an I2Cslave device:1. The master device pulls the clock line (SCL) of the bus to HIGH

2. The master device pulls the data line (SDA) LOW when the SCL line is at logic HIGH (this isthe start condition for data transfer)

3. The master device sends the address of the slave device over the SDA line. Clock pulses aregenerated at the SCL line for synchronizing the bit reception by the slave device. The MSBof the data is always transmitted first. The data in the bus is valid during the HIGH period

of the clock signal. . ,

write)

5. Master waits for the acknowledgement from slave while slave dcode the address sent onthe SDA line

6. Slave device sends an acknowledgement over SDA line

7. Master transmits 8-bit data over SDA line if it is write operation or slave sends the data if itis Read operation

8. Acknowledgement for data transfer is done (either master or slave will send depending onread or write operation)

9. The master device terminates the transfer by pulling the SDA line HIGH when the clockline SCL is at logic HIGH (indicating the STOP condition)


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Three different rates supported by I2C are; Standard mode (100kbps)

Fast mode (400kbps)

High speed mode(3.4mbps)

Serial Peripheral Interface (SPI) Bus

It is synchronous, bi-directional full-duplex four wire serial interface bus

It is a single master multi-slave system

More than one master is allowed but only one will be active at a time.

Signals used with SPI are: Master Out Slave In (MOSI): Signal carrying data from master to slave device. It is also

known as Slave Input/Slave Data In (SI/SDI)

Master In Slave Out (MISO): Signal line carrying data from slave to master device. It isalso known as Slave Output (SO/SDO)

Serial Clock (SCLK): Signal line carrying clock signals

Slave Select (SS): Signal line for slave device select. It is active low signal.


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Master is responsible for generating clock signal. It selects the required slavedevice. The data outline (MISO) of all the slave devices when not selected floats athigh impedance state.

Serial data transmission through SPI bus is fully configurable. Certain set ofregisters are used for this. The serial peripheral control register holds theconfiguration parameters such as slave select address, baud rate, clock signal

control etc. The status register holds the status of various conditions for TX and RX. .

device have special shift registers. Size of the shift register is normally devicedependent and it is generally multiple of 8.

Shift registers of master and slave forms a circular buffer. Data transfer happensfrom master shift register to slave shift register through MOSI pin. Whereasotherwise communication is through MISO pin.

Comparison to I2C bus, SPI bus is most suitable for applications requiring transfer

data in Streams. Limitation is that it does not support acknowledgement mechanism.


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Universal Asynchronous Receiver Transmitter (UART) Asynchronous serial data transmission, no clock signal required.

Pre defined rules and agreements control the data transfer.

The serial communication settings (baud rate, number of bits per byte,parity, number of start and stop bits and flow control ) for both Tx and

Rx should be set as identical. o ng o a a a x s one a e ra e x secon s w ere x s e

baud rate. The receiver unit polls the receiver line exactly half of thetime slot available for the bit.

Parity adding and checking is done at Tx and Rx respectively.

In addition to the serial data transmission function, UART provideshardware handshaking signal support for controlling the serial dataflow.

National semiconductors 8250 is an example for UART chip.

Present day processors/controllers comes with integrated UARTfunctionality.


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1-Wire Interface

It is an asynchronous half-duplex communication protocoldeveloped by Maxim Dallas. It is also referred to as Dallas1-wire protocol.

Sin le line called DQ is used for communication. Master-Slave communication model is followed.

Power can be sent along the signal-wire

Supports single master and one or more slave devices.

Every 1-wire device contains a globally unique 64 bitidentification number stored within it. The identifier asthree parts: an 8-bit family code, a 48-bit serial numberand an 8-bit CRC computed from the first 56 bits.


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The communication protocol is:1. The master device sends a Reset pulse on the 1-wire bus

2. The slave device present on the bus respond with a Presence pulse

3. The master device sends a ROM command (Net address commandfollwoed by the 64 bit address of the device). This addresses the

slave devices to which it wants to initiate a communcation.. e mas er ev ce sen s a rea wr e unc on comman o rea

/write the internal memory or register of the slave device.

5. The master initiates a Read data/Write data from the device or tothe device.

All communication over 1-wire bus is mater initiated.

Communication is divided into timeslots of 60 microseconds. Each operation of data communication is expressed interms of

above time slots. Ex In the step -1 Reset pulse occupies 8 timeslots.


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Parallel Interface Generally used with memory mapped devices onboard

The host processor/controller of the embedded system containsa parallel bus and the device which supports parallel bus candirectly connect to this bus system

Communication on this bus is controlled throu h control si nalinterface.

Control signal includes Read and write and device select.Direction of data transfer is controlled by Read and Write signal.

Strict timing characteristics are followed for parallelcomunication.

Parallel communication is always host initiated

If the device wants initiate a data transfer then interruptmechanism is used.


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External Communication Interfaces RS-232 C & RS-485

RS-232 C (Recommended Standard number 232,revision Cfrom the Electron Industry Association(EIA)) is a legacy, full

duplex, weird, asynchronous serial communication interface eve ope n s. - ex en s e

communication signals for external data communication

RS-232 follows EIA standard for bit transmission (logic 0 isrepresented by voltage +3 to +25 V and logic 1 isrepresented with voltage between -3 to -25 V. Logic 0

referred to as Space and logic 1 known as Mark RS-232 has various handshaking signals for data

communication apart from standard transmit and receive

Two connectors are supported DB-9 and DB-25


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1 5

4 9

11

3

1

4

2

5


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Pin

name

DB-9 DB-25 Description

TXD 3 2 Transmit pins for transmitting serial data

RXD 2 3 Receive pin for Receiving serial data

RTS 7 4 Request to send

CTS 8 5 Clear to send

DSR 6 6 Data set ready

GND 5 7 Signal Ground

DCD 1 8 Data Carrier detect

DTR 4 20 Data terminal Ready

RI 9 22 Ring Indicator

FG 1 Frame Ground

SDCD 12 Secondary DCD

SCTS 14 Secondary CTS

STXD 15 Secondary TXD


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Pin

name

DB-9 DB-25 Description

TC 15 Transmission Signal Element Timing

SRXD 16 Secondary RXD

RC 17 Receiver Signal Element Timing

SRTS 19 Secondary RTS

SQ 21 Signal Quality detector

NC 9 No connection

NC 10 No connection

NC 11 No connection

NC 18 No connection

NC 23 No connection

NC 24 No connection

NC 25 No connection


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Data Terminal Equipment (DTE) and Data Communication Equipment (DCE) are involved in point-to-point communication usingRS-232

If no data flow control is required then it is only TXD and RXD are required in crossconnection mode.

Control signals are used for modem communication .

RTS and CTS signals coordinate the communication between DTE and DCE.

DTR and DSR are acknowledgement kind of signals from DTE and DCE respectively.

DCD is used by the DCE to indicate the DTE that a god signal is being received.

RI is a modem specific signal line for indicating an incoming call on the telephone line.

The 25 pin DB connector contains two sets of signal lines for transmit, receive and controllines. Now a days DB-25 connector is obsolete.

Baud rate supported are 300bps,1200bps,9600bps,11.52kbps and 19.2kbps. 9600 bps is themost widely used one.

Maximum operating distance of RS-232 is 50 feet

UART is used as onboard communication interface in most of the embedded systemsconversion from onboard to RS-232 is done through converters both at TX and RX. (eg MAX232)


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Disadvantages of RS-232 Bluetooth, USB, Firewire technologies have pushed RS-232

technology.

RS-232 supports only point-to-point communication not suited formulti-drop communication

Since it uses single ended data transfer technique for signaltransmission and threb more susce tible to noise and this reatlreduces the operating distance.

RS-422 is another standard from EIA supporting 100kbps baudrate over 400 feet. It is compatible with RS-232, converters areneeded.

Multi-drop communication with one TX device and Rx devices

upto 10. RS-485 is the enhanced version of RS-422. It can go up to 32

receivers. The communication between devices in the bus usesthe addressing mechanism to identify slave sections.


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Universal Serial Bus (USB) Wired high speed bus

Intel, Microsoft, IBM, Compaq, Digital and Northern Telecom togetherproposed this standard.

USB communication system follows a star topology with a USB host at

the centre and one or more USB peripheral devices connected to it. os can suppor connec on up o nc us ve o s ave an

other USB hosts.

USB transmits data in packet format. Comunnication is host initiatedone.

USB host contains a host controller which is responsible for controllingthe data communication, including establishing connectivity with USB

slave devices, packetizing and formatting the data. Two important standards Open Host Control Interface (OHCI) and

Universal Host Control Interface (UHCI)


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USB cable is used to establish physical connectionbetween host and other devices.

USB cable supports communication upto 5 meters.

USB standard uses two different types of connector at.

Type A connector is used for upstream connection(connection with host) and Type B is used fordownstream connection (connection with slave)

Type A connector is used with PCs and Laptops.

Both Type A and Type B contain 4-pins forcommunication.


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Pin no Pin Name Description

1 V Bus Carries power (5V)

2 D- Differential data carrier line

3 D+ Differential data carrier line

4 GND Ground signal line


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USB uses differential signals for data transmission. It improves the noise immunity.

USB interface has the ability to supply power to the connecting devices. It can supply power upto 500mA at5 V.Mini and Micro USB connectors are available for small form factor devices like portable media players.

Each USB device contains a product ID (PID) and Vendor ID (VID) which embedded into the USB chip by theUSB device manufacturer. VID is supplied by the USB standards forum. PID and VID are essential for loadingthe drivers corresponding to a USB device for communication.

USB supports four modes of data transfer:

Control: Used by USB system software to query, configure and issue commands to the USBdevice

Bulk: Is used for sending block of data to a device. This supports error checking and correction.Transferring data to a printer.

Isochronous mode: Used for real data communication. Data transmitted as stream in real-time. No error-checking allowed. Audio devices and medical equipments use this.

Interrupt transfer: Used for small amount of data transfer . Uses polling technique to seewhether the USB device has any data to send. Mouse and keypad uses this technique .

Four different data rates : Low speed (1.5 Mbps), Full speed (12 Mbps), High speed (480Mbps) andsuper speed (4.8 Gps)

USB1.0 defines Low and Full speed

USB 2.0 and above defines high and super speed.


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IEEE 1394 (Firewire) Wired, isochronous high speed serial communication bus, also known as High

Performance Serial Bus (HPSB)

Apple carried out this research and standard proposed by IEEE. Available fromvarious vendors (Firewire from Apple, i.Link from Sony, Lynx from TI)

Supports peer-to-peer connection and point-to-multipoint communication

allowing 63 devices to be connected on the bus in a tree topology. Can support cable length of 15 feet.

Evolution from initial version (1394-1995) to recent version (1394-2008)

Supports data rate from 400 to 3200 Mbits/sec

Uses differential data transfer

Interface cable supports 3 types of connectors, namely; 4-pin connector, 6-pinconnector(alpha connector) and 9 pin connector (beta connector)

6 & 9 pin connectors carry power also to power peripheral devices. It cansupply unregulated power in the range of 24 to 30 V.


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Pin Name 4pin 6pin 9pin Description

Power 1 8 Unregualted DC supply, 24 30V

Signal Ground 2 6 Ground connection

TPB- 1 3 1 Diff signal line for signal line B

TPB+ 2 4 2 Diff signal line for signal line B

TPA- 3 5 3 Diff signal line for signal line A

TPA+ 4 6 4 Diff signal line for signal line A

TPA (S) 5 Shield for Diff signal line A. Normally Gnded

TPB(S) 9 Shield for Diff signal line B. Normally Gnded

NC 7 No connection


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There are two differential data transfer lines A & B perconnector. In a 1394 cable, normally the differentiallines of A are connected to B

1394 is a popular communication interface for

connecting embedded devices like Digital camera,,transfer and storage.

Unlike USB interface ,IEEE 1394 does not require ahost for communicating between devices. Eg., scannercan be connected to printer directly.

Data rate supported by 1394 is far higher than the onesupported by USB 2.0 interface.


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Infrared (IrDA) Serial, half duplex, line of sight based wireless technology (used with

TV, VCD etc)

Uses infrared waves of electromagnetic spectrum for transmitting thedata.

Supports point-to-point and point-to-multipoint communication.

Typical range 10 cm to I mt. Range can be increased further byincreasing TX power.

Speed of transmission is from 9600 bps to 16 Mbps

Based on speed five classifications. Serial IR (SIR) 9600bps to 115.2 kbps

Medium IR (MIR)-0.576 Mbps to 1.152 Mbps

Fast IR (FIR)- 4Mbps

very fast IR (VFIR) -16Mbps

Ultra Fast IR (UFIR)-targeted for 100Mbps


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Tx and Rx are involved in Ir DA communication. LED is the IR source fortransmission and photodiode at RX used for reception.

Both Tx and Rx will be present in the device known as Transceiver tohave two-way communication.

Infra-red Data Assocaition is the regulatory body.

IrDA communication has two essential parts; a physical link part and.of data between devices and protocol part is responsible for definingthe rules of communication. IrDA specification include the standardfor both physical link and protocol layer.

The IrDA control protocol contains implementations for physical layer(PHY), Media Access Control (MAC) and Logical Link Control (LLC)

IrDA is a popular interface for file exchange and data transfer in lowcost devices.


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Bluetooth (BT)

Low cost, low power, short range wireless technology for data and voice data communication.

Proposed first by Ericsson in 1994

Operates at 2.4 GHz of the Radio Freq spectrum and uses Frequency Hopping Spread Spectrum(FHSS) technique

Supports data rate of 1 Mbps and 30 feet

Has physical link part and protocol part.

Bluetooth enabled devices essentially contain a Bluetooth wireless radio for the transmission andreception of data. Rules governing the Bluetooth communication is implemented in the Bluetoothprotocol stack. Bluetooth communication IC holds the stack.

Each Blue tooth device has a 48 bit ID number. Communication follows packet based transfer.

Supports point-to-point and point-to-multipoint communication. Master slave communicationmodel is followed. When network is formed with one bluetooth device as master and more than onedevice as slaves, it is called Piconet. Piconet supports max of seven slave devices.

Most widely used with Mobile devices

The Generic Access Profile (GAP) defines the requirements for detecting a Bluetooth device andestablishing a connection with it. All other specific usage profiels are based on GAP. Serial Port Profile

(SPP) for serial communication, File transfer Profile (FTP ) for file transfer between devices, HumanInterface Device (HID) for supporting human interface devices like keyboard and mouse.

Blue tooth Special interest group (SIG) defines the standards.


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Wi-Fi or Wireless Fidelity Popular communication technique for networked communication of devices and it supports

Internet Protocol(IP)

It follows IEEE 802.11 standard

As it is requirement of networking devices to have identification, in wi-fi it is done through IPaddress.

In Wi-Fi routers/access points to manage communication are needed.

Routers/access points are responsible for restricting the access to a network, assigning IP,

network

Wi-Fi enables devices contain a wireless adaptor for transmitting and receiving data in theform of Radio signals through an antenna.

Wi-Fi operates at 2.4 GHz or 5GHz of radio spectrum

Service Set Identifier (SSID) are used in identifying available networks. In case of securednetworks password is needed.

Wi-Fi employs different security mechanisms like Wired Equivalency Privacy (WEP), WirelessProtected Access (WPA) etc.. for securing the data communication

Supports data rates from 1 Mbps to 150 Mbps depending on the standards andaccess/modulation method.

Depending on the type of antenna and usage location , Wi-Fi offers a range of 100-300 feet.


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ZigBee Low power, low cost, woreless network communication protocol based on the IEEE

802.15.4.2006 standard

Targeted for Wireless Personal Area Networking (WPAN).

ZigBee specifications support a robust mesh network containing multiple nodes. Thisnetworking strategy makes the network reliable by permitting messages to travelthrough a number of different paths to get from one node to another.

Operates worldwide at the unlicenced badns of Radio spectrum. Supports operating distance up to 100 mts and a data rate of 20 to 250kbps.

ZigBee Coordinator(ZC)/Network Coordinator: This acts as root of the ZigBee network.It is responsible for initiating the network and it has the capability to store informationabout the network.

ZigBee Router(ZR)/Full function Device (FFD): Responsible forpassing informationfromm device to another device or ZR

ZigBee End Device (ZED)/Reduced Function Device (RFD): End device containing ZigBee

functionality for data communication . It can talk with a ZR or ZC and doesnt have thecapability to act a mediator for transferring data from one device to another.


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ZigBee has wide application areas such as Home & Industrial automation,

energy management, home control/security, medical/patient tracking,

logistics & asset tracking and sensor networks & active RFID

ZigBee alliance manages defining standards


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General Packet Radio Service (GPRS) GPRS is a communication technique for transferring data over a mobile

communication network like GSM.

Packet communication is used

GPRS supports a theoretical maximum transfer rate of 171.2 Kbps.

Shared communication is used, i.e., instead of radio channel is dedicated to

single cell user it shared among many users. Time division multiplexing is used, i.e., channel is divided into 8 timeslots and

transmits data over the available channel.

GPRS supports IP, Point to Point Protocol (PPP) and X.25 protocols forcommunication.

GPRS is mainly used by mobile enabled embedded devices for datacommunication. The device should support the necessary GPRS hardware like

GPRS modem and GPRS radio. To accomplish GPRS based communication, the carrier network also should

have support for GPRS communication

EDGE, High Speed Downlink Packet Access (HSDPA) are now replacing GPRS.


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Embedded Firmware This refers to the control algorithm (Program

Instructions) and or the configuration settings than anembedded system developer dumps into the code

(Program) memory of the embedded system. This isan unavo a e par o m e e sys em.

Different ways of developing Embedded Firmware are1. Write program in high level languages like Embedded

C/C++ using an Integrated Development Environment(IDE). IDE will contain an editor, compiler,l inker, debugger,

simulator etc. IDE is different for different family ofprocessors. Eg., Keil with 8051 microcontrollers

2. Writing an Assembly level program


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Process of converting the program written in either a high level language or processorspecific Assembly code to machine readable binary code is called HEX File Creation.The methods used for HEX File Creation is different depending on the programmingtechniques used.

For a beginner it is always better to use High level language method, since it is easilyportable. Also programs written in high level languages are not developer dependent.Any skilled programmer can trace out the functionalities and do suitable modification ifsufficient comments and documentation is done.

Debu in time will be ver short.

Assembly language approach is very time consuming and tedious. Each has their ownstyle of writing. Knowing every instruction of the processor is not easy.

Two types of control algorithm development are used in practice. Infinite or loop or super loop approach, where control flow runs from top to bottom an then

jumps back to the top of the program. It is similar to while (1) { } based technique in C.

Second method deals with splitting the function to be executed into tasks and running thesetasks using a scheduler which is part of General Purpose or Real Time Embedded Operation

System (GPOS/RTOS)


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Other System Components

Reset Circuit

Brown-out Protection circuit

Real-Time Clock (RTC)

Watchdog Timer


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Reset Circuit It is essential to ensure that the device is not operating at a

voltage level where the device is not guaranteed tooperate, during system power ON.

The reset signal brings the internal regsiters and the

a known state and starts the firmware execution from thereset vector.

Reset signal can be active High or Low

Since the processor operation is synchronised to a clock

signal, the reset pulse should be wide enough to give timefor the clock oscillator to stabilize before the internal resetstate starts.


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Brown-out Protection Circuit

This circuit prevents the processor/controller fromunexpected program execution behaviour when thesupply voltage to the processor/controller falls below a

specified voltage. It is essential for battery powered devices.

Processor may not behave predictably if voltage falls belowrecommended voltage. It may lead to data corruption.

A brown-out protection circuit holds the processor

/controller in reset state, when the operating volatge fallsbelow the threshold, until it rises above the thresholdvolatge.


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The Zener diode Dz and transistor Q forms the heart of the circuit. The transistor

conducts always when the supply voltage Vcc is greater than that of the sum of VBEand VZ. Moment Vcc drops below this threshold Q stops conducting. When Q is

ON pulse is in High mode when Q in OFF reset pulse is Low.


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Oscillator Unit Commonly clock circuit are built on the board. However, certain

processors/controllers integrate a built-in-oscillator unit and simplyrequire an external ceramic resonator/quartz crystal for producing thenecessary clock signals. Quartz crystal and ceramic resonators areequivalent in operation , however they possess physical difference.

S eed of the rocessor de ends on the clock fre but this fre cannotbe blindly increased. The internal gates decides the threshold.

The total system power consumption is directly proportional to theclock frequency.

The accuracy of program execution depends on the accuracy of theclock signal. The accuracy of the crystal oscillator or ceramic resonator

is normally expressed in terms of +/- ppm(parts per million)


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Real-Time Clock (RTC) RTC is a system component responsible for keeping track of time. This supplies

timing reference to the system.

RTC is intended to perform in the absence of power.

The RTC chip contains a microchip for holding the time and date relatedinformation and backup battery cell for functioning in the absence of power, in

a single IC package. The RTC chip is interfaced to the processor or controller ofe em e e sys em.

For OS based embedded devices, a timing reference is essential forsynchronizing the operations of the OS kernel. The RTC can interrupt the OSkernel by asserting the interrupt line of the processor/controller to which theRTC interrupt line is connected. One IRQ can be assigned to the RTC interruptand the kernel can perform necessary operations like system date timeupdation, managing software timers etc when an RTC timer tick interrupt

occurs. The RTC can be configured to interrupt the processor at predefined intervals

or to interpret the processor when the RTC register reaches a specified value.


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Watchdog Timer Watchdog timer is responsible to reset the embedded

system when the execution of program hangs up.

This is a Hardware timer for monitoiring the firmwareexecution

epen ng on n erna mp emen a on , e wa c ogtimer increments or decrements a free running counterwith each clock pulse

Generates a reset signal to reset the processor if the countreaches zero incase of decrement counter or highest value

in case of up-counter. Firmware can initialize the watchdog counter before the

start of execution


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If the firmware execution doesnt complete due to malfunctioning,within the time required by the watchdog to reach the maximumcount, the counter will generate a reset pulse and this will reset theprocessor. If the program completes the execution then watchdogcounter can be loaded with 0 (up counter)

Most of the processors implements this as built-in component and

provides status register to control the watchdog timer and watchdogtimer register for writing the count value.

Some processors have this as external circuitry also. The hardware/logic takes care of generating necessary enabling, disabling, countincrement/decrement and reset generation

The Microprocessor supervisor IC DS1232 integrates a hardwarewatchdog timer in it.

Interrupt can also be generated instead of reset and interrupt handlercan be programmed to handle the situation.


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PCB and Passive Components

PCB is the backbone of every Embedded System

Along with ICs responsible for executing required

logic etc. there are passive components likeresistors, capacitors supporting the whole system.

There are many subsystems like circuit responsiblefor supplying regulated (ripple free) power supply,spike suppressors etc which are of equalimportance in defining performance of thesystem.

Characteristics and Quality Attributes


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Characteristics and Quality Attributes

of Embedded System Characteristics of an Embedded System

1. Application and domain specific-designed for one application cannot be used for other

2. Reactive and Real Time- responding to input and that to too quickly

3. Operates in harsh environments-dusty, high temperature andvibration full atmosphere

. s r u e - ar rea ng, ransac ons, money coun er antransaction printer in ATM are independent embedded systems.Coffee vending machine has card reader and vending unit which areseparate ES. Supervisory Control and Data Acquisition (SCADA)

5. Small size and weight-Small is comfortable, compact and easy tomaintain

6. Power concerns-devices consuming less power, devices with lowpower technology


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Quality Attributes of Embedded System

These are the non-functional requirements that

need to be documented properly in any system

desi n. More concrete and measurable has better impact

on system development process.

1. Operational Quality Attributes

2. Non-Operational Quality Attributes


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Operational Quality Attributes

Represents the relevant quality attributes related to the

embedded system when it is in the operational mode

or online mode

. esponse- easure o qu c ness

2. Throughput- No. of products, no. of transactions over a

fixed time, Measured in terms of Benchmark

3. Reliability- percentage of reliance of proper functioning or

what is the susceptibility of the system for failure, Mean

Time Between Failures (MTBF) and Mean Time BetweenRepair (MTTR) are used in expressing above.


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4. Maintainability- Reliability and Maintainability are complementary.Maintainability is closely related to system availability. Two categories

Scheduled or Periodic Maintenance, Maintenance to unexpectedfailures Eg: Printer

5. Security Confidentiality Integrity and Availability. Confidentialitydeals with protection of data and application from unauthorizeddisclosure. Integrity deals with protection of data and application from

unauthorized modification. Availability deals with protection of data. .(PDA). In case of shared one PDA is operated and available toindividual through password, this is Availability. Not all data isaccessible to everyone. Administrator defined security is used. ThisConfidentiality. Data available to users can only be seen but notalterable this is Integrity

6. Safety This is possible damage to the operators, public andenvironment due to the breakdown or emission of dangerousradioactive or hazardous materials. Breakdown may due to failure ofhardware or software. Safety analysis should be done during thedesign.


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Non Operational Quality Attributes

1. Testability & Debug-ability

2. Evolvability

.

4. Time to prototype and market

5. Per unit and total cost


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Testability and Debug ability

Ease of testing (both hardware & software)

Debug-ability is a means of debugging the product assuch for figuring out the probable sources that create

unex ected behaviour in the total s stem. Bothhardware and software debugging option need to beprovided.

Evolvability

This is referred to as non-heritable variation. It is the

ease with which embedded product can be modified totake the advantage of new firmware or hardwaretechnologies.


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Portability

It is a measure of system independence

The ease with which an embedded product can be ported onto a new platform is a direct measure of the re-workrequired.

Standard embedded product should always be flexible andportable.

In embedded products, the termporting represents themigration of the embedded firmware written for one targetprocessor to a different target processor.

Using high-level language in writing fimrware improvesportability.

If the firmware is platform independent it is still better.


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Time-to-Prototype and Market

This is the time elapsed between the conceptualisationof a product and the time at which the product is readyfor selling or use.

This time has to be as small as ossible to beat thecompetition

Delay in making may lead to outdate of the technology.

Prototyping is an informal kind of rapid productdevelopment in which important features of the

product under consideration are developed. If Prototype is developed fast time for final product can

be speeded up.


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Per Unit Cost and Revenue

Product life cycle (PLC) has different stages:

Product development- idea discussion, prototyping, design

and development. This stage has only investment no returns

.Generally low revenue in this stage

Growth This stage product gains high market and revenue

increases

Product Maturity Revenue peaks up in this stage

Product retirement revenue starts declining due tocompetition from similar products or change in technology

Documents

Embedded System Design-Presentation