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September 2013 Doc ID 7767 Rev 6 1/26
1
VND920
Double channel high-side solid-state relay
Features
■ CMOS compatible input
■ Proportional load current sense
■ Shorted load protection
■ Undervoltage and overvoltage shutdown
■ Overvoltage clamp
■ Thermal shutdown
■ Current limitation
■ Protection against loss of ground and loss of VCC
■ Very low standby power dissipation
■ Reverse battery protected
DescriptionThe VND920 is a double chip device designed in STMicroelectronics™ VIPower™ M0-3 technology. The VND920 is intended for driving any type of load with one side connected to ground. The active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload.
The device integrates an analog current sense output which delivers a current proportional to the load current. The device automatically turns off in the case where the ground pin becomes disconnected.
Type RDS(on) IOUT VCC
VND920 16 mΩ 35 A(1)
1. Per channel with all the output pins connected to the PCB.
36 V
SO-28 (double island)
Table 1. Device summary
PackageOrder codes
Tube Tape and reel
SO-28 VND920 VND92013TR
www.st.com
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Contents VND920
2/26 Doc ID 7767 Rev 6
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 17
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 18
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 19
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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VND920 List of tables
Doc ID 7767 Rev 6 3/26
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Table 5. Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Table 6. Switching (VCC = 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Table 7. VCC output diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Table 8. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Table 9. Current sense (9 V £ VCC £ 16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Table 10. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Table 13. Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 14. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 15. SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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List of figures VND920
4/26 Doc ID 7767 Rev 6
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 4. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 5. IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 7. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 8. High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 10. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 11. Over-voltage shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 12. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 13. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 14. On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 15. Input high-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 17. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 18. Input low-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 19. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 20. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 21. SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 22. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 21Figure 23. Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 24. Thermal fitting model of a double channel HSD in SO-28 . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 25. SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 26. SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 27. SO-28 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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VND920 Block diagram and pin description
Doc ID 7767 Rev 6 5/26
1 Block diagram and pin description
Figure 1. Block diagram
UNDERVOLTAGE
OVERTEMPERATURE
VCC 1
GND 1
INPUT 1OUTPUT 1
OVERVOLTAGE
CURRENT LIMITER
LOGIC
DRIVER
Power CLAMP
VCCCLAMP
VDS LIMITER
DETECTION
DETECTION
DETECTION
KIOUT CURRENT
SENSE 1
UNDERVOLTAGE
OVERTEMPERATURE
VCC 2
GND 2
INPUT 2OUTPUT 2
OVERVOLTAGE
CURRENT LIMITER
LOGIC
DRIVER
Power CLAMP
VCCCLAMP
VDS LIMITER
DETECTION
DETECTION
DETECTION
KIOUT CURRENT
SENSE 2
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Block diagram and pin description VND920
6/26 Doc ID 7767 Rev 6
Figure 2. Configuration diagram (top view)
Table 2. Suggested connections for unused and not connected pins
Connection / pin Current Sense N.C. Output Input
Floating X X X
To groundThrough 1KΩ
resistorX
Through 10KΩ resistor
VCC 1
GND 1
INPUT 1
CURRENT SENSE 1
NC
VCC 1
VCC 2
GND 2
INPUT 2
CURRENT SENSE 2
VCC 2 VCC 2OUTPUT 2OUTPUT 2
OUTPUT 2
OUTPUT 2
OUTPUT 1OUTPUT 1OUTPUT 1
OUTPUT 1
VCC1
OUTPUT 2OUTPUT 2
OUTPUT 1OUTPUT 1
NC
NCNC
1
14 15
28
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VND920 Electrical specifications
Doc ID 7767 Rev 6 7/26
2 Electrical specifications
Figure 3. Current and voltage conventions
Note: VFn = VCCn - VOUTn during reverse battery condition.
2.1 Absolute maximum ratingsStressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality document.
IS2
IGND2
OUTPUT2
VCC2
IOUT2
VCC2
VSENSE2
CURRENT SENSE 1ISENSE1
VOUT2
OUTPUT1IOUT1
CURRENT SENSE 2ISENSE2
VSENSE1
VOUT1
INPUT2IIN2
INPUT1
IIN1
VIN2
VIN1
GROUND2
IS1
VCC1VCC1
IGND1
GROUND1
VF1 (*)
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 41 V
-VCC Reverse DC supply voltage - 0.3 V
-Ignd DC reverse ground pin current - 200 mA
IOUT DC output current Internally limited A
-IOUT Reverse DC output current - 21 A
IIN DC input current +/- 10 mA
VCSENSE Current sense maximum voltage- 3
+ 15VV
VESD
Electrostatic discharge (human body model: R = 1.5 KΩ; C = 100 pF)
– INPUT– CURRENT SENSE– OUTPUT
– VCC
400020005000
5000
VVV
V
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Electrical specifications VND920
8/26 Doc ID 7767 Rev 6
2.2 Thermal data
EMAX
Maximum switching energy(L = 0.25 mH; RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C; IL = 45 A)
355 mJ
Ptot Power dissipation TC ≤ 25 °C 6.25 W
Tj Junction operating temperature Internally limited °C
Tc Case operating temperature - 40 to 150 °C
Tstg Storage temperature - 55 to 150 °C
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 4. Thermal data (per island)
Symbol Parameter Value Unit
Rthj-lead Thermal resistance junction-lead 20 °C/W
Rthj-amb Thermal resistance junction-ambient (one chip ON) 60(1)
1. When mounted on a standard single-sided FR-4 board with 1cm2 of Cu (at least 35 µm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow.
45(2)
2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35 µm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow.
°C/W
Rthj-amb Thermal resistance junction-ambient (two chips ON) 46(1) 32(2) °C/W
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VND920 Electrical specifications
Doc ID 7767 Rev 6 9/26
2.3 Electrical characteristicsValues specified in this section are for 8 V < VCC < 36 V; -40 °C < Tj < 150 °C, unless otherwise stated.
Note: VCLAMP and VOV are correlated. Typical difference is 5V.
Table 5. Power
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage 5.5 13 36 V
VUSD Undervoltage shutdown 3 4 5.5 V
VOV Overvoltage shutdown 36 V
RON On-state resistance
IOUT = 10 A; Tj = 25 °C; 16 mΩ
IOUT = 10 A; 32 mΩ
IOUT = 3 A; VCC = 6 V 55 mΩ
VCLAMP Clamp voltage ICC = 20 mA 41 48 55 V
IS Supply current
Off-state; VCC = 13 V; VIN = VOUT = 0 V
10 25 µA
Off-state; VCC = 13 V; VIN = VOUT = 0 V; Tj = 25 °C
10 20 µA
On-state; VCC = 13 V; VIN = 5 V; IOUT = 0 A; RSENSE = 3.9 kΩ 5 mA
IL(off1) Off-state output current VIN = VOUT = 0 V 0 50 µA
IL(off2) Off-state output current VIN = 0 V; VOUT = 3.5 V -75 0 µA
IL(off3) Off-state output currentVIN = VOUT = 0 V; VCC = 13 V; Tj = 125 °C
5 µA
IL(off4) Off-state output currentVIN = VOUT = 0 V; VCC = 13 V; Tj = 25 °C
3 µA
Table 6. Switching (VCC = 13 V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time RL = 1.3 Ω (see Figure 4) 50 µs
td(off) Turn-off delay time RL = 1.3 Ω (see Figure 4) 50 µs
dVOUT/dt(on) Turn-on voltage slope RL = 1.3 Ω (see Figure 4) See Figure 10 V/µs
dVOUT/dt(off) Turn-off voltage slope RL = 1.3 Ω (see Figure 4) See Figure 12 V/µs
Table 7. VCC output diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
VF Forward on voltage -IOUT = 5 A; Tj = 150 °C 0.6 V
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Electrical specifications VND920
10/26 Doc ID 7767 Rev 6
Table 8. Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low-level voltage 1.25 V
IIL Low-level input current VIN = 1.25 V 1 µA
VIH Input high-level voltage 3.25 V
IIH High-level input current VIN = 3.25 V 10 µA
VI(hyst) Input hysteresis voltage 0.5 V
VICL Input clamp voltageIIN = 1 mA 6 6.8 8 V
IIN = -1 mA -0.7 V
Table 9. Current sense (9 V ≤ VCC ≤ 16 V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K1 IOUT/ISENSEIOUT = 1 A; VSENSE = 0.5 V;Tj = -40 °C...150 °C
3300 4400 6000
dK1/K1Current sense ratio drift
IOUT = 1 A; VSENSE = 0.5 V; Tj = -40 °C...150 °C
-10 +10 %
K2 IOUT/ISENSE
IOUT = 10 A; VSENSE = 4 V; Tj = -40 °C;Tj= 25°C...150°C
42004400
49004900
60005750
dK2/K2Current sense ratio drift
IOUT = 10A; VSENSE = 4V; Tj = -40 °C...150 °C
-8 +8 %
K3 IOUT/ISENSE
IOUT = 30 A; VSENSE = 4 V;Tj = -40 °CTj = 25 °C...150 °C
42004400
49004900
55005250
dK3/K3Current sense ratio drift
IOUT = 30 A; VSENSE = 4 V; Tj = -40 °C...150 °C
-6 +6 %
ISENSE0Analog sense current
VCC = 6...16 V; IOUT = 0 A; VSENSE = 0 V;
Tj = -40 °C...150 °C
0 10 µA
VSENSE
Max analog sense output voltage
VCC = 5.5 V; IOUT = 5 A;
RSENSE = 10 kΩ2 V
VCC > 8 V, IOUT = 10 A;
RSENSE = 10 kΩ4 V
VSENSEH
Sense voltage in overtemperature condition
VCC = 13 V; RSENSE = 3.9 kΩ 5.5 V
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VND920 Electrical specifications
Doc ID 7767 Rev 6 11/26
RVSENSEH
Analog sense output impedance in overtemperature condition
VCC = 13 V; Tj > TTSD; output open 400 Ω
tDSENSECurrent sense delay response
To 90% ISENSE(1) 500 µs
1. Current sense signal delay after positive input slope.
Table 10. Protections(1)
1. To ensure long term reliability under heavy over-load or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
TTSD Shutdown temperature 150 175 200 °C
TR Reset temperature 135 °C
Thyst Thermal hysteresis 7 15 °C
Ilim Current limitationVCC = 13 V 30 45 75 A
5 V < VCC < 36 V 75 A
VdemagTurn-off output clamp voltage
IOUT = 2 A; VIN = 0 V; L = 6 mH
VCC - 41 VCC - 48 VCC - 55 V
VONOutput voltage drop limitation
IOUT = 1 A; Tj = -40 °C...150 °C
50 mV
Table 11. Truth table
Conditions Input Output Sense
Normal operationLH
LH
0Nominal
Over-temperatureLH
LL
0VSENSEH
Under-voltageLH
LL
00
Over-voltageLH
LL
00
Short circuit to GNDLH
H
LL
L
0(Tj < TTSD) 0
(Tj > TTSD) VSENSEH
Short circuit to VCCL
H
H
H
0
< Nominal
Negative output voltage clamp L L 0
Table 9. Current sense (9 V ≤ VCC ≤ 16 V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
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Electrical specifications VND920
12/26 Doc ID 7767 Rev 6
Figure 4. Switching characteristics
Table 12. Electrical transient requirements
ISO T/R
7637/1
Test pulse
Test level
I II III IV Delays and impedance
1 - 25V(1)
1. All functions of the device are performed as designed after exposure to disturbance.
- 50V(1) - 75V(1) - 100V(1) 2ms, 10Ω
2 + 25V(1) + 50V(1) + 75V(1) + 100V(1) 0.2ms, 10Ω
3a - 25V(1) - 50V(1) - 100V(1) - 150V(1) 0.1µs, 50Ω
3b + 25V(1) + 50V(1) + 75V(1) + 100V(1) 0.1µs, 50Ω
4 - 4V(1) - 5V(1) - 6V(1) - 7V(1) 100ms, 0.01Ω
5 + 26.5V(1) + 46.5V(2)
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.
+ 66.5V(2) + 86.5V(2) 400ms, 2Ω
VOUT
dVOUT/dt(on)
tr
80%
10% tf
dVOUT/dt(off)
ISENSE
t
t
90%
td(off)
INPUT
t
90%
td(on)
tDSENSE
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VND920 Electrical specifications
Doc ID 7767 Rev 6 13/26
Figure 5. IOUT/ISENSE versus IOUT
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 323000
3500
4000
4500
5000
5500
6000
6500
min.Tj=-40°C
max.Tj=-40°C
min.Tj=25...150°C
max.Tj=25...150°C
typical value
IOUT (A)
IOUT/ISENSE
6500
6000
5500
5000
4500
4000
3500
3000
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Electrical specifications VND920
14/26 Doc ID 7767 Rev 6
Figure 6. Waveforms
SENSE
INPUT
NORMAL OPERATION
UNDERVOLTAGE
VCC
VUSD
VUSDhyst
INPUT
OVERVOLTAGE
VCC
SENSE
INPUT
SENSE
LOAD CURRENT
LOAD CURRENT
LOAD CURRENT
VOV
VOVhystVCC > VUSD
SHORT TO GROUND
INPUT
LOAD CURRENT
SENSE
LOAD VOLTAGE
INPUT
LOAD VOLTAGE
SENSE
LOAD CURRENT
<Nominal <Nominal
SHORT TO VCC
OVERTEMPERATURE
INPUT
SENSE
TTSD
TRTj
LOAD CURRENT
ISENSE=RSENSE
VSENSEH
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VND920 Electrical specifications
Doc ID 7767 Rev 6 15/26
2.4 Electrical characteristics curves
Figure 7. Off-state output current Figure 8. High-level input current
Figure 9. Input clamp voltage Figure 10. Turn-on voltage slope
Figure 11. Over-voltage shutdown Figure 12. Turn-off voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
9
IL(off1) (uA)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Iih (uA)
Vin=3.25V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
Vicl (V)
Iin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
250
300
350
400
450
500
550
600
650
700
dVout/dt(on) (V/ms)
Vcc=13VRl=1.3Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
30
32
34
36
38
40
42
44
46
48
50
Vov (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
350
400
450
500
550
dVout/dt(off) (V/ms)
Vcc=13VRl=1.3Ohm
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Electrical specifications VND920
16/26 Doc ID 7767 Rev 6
Figure 13. ILIM vs Tcase Figure 14. On-state resistance vs VCC
Figure 15. Input high-level Figure 16. Input hysteresis voltage
Figure 17. On-state resistance vs Tcase Figure 18. Input low-level
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
10
20
30
40
50
60
70
80
90
100
Ilim (A)
Vcc=13V
5 10 15 20 25 30 35 40
Vcc (V)
0
5
10
15
20
25
30
35
40
45
50
Ron (mOhm)
Tc= - 40ºC
Tc= 25ºC
Tc= 150ºC
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
Vhyst (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
5
10
15
20
25
30
35
40
45
50
Ron (mOhm)
Iout=10AVcc=8V; 36V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Vil (V)
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VND920 Application information
Doc ID 7767 Rev 6 17/26
3 Application information
Figure 19. Application schematic
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1. RGND ≤ 600 mV / (IS(on)max).
2. RGND ≥ (-VCC) / (-IGND)
where - IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC < 0: during reverse battery situations) is:
PD = (-VCC)2/ RGND
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high-side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
VCC1
OUTPUT2
C. SENSE 1
Dld
+5V
Rprot
OUTPUT1
RSENSE1,2
INPUT1
C. SENSE 2
INPUT2
μC
Rprot
Rprot
Rprot
DGND
RGND
VGND
GND1 GND2
VCC2
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Application information VND920
18/26 Doc ID 7767 Rev 6
3.1.2 Solution 2: diode (DGND) in the ground line
A resistor (RGND = 1 kΩ) should be inserted in parallel to DGND if the device drives an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (≈600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating.
Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.
3.2 Load dump protection Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 MCU I/Os protectionIf a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins to latch-up.
The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -100V and Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
5 kΩ ≤ Rprot ≤ 65 kΩ.
Recommended values: Rprot = 10 kΩ .
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VND920 Application information
Doc ID 7767 Rev 6 19/26
3.4 Maximum demagnetization energy (VCC = 13.5V)
Figure 20. Maximum turn-off current versus inductance
Note: Values are generated with RL =0 Ω.In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
1
10
100
0.01 0.1 1 10 100L(mH)
ILMAX (A)
A
BC
C: Tjstart = 125°C repetitive pulse
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
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Package and PCB thermal data VND920
20/26 Doc ID 7767 Rev 6
4 Package and PCB thermal data
4.1 SO-28 thermal data
Figure 21. SO-28 PC board
Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 µm, Copper areas: 0.5 cm2, 3 cm2, 6 cm2).
RthA = Thermal resistance Junction to Ambient with one chip ON
RthB = Thermal resistance Junction to Ambient with both chips ON and Pdchip1 = Pdchip2
RthC = Mutual thermal resistance
Table 13. Thermal calculation according to the PCB heatsink area
Chip 1 Chip 2 Tjchip1 Tjchip2 Note
ON OFF RthA x Pdchip1 + Tamb RthC x Pdchip1 + Tamb
OFF ON RthC x Pdchip2 + Tamb RthA x Pdchip2 + Tamb
ON ON RthB x (Pdchip1 + Pdchip2) + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1 = Pdchip2
ON ON (RthA x Pdchip1) + RthC x Pdchip2 + Tamb (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1 ≠ Pdchip2
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VND920 Package and PCB thermal data
Doc ID 7767 Rev 6 21/26
Figure 22. Rthj-amb vs PCB copper area in open box free air condition
Figure 23. Thermal impedance junction ambient single pulse
10
20
30
40
50
60
70
0 1 2 3 4 5 6 7PCB Cu heatsink area (cm^2)/island
RTHj_amb (°C/W)
RthC
RthB
RthA
0.01
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10 100 1000time(s)
Zth(°C/W)
One channel ON
Tw o channels ON
6 cm ^2/is land
3 cm ^2/is land
0,5 cm ^2/is land
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Package and PCB thermal data VND920
22/26 Doc ID 7767 Rev 6
Equation 1pulse calculation formula
Figure 24. Thermal fitting model of a double channel HSD in SO-28
Table 14. Thermal parameters
Area/island (cm2) 0.5 6
R1 (°C/W) 0.02
R2 (°C/W) 0.1
R3 (°C/W) 2.2
R4 (°C/W) 11
R5 (°C/W) 15
R6 (°C/W) 30 13
C1 (W.s/°C) 0.0015
C2 (W.s/°C) 7.00E - 03
C3 (W.s/°C) 1.50E - 02
C4 (W.s/°C) 0.2
C5 (W.s/°C) 1.5
C6 (W.s/°C) 5 8
ZTHδ RTH δ ZTHtp 1 δ–( )+⋅=
where δ tp T⁄=
T_amb
Pd1
C1
R4
C3 C4
R3R1 R6R5R2
C5 C6C2
Pd2
R2
C1 C2
R1
Tj_1
Tj_2
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VND920 Package and packing information
Doc ID 7767 Rev 6 23/26
5 Package and packing information
5.1 ECOPACK® packagesIn order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
Figure 25. SO-28 package dimensions
Table 15. SO-28 mechanical data
SymbolMillimeters
Min. Typ. Max.
A 2.65
a1 0.10 0.30
b 0.35 0.49
b1 0.23 0.32
C 0.50
c1 45° (typ.)
D 17.7 18.1
E 10.00 10.65
e 1.27
e3 16.51
F 7.40 7.60
L 0.40 1.27
S 8° (max.)
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Package and packing information VND920
24/26 Doc ID 7767 Rev 6
5.2 SO-28 packing information
Figure 26. SO-28 tube shipment (no suffix)
Figure 27. SO-28 tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Q.ty 28Bulk Q.ty 700Tube length (± 0.5) 532A 3.5B 13.8C (± 0.1) 0.6
A
CB
Base Q.ty 1000
Bulk Q.ty 1000A (max) 330B (min) 1.5
C (± 0.2) 13F 20.2G (+ 2 / -0) 16.4
N (min) 60T (max) 22.4
Tape dimensionsAccording to Electronic Industries Association(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4Component Spacing P 12Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5Hole Position F (± 0.05) 7.5Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm minEmpty components pocketssaled with cover tape.
User direction of feed
Reel dimensions
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VND920 Revision history
Doc ID 7767 Rev 6 25/26
6 Revision history
Table 16. Document revision history
Date Revision Changes
07-Jul-2004 1 Initial release.
09-Sep-2004 2
Minor changes.Current and voltage convention update (page 2).Configuration diagram (top view) and suggested connections for unused and n.c. pins insertion (page 2).6 cm2 Cu condition insertion in thermal data table (page 3).
VCC - output diode section update (page 4).Revision history table insertion (page 34).Disclaimers update (page 35).
03-May-2006 3 Suggested connections for unused and n.c.pins correction.
17-Dec-2008 4Document reformatted and restructured.Added content, list of figures and tables.Added ECOPACK® packages information.
28-Feb-2011 5
Updated following figures:– Figure 13: ILIM vs Tcase
– Figure 22: Rthj-amb vs PCB copper area in open box free air condition
19-Sep-2013 6 Updated Disclaimer.
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VND920
26/26 Doc ID 7767 Rev 6
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve theright to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at anytime, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes noliability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of thisdocument refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party productsor services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of suchthird party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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