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Ankur Agarwal 1
Welcome to IC Mask Design
Training
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2
Fabrication Process
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Agenda
What we want!!!!
Steps involved in the fabrication process
N-Well Process
P-Well Process
Twin Tub Process
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What we want!!!!!
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Lets fabricate this first!!!!!
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Steps involved in the fabricationprocess
Crystal Growth
Epitaxial Growth
Film Formation
Lithography
Etching
Impurity Doping
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Crystal Growth
Techniques forgrowing single
crystals of Silicon toform a Wafer.
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General Procedure
Wafer
Single Crystal
Polycrystalline Semiconductor
Starting Material
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Single Crystal Silicon growth
Czochralski method
Silicon crystal growth from the Melt
> 90 % of the the semiconductorindustry use this option.
Starting Material : Quartzite Pure form
of Sand (SiO2)
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Czochralski Method (Contd)
SiO2is heated in a furnace along withvarious forms of carbon like coal, coke
and wood chips
SiC + SiO2 Si + SiO + CO
This produces a metallurgical- gradeSilicon with a purity of about98 %
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Czochralski Method (Contd)
Solid Silicon is pulverized and treated withHydrogen Chloride (HCl)
Si + 3HCl SiHCl3 + H2
TriChloroSaline (SiHCl3) is liquid at room
temperature Fractional distillation removes unwanted
impurities
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Czochralski Method (Contd)
Electronic grade Silicon (EGS) is gotby hydrogen reduction of SiHCl3
SiHCl3 + H2 Si + 3HCl
This reaction takes place in a reactorwith resistance-heated Silicon rod onwhich the deposition takes place.
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Czochralski Method (Contd)
ECG is a polycrystalline material of highpurity (impurity concentration is in the
order of parts-per-billion) is the rawmaterial for device-quality single crystalSilicon
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Czochralski Method (Contd)
Crystal Puller
Three main parts
A furnace which includes a fused-silicon (SiO2) crucible , a graphitesusceptor, a rotation mechanism , a
heating element and a power supply
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Czochralski Method (Contd)
A crystal pulling mechanism containsa seed holder and a counter-clockwise
rotating mechanism
An Ambient control a gas source
(argon), a flow control and a exhaustsystem
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Czochralski Method (Contd)
Crystal growing process
- Polycrystalline Silicon (EGS) is placedin the crucible and heated to its meltingpoint
- A suitably oriented seed-crystal is is
suspended in the crucible
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Czochralski Method (Contd)
- the seed crystal is slowly withdrawn
- Progressive freezing at the solid-liquid
interface yields a large, single crystal calledIngot
- typical pull rate is a few millimeters perminute
- a know amount of dopant is added to themelt to obtain the desired dopingconcentration
- For Silicon born and phosphorus are the
common dopants for p and n type materials
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Material Characterization
Wafer Shaping
Crystal characterization
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Material Characterization (Contd)
Wafer Shaping
- the two ends are removed
- the surface is grinded to to give therequired diameter
- one or more flat regions grounded
along the length of the ingot- ingots are diamond sawed to givewafers
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Material Characterization (Contd)
- Slicing determines four waferparameter
Surface orientationThickness (0.5-0.7 mm)
Taper
Bow- both the sides are lapped with amixture ofAl2O3and glycerin
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Material Characterization (Contd)
- the damaged and contaminatedregions are removed using chemical
etching- polished to provide a smooth andspecular surface
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Material Characterization (Contd)
Crystal characterization
- Crystal defects
- Material properties
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Material Characterization (Contd)
Crystal Defects
- Point defects
- Line defects
- Area defects
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Material Characterization (Contd)
Material Properties
- Resistivity
- Minority carrier lifetime- Trace impurities such as oxygen and carbon
- Surface flatness
- Slice Taper- Slice Bow
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Epitaxial Growth
Growth of crystal of one mineral onanother to achieve same structural
orientation Methods
- Chemical-Vapor Deposition
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Chemical-Vapor Deposition
Also know as Vapor-Phase epitaxy
Silicon Tetrachloride (SiCl4),
Dichlorosilane (SiH2Cl2), trichlorosilane(SiHCl3) and Silane (SiH4) are used
SiCl4 + 2H2 Si + 4HCl
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Chemical-Vapor Deposition
A competing reaction also takes place
SiCl4 + Si 2SiCl2
Etching will take place if theconcentration is too high.
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Chemical-Vapor Deposition(Contd) Diborane (B2H6) is used as p-type
dopant
Phospine (PH3) or Arsine (AsH3) is usedfor n-type
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Film Formation
Several different layers of thin film need to befabricated during IC fabrication
Thin films can be classified as- Thermal Oxides
- Dielectric layers
- Polycrystalline Silicon- Metal Films
Chemical-Mechanical Polishing
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Film Formation (Contd)
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Thermal Oxidation
Gate-oxide and Field-oxide fall are grownusing this technique
Gate-Oxide is the layer below which aconducting channel is formed between sourceand drain
Field-Oxide provides isolation from otherdevices
Gate-Oxide and Field-Oxide are grown usingthermal oxidation
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Thermal Oxidation (Contd)
Setup of Thermal Oxidation
- Filtered flow of air is maintained is
maintained at one end of the cylindrical tube.This minimizes dust and particulate matters inthe air surrounding the wafers and minimizecontamination during wafer loading
- Oxidation temperature is generally 9000c 12000c
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Thermal Oxidation (Contd)
- Oxidation system uses microcomputers toregulate the gas flow sequence, automaticinsertion and removal of wafers, to ramptemperature, to maintain the oxidationtemperature
- Dry Oxidation
Si + O2
SiO2
- Wet Oxidation
Si + 2H2O SiO2 +2H2
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Dielectric Deposition
Used for deposition of insulation layerand the passivation layer
Three commonly used methods
- Atmosphere-pressure CVD
- Low-Pressure CVD
- Plasma-enhanced CVD
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Dielectric Deposition (Contd)
Setup ofAtmospheric-Pressure CVD and Low-Pressure CVD are similar to the Thermal
oxidation chamber. The gases used aredifferent.
Setup of Plasma-Enhanced CVD
- RF voltage causes the plasma discharge
- Temperature is maintained at 100-4000cusing resistance heater
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Silicon Dioxide Deposition
Used to insulate multilevel metallization,to mask ion implantation diffusion and
to increase the thickness of thethermally grown SiO2 For low temperature (300-5000C)
deposition, film is formed by reacting
Silane (SiH4) and oxygenSiH4 + O2 SiO2 +2H2
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Silicon Dioxide Deposition (Contd) For intermediate temperature (500-8000C)
deposition, TetraEthylOrthoSilicate
(Si(OC2H5)4) is decomposed in a LPCVDSi(OC2H5)4 SiO2 + by-products
For high temperature (9000C) deposition,SiO2 is deposited by reacting DiChloroSilane
(SiCl2H2) with Nitrous oxide (N2O)SiCl2H2 + 2N2O SiO2 + 2N2 +2HCl
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Silicon Nitride Deposition
Acts as good barrier for water andsodium, excellent scratch protection, as
mask for selective oxidation of silicon In LCPVD process, DiChloroSilane and
ammonia react at700-8000C to deposit
Silicon Nitride3SiCl2H2 + 4NH3 Si3N4 + 6HCl + 6H2
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Silicon Nitride Deposition (Contd)
Silicon Nitride is formed by reactingSilane and ammonia in an argon
discharge or Nitrogen dischargePlasma-Enhanced CVD
SiH4 + NH3 SiNH + 3H22SiH4 + N2 2SiNH + 3H2
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PolySilicon Deposition
Used as gate electrode, high valueresistor and also as conductor for shot
length LPCVD operating at600-6500C is used
to react pyrolyzing silane according to
the following reactionSiH4 Si + 2H2
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Metallization
Physical vapor deposition
- Evaporation and E-Beam Evaporation
When a source of material is heated above itsmelting evaporation occurs. The evaporatedatoms travel at high velocity and gets settledon the wafer surface. The heating is done
through resistance heating, rf heating orthrough the use of electron beam
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Metallization (Contd)
- Ion Beam Sputtering
A source of Ion beam is accelerated and
impinged on the surface of thesemiconductor wafer. Magnetic field isused to increase the efficiency
Chemical vapor deposition (CVD) is alsoused for certain metals
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Chemical-Mechanical Polishing
Used for global planarization
It consists of the sample surface against a
pad that carries slurry between them Abrasive materials in the slurry cause
mechanical damage on the sample surfaceloosening the material for enhanced chemical
attack or fracturing of the pieces of thesurface into slurry where they dissolved orswept away
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Lithography
Lithography is the process of transferringpatterns of geometric shapes on a mask to a
thin layer of radiation-sensitive material calledphoto-resist covering the surface of asemiconductor wafer. These patterns definethe various regions of a integrated circuit
And you as a IC Layout mask designer will bedefining these mask
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Optical Lithography
Vast majority of lithographicequipments for IC fabrication is Optical
equipments using ultraviolet light
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The Clean Room
Clean rooms are necessary because dustparticles in the air can settle on
semiconductor wafers and the lithographicmasks and can cause defects in the devices,which will result in the circuit failure
The total number of dust particles, the
temperature and the humidity are controlledin a clean room
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The Clean Room (Contd)
Two systems to define a clean room
1. English system the numerical
designation of the class is taken from themaximum allowable number of particles0.5m and larger, per cubic foot
2. Metric system the class is taken form
the logarithm (base 10) of the maximumallowable number of particles 0.5m andlarger, per cubic meter
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Exposure Tools
The pattern transfer process isaccomplished by using a lithographic
exposure tool Three parameters define the
performance
- Resolution
- Registration
- Throughput
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Exposure Tools (Contd)
Resolution is the minimum featuredimension that can be transferred with highfidelity to a resist film on a semiconductorwafer
Registration is a measure of how accuratelypatterns on successive masks can be aligned(or overlaid) with respect to the previously
defined patterns on wafer Throughput is the number of wafers that
can be exposed per hour for a given masklevel
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Exposure Tools (Contd)
Two optical methods
- Shadow printing
- Projection printing
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Exposure Tools (Contd)
Shadow printing
- Contact printing The mask and
the wafer are in direct contact
- Proximity printing - The mask andthe wafer are in close proximity
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Exposure Tools (Contd)
Projection printing
- The mask patterns are projected on to the
resisted-coated wafer many centimeters awayform the mask
- To increase resolution only a small portionof the mask is exposed at a time and the area
is scanned or stepped over the wafer to coverthe entire surface
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Exposure Tools (Contd)
Four methods
- Annual-field wafer scan
- 1:1 Step-and-Repeat
- M:1 reduction step-and-repeat
- M:1 reduction step-and-scan
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Exposure Tools (Contd)
Ultraviolet source
- High-pressure mercury-arc lamp is
widely used 436nm 0.3m
- KrF excimer laser 248nm 0.18m
- ArF excimer laser 193nm 0.10m
- F2 excimer laser 157nm 0.07m
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Masks
Using EDA tools, layout designerscompletely describe the circuit patterns
electrically The digital data produced by the EDA
tool then drives a pattern generator,
which is an electron-beam lithographicsystem that transfers the patternsdirectly to electron-sensitized mask
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Masks (Contd)
The mask consists of a fused silica substratecovered with chromium layer. 15x15cm2 in
size and0.6cm in thickness
The pattern on a mask defines one level of anIC design. The composite layout is brokeninto mask levels that correspond to the IC
process sequence Typically 15-20 different mask levels are
required for a complete IC process cycle
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Masks (Contd)
Defects can be introduced during themanufacture of mask or during thesubsequent lithographic processes
Yield is defined as the ratio of number ofgood chips to the total number of chips perwafer
y = e DA , where D(Defect Density) is theaverage number of fatal defects per unit areaand A is the area of a chip
For a N level mask the final yield is y = e -NDA
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Photoresist
A radiation-sensitive compound
Types
- Positive resists The exposed regionbecomes more soluble and can be removedof more easily during development. Thepattern formed is same as on the mask
- Negative resists The exposed regionsbecome less soluble and the pattern formedis the reverse of that on the mask
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Photoresist (Contd)
Positive resist
- Consists of a photosensitive compound, a
base resin and an organic solvent- Prior to exposure the photosensitivecompound is insoluble in the developersolution. After exposure, the photosensitive
compound absorbs the radiations, changes itschemical structure and becomes soluble inthe developer solution
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Photoresist (Contd)
Negative resist
- Consists of polymers combined with a
photosensitive compound- After exposure, the photosensitivecompound absorbs the optical energy andconverts it into chemical energy to initiate a
polymer linking reaction. These cross-linkedpolymers become insoluble in the developer
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Etching
Cleaning of the wafer to removecontamination that results from handling andstoring and also for selective removal of
certain portion of the deposited material on awafer
The material to be removed can be thecontamination, insulating layer, the
photoresist, the metal layers et al Two methods are :
- Wet Chemical etching
- Dry or Plasma Etching
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Wet Chemical Etching
Three basic steps are involved
- The reactants are transported by
diffusion to the reacting surface- Chemical reaction occurs at the
surface
- The products form the surface areremoved by diffusion
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Wet Chemical Etching (Contd)
Silicon Etching
- First the silicon is oxidized using Nitric acidin water or acetic acid (CH3COOH)
Si + 4NHO3 SiO2 + 2H2O + 4NO2- HydroFluoric acid is used to dissolve theSiO2 layer
SiO2 + 6HF
H2 SiF6 + 2H2O Polysilicon etching is similar to Si etching
except the rate of etching is faster and henceneed to be controlled precisely
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Wet Chemical Etching (Contd)
Silicon Dioxide Etching
- SiO2 etching is accomplished using a dilutesolution of HydroFluoric acid
SiO2 + 6HF H2 + SiF6 + 2H2O
Silicon Nitride Etching- Si3N4 is etched using HydroFluoric (HF) acidand Phosphoric acid (H3PO4)
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Wet Chemical Etching (Contd)
Aluminum Etching
- Etched using heated solutions of
Phosphoric acid, Nitric acid, acetic acidand DI water
- Nitric acid (HNO3) oxidizes the
aluminum and then the oxide isdissolved in Phosphoric acid (H3PO4)
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Dry or Plasma Etching
Plasma is a fully or partially ionized gascompound
When an electric field of sufficientmagnitude is applied to a gas, the gasbreakdowns and becomes ionized
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Plasma Etching (Contd)
Plasma Etching process takes place in 5 steps
- The etchant species is generated in plasma
- The reactant is then transported bydiffusion through the stagnant gas layer tothe surface
- The reactant is absorbed on the surface
- Chemical reaction takes place to form avolatile compound
- The compounds are desorbed in from thesurface, diffused into the bulk gas and
pumped out of the system
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Plasma Etching (Contd)
Two methods
- Physical Method
Positive Ions bombard the surface athigh velocity
- Chemical Method
Neutral reactive species generatedby the plasma interact with the materialsurface to form volatile products
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Impurity Doping
Introduction of controlled amounts ofimpurity dopants into the
semiconductor. This changes theelectrical properties of thesemiconductors
Two methods
- Diffusion- Ion Implantation
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Diffusion
Dopant atoms are placed on or near thesurface of the wafer by deposition from
the gas phase of the dopant or by usingdoped-oxide sources
At elevated temperatures, the dopant
diffuses into the wafer because of highconcentration
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Open tube diffusion system
Wafer is placed in a controlled hightemperature quartz-tube furnace
Gas containing the required dopant ispassed over it at around 6000C
Boron is used for p-type
Arsenic and Phosphorous are used forn-type
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Open tube diffusion system (Contd)
An example for phosphorous diffusionusing a liquid source is
4POCl3 + 3O2 2P2O5 + 6Cl2P2O5 forms a glass on silicon wafer and is
then reduced to phosphorous by Si
2P2
O5
+ 5Si 4P + 5SiO2
Phosphorous then diffuses into the waferand Cl2 is released
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Ion Implantation
Introduction of energetic, chargedparticles into a substrate
More precise control and reproducibilityof impurity doping and its lowerprocessing temperature
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