Chapter 10 Input/Output Interface Circuits and LSI Peripheral Devices

Chapter 10 Input/Output Interface Circuits and LSI Peripheral Devices

• 1. Core and special-purpose I/O interface

• 2. Byte-wide output ports using isolated I/O

• 3. Byte-wide input ports using isolated I/O

• 4. Input/output handshaking and a parallel printer interface

• 5. 82C55A programmable peripheral interface

• 6. 82C55A implementation of parallel input/output ports

• 7. Memory-mapped input/output ports

Chapter 10 Input/Output Interface Circuits and LSI Peripheral Devices

• 8. 82C54 programmable interval timer

• 9. 82C37 programmable direct memory access controller

• 10. Serial communication interface

• 11. Programmable communication interface controller

• 12. Keyboard and display interface

• 13. 8279 programmable keyboard/display controller

Fig.10-1 Sixty-four-line parallel output circuit

A15L=1

Figure 10.1 Sixty-four-line parallel output circuit for 8088 microcomputer

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Chapter 10 Homework

• 3, 5, 7, 9, 13, 15, 17, 19, 21, 23, 25, 27,

• 29, 31, 33, 35

• 39, 43, 45, 47, 50, 55, 59, 61, 65, 67, 69

Fig. 10.1 output address

Output the byte contents of the memory address

Output the byte contents of the memory address

Figure 10.2 Driving an LED

Figure 10.3 Sixty-four-line parallel input circuit

I/O address of part 7

Input the byte contents of input port 7

Reading the setting of a switch

Parallel printer

interface

I/O interface and

handshaking

Figure 10.6 Handshaking printer interface circuit

A15L=1

Ex 10.5 Port address

Ex 10.6Flowchart

Ex 10.6

10.5 82C55A Programmable peripheral interface

• 82C55 provides a flexible parallel interfaces, which includes features such as single-bit, and byte-wide input output ports; level-sensitive inputs; latched outputs; strobed input and outputs; strobed bidirectional input/output. These features are selected under software control.

• 8-bit bidirectional data bus• Read/write control signals• Register select code• Chip select and reset

Figure 10.7 Block

diagram of the 82C55A

Figure 10.8 Addressing an

82C55A using the microprocessor

interface

1

Figure 10.9 Control-word bit

functions

It must be at logic 1(active) Whenever the mode of operationis to be changed

Operation mode

• Mode 0 selects what is called simple I/O operation. By simple I/O, we mean that the lines of the port can configured as level-sensitive inputs or latched output.

• Fig. 10-11

Control words I/O configurations

Figure 10.10 Mode 0 port pin functions

Ex 10.7 Mode 0 operation Fig. 10-11 (c)

Mode 0 control words and

corresponding input/output

configuration

Figure 10.11

Figure 10.11

Mode 1 operation

• Mode 1 operation represents what is known as strobed I/O. The ports of the 82C55A are put into this mode of operation by setting D7=1 to activate the mode-set flag and setting D6D5=01 and D2=1.

• In this way, the A and B ports are configured as two independent byte-wide I/O ports, each of which has a 4-bit control/data port associated with it. The control/data ports are formed from the lower and upper nibbles of port C, respectively. Fig10-12 lists the mode 1 functions of each pin at ports A, B, and C.

Figure 10.12 Mode 1 port pin functions

Figure 10.13 Mode 1, port A input configuration

Figure 10.14 Timing

diagram for an input port in

mode 1 configuration

Control signals

• Strobe input: STB

• Input buffer full: IBF

• Interrupt request: INTR

• Acknowledge: Ack

• Interrupt enable: INTE

• Output buffer full: OBF

Ex 10.8

Figure 10.15 Mode 1, port B configuration

Mode 2 operation

• Mode 2 represents the strobed bidirectional I/O

• The key difference is that now the port works as either inputs or outputs and control signals are provided for both functions. Only port A can be configured to work in a 8-bit bidirectional I/O.

Figure 10.16 Mode 2 port pin functions

Figure 10.17 Mode 2 input/output configuration

Figure 10.18 Bit set/reset format

Ex 10.9

Ex 10.9

Figure 10.19 Combined mode 2 and

mode 0

Figure 10.10 Control word

in control register

Figure 10.11 Control word in control register

Mode 1 status information

• The format of the status information input by reading port C of an 82C55A operating in mode is shown in Fig. 10-20(a). Note that if the ports are configured for input operation, the status byte contains the values of the IBF and INTR outputs and INTE flag for both ports. Once read by the MPU, these bits can be tested with other software to control the flow of the program.

• By using a software handshake sequence that tests the bits to change the program sequence, hardware signals such as interrupts can be saved.

Figure 10.20 Mode 1 status information for port C

10.6 82C55A Implementation of parallel input/output ports

• The 82C55A PPI can be used to design a more versatile parallel I/O interfaces. This is because its ports can be configured either as input or outputs under software control.

• Address bus port numbers

• Data bus Port (channel)

Figure 10.21 82C55A parallel I/O ports in an

8088-based microcomputer

Ex 10.12 Port C of PPI 14

Ex 10.12 Port C of PPI 14

Ex 10.13 Input from ports B and C and output to port A

Figure 10.22 82C55A parallel I/O ports at even and odd address

boundaries

Figure 10.23 Memory-mapped 82C55A

parallel I/O ports

Ex 10.14 Which I/O port?

Ex 10.14 Which I/O port?

Ex 10.15 Output port: port A,

Input ports: port B and C

Ex 10.16 Output

port: port A,

Input ports: port B and C

Figure 10.24 Memory-mapped 82C55A parallel

I/O ports

10.8 82C54 Programmable interval timer

• The 82C54 is an LSI peripheral designed to permit easy implementation of timer and counter functions in microcomputer system.

• The 82C54 contains three independent 16-bit counters that can be programmed to operate in a variety of implement timing functions.

• For instance, they can be set up to work as a one-shot pulse generator, square-wave generator, or rate generator.

82C54 control signals

• Control signal: Read (RD), Write (WR),• Chip-select (CS)• GATE: The gate input is used to enable or

disable the counter• Clock: The clock input are used to

decrement counter 0.• OUT0:The counter produces either a clock

or a pulse at OUT0

Architecture of the 82C54

• 82C54: data bus buffer, read/write logic, control word register, and three counters.

• The control word register section actually contains three 8-bit registers used to configure the operation of counter 0, 1, and 2.

• The control word format is shown in Fig. 10-27.

Figure 10.25 Block diagram of the 82C54 interval

timer

Figure 10.26 Internal architecture of the 82C54

Figure 10.27 Control word format of the

82C54

Ex 10.17 Control word format

Ex 10.18 Setting up the three counters

Ex 10.18 Setting up the three counters

Ex 10.18 Setting up the three counters

Ex 10.19The contents of the count registers can also be read without first inhibit the counter. That is, the count can be read on the fly. To do this in software, a command must first be issued to the mode register to capture the current value of the counter

into a temporary internal storage register.

Ex 10.19

Read-back mode

• Read-back mode permits a programmer to capture the current count values and status information of all three counters with a single command.

• For instance, to capture the values in all three counters, the read-back command is 110111102=DE16. This command must be written into the control word register of the 82C54.

Read-back mode

• Fig. 10-31 shows some other examples of read-back commands. Note that both count and status information can be latched with a single command.

• Our read-back command example, DE16, only latches the values of the three counters. The programmer must read these values by issuing read commands for the individual counters. Once the value of a counter or status is latched, it must be read before a new value can be captured.

Read-back command

• The first command if Fig. 10-31, 110000102=C216, captures both the count and status information for counter 0. When both count and status information is captured with a read-back command, two read-counter commands are required to return the information to the MPU.

• During the first read operation, the value of the count is read, and the status information is transferred during the second read operation.

Figure 10.30

Figure 10.31

Figure 10.32

Operating modes of 82C54 counters

• The 82C54’s counters can be configured to operate in one of six modes.

• Note that mode 0 operation is known as interrupt on terminal count and mode 1 is called programmable one-shot.

• The GATE input of a counter takes on different functions, depending on which mode of operation is selected.

• For instance, in mode 0, GATE disables counting when set to 1.

Figure 10.33 Operating

mode of the 82C54

The interrupt on terminal count mode

• The interrupt on terminal count mode of operation is used to generate an interrupt to the microcomputer after a certain interval of time has elapsed, as shown in the waveform for mode 0 operation in Fig. 10-33.

Ex 10.20 Mode 0 operation

Ex 10.20 Mode 0 operation

Ex 10.20 Mode 0 operation

Mode 1 operation

• Mode 1 operation implement what is known as a programmable one-shot. As Fig. 10-33shows, when set for this mode of operation, the counter produces a simple pulse at its output.

Ex 10.21 Mode 1 operation

Figure 10.36 Mode 1 operation

Mode 2 operation

• When set for mode 2, rate generator operation, the counter within the 82C54 is set to operate as a divide-by-N counter. Here N stands for the value of the count loaded into the counter.

Ex 10.22 Mode 2 operation

Figure 10.37 Mode 2 operation

Ex 10.23 Mode 3 operation

Figure 10.38 Mode 3 operation

Ex 10.24 Mode 4

operation

Ex 10.24 Mode 4 operation

10.9 82C37A Programmable direct memory access controller

• DMA capability permits devices, such as peripherals, to perform high-speed data transfers between either two sections of memory or between memory and I/O device.

Figure 10.40

Figure 10.41

Figure 10.42 DMA interface to I/O devices

Figure 10.43 Internal architecture of the 8237A

Figure 10.44 Internal registers of the 8237A

Figure 10.45 Accessing the registers of the

82C37A

Figure 10.46 Command register format

Ex 10.25

Figure 10.47 Mode register format

Ex 10.26

Figure 10.48 Request register format

Figure 10.49 Single-channel mask-register command format

Figure 10.50 Status register

Ex 10.27

Ex 10.27

Figure 10.51 8088-based

microcomputer with 82C37A

DMA Interface

Figure 10.52 Synchronous communication interface

Figure 10.53 Asynchronous communication interface

Figure 10.54 Simplex, Half-duplex, Full-duplex

Simplex, Half-duplex, Full-duplex

• Simplex: A single unidirectional communication link

• Half-duplex: Data are transmitted and received over the same line. (transmission and reception of cannot data take place at the same time)

• Full-duplex: data can be transferred in both direction at the same time.

Ex 10.28Baud rate: the number of bits data transferred per second

The RS-232C Interface

• The RS-232C interface is a standard hardware interface for implementing asynchronous serial data communication ports on devices such as printers, CRT terminals, keyboards, and modems.

• The Electronic Industries Association (EIA) defines the pin definitions and electrical characteristics of this interface. The aim behind publishing standards, such as the RS-232C, is to assure compatibility between equipment made by different manufacturers.

The RS-232C Interface

Asynchronous serial data

• Higher reliability

• Low-cost

• Compatibility

• Lower speed

The RS-232C Interface

• The RS-232C standard defines a 250pin interface. Fig. 10-55 lists each pin and its function. Note that the three signals, transmit data (TxD), receive data (RxD), and signal ground are located at pins 2, 3, and 7

• Pins 4 and 5 are the request-to-send and clear-to-send control signal.

Figure 10.55RS-232C

interface pins and functions

Figure 10.56 A DTE-to-DTE serial communication connection

DTE: Data Terminal Equipment

RS-232C

• Distance: 100 feet

• Voltage level: +5V~+15V at the transmitting end, +3 V~ or more at the receiving end.

• 9600 baud=9600 bits/sec

Figure 10.57Universal synchronous/asynchronous receiver transmitter (USART)

Figure 10.58 Read/Write operations

Ex 10.29

Figure 10.59 Receiver and transmitter driven at the same baud rate

Figure 10.60 Mode instruction format

Ex 10.30

Ex 10.30

Figure 10.61

Figure 10.62

Figure 10.63

Ex 10.31

Ex 10.31

Ex 10.31

Figure 10.64

Figure 10.65

Figure 10.66

Figure 10.67

Figure 10.68

Ex 10.32

Figure 10.69

Figure 10.70

Figure 10.71

Figure 10.72

Figure 10.73

Figure 10.74

Figure 10.75

Figure 10.76

Ex 10.33

Ex 10.33

Ex 10.33

Figure 10.82

Figure 10.83

Ex 10.34

Figure 10.84

Figure 10.85