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The TI-UPRM Program: A Model for Industry-Academia Collaboration
Dr. Manuel JiménezProfessor
September 2010
University of Puerto Rico at Mayagüez Electrical and Computer Engineering Department
OutlineTI-UPRM Program StructureThe TI-UPRM Research/Co-op ModelProgram HighlightsSample ProjectsThe IAPContact Info
Undergraduate ECE Program Highlights
A five year programComprehensive curriculum: 168+ credit-hoursHeavy design component across curriculumCapstone design experienceResearch opportunitiesHands on experience
Bilingual Program (Spanish /English)All Puerto Rican students are US citizens
Flexible and up to date curriculum Strong faculty-student interaction
MentoringSmall class sizes
The TI-UPRM ProgramObjective:Strengthening the academic and research programs in Electronics
Methodology:Creation of an educational model that combines research and Co-op education
Outcomes:Full fledged industrial- academic partnership with benefits for all involved parties
University Commitment
& Support
University Commitment
& Support
Industry Support &
Involvement
Industry Support &
Involvement
Increased faculty
involvement
Increased faculty
involvement
Infrastructure development
Infrastructure development
Curricular improvements
Curricular improvements
Electronics scholarships Electronics
scholarships
Graduate-level support
Graduate-level support
Collaborative research projects
Collaborative research projects
Co-op/FT recruitment
plan
Co-op/FT recruitment
plan
The TI-UPRM Collaborative
Program
The TI-UPRM Collaborative
Program
The Research/Co-op ModelCombines traditional Co-op education with undergraduate and graduate research experiences
COOP
Academic Research
COOP Experience
Side Project
Academic Research
Side project Presentation
Pre-COOP
Post-COOP
Industry & Academic Mentors
General Education
Technical Background
Faculty Mentoring
COOP Supervisor
Company Presence
Participant Professors and CollaboratorsLead
Manuel JiménezRogelio PalomeraGladys O. Ducoudray
CollaboratorsDomingo Rodriguez (DSP)Shawn Hunt (DSP)Nelson Sepulveda (Materials)Nayda Santiago (Computing)Raúl Torres (Control)Jaime Arbona (Electronics)Guillermo Serrano (Electronics)Manuel Toledo (Electronics)
Infrastructure & Program Support Integrated Circuits Design Laboratory (ICDL):
Undergraduate and Graduate Teaching/Research Lab. for Analog and Mixed-signal Systems
Electronic Testing and Characterization Lab. (ETC)Wafer- and IC-level electronic testing and characterization
Rapid Systems Prototyping Laboratory (RASP):Graduate research in system-level hardware implementations
Digital Signal Processing Laboratory (DSP-Lab):Support to DSP Laboratory. Extensive use of TMS320
Microprocessor Development Systems Lab. (MDS):Support through donations for teaching and undergraduate research. Extensive use of MSP430
Academic OutcomesElectronics Courses at UPRM
Seven New Courses CreatedFive Re-activated & Improved CoursesTwo supported Courses
Twenty Technical WorkshopsTesting, VHDL/Verilog, MEMs, etc…
28 Professional Advancement WorkshopsFocused on soft skills sharpening
Six Distinguished Lecturers
Some UPRM/TI Program OutcomesOver 125 students in twelve years
112 Co-op students (undergrad & grad)Over 27 TI patents by program studentsDevelopment of modeling and testing methods now adopted by TI worldwideApplication Notes used by TI worldwideOver 70 refereed papers in last eight years
54 student co-authored publicationsThirty-one master theses
Samples of Research OutcomesBehavioral Macromodels for Sigma-Delta Modulators in Oversampled Data Converters (TI Wireless)
LDMOS Characterization (ATD)
~SMU
Channel
GateDriver
Samples of Project OutcomesIrDA on the MSP430 (HPA/ASP)
Performance-driven DesignLow-EMI PCB Layout Techniques for Power Electronics PCBs
Actual IPEM & Gate Driver
Electronic Design AutomationHigh-level Partitioning Methods for Discrete Signal Transforms on Distributed Hardware Architectures
16422
422244444 )))()(()(( PFITIFIIFF ⊗⊗⊗⊗=×
Partitioned structure:
F2
F2
F4
F4
F4
F4
F2
F2
F2
F2
F2
F2
F2
F2
F2
F2
F2
F2
F2
F2
Scheduled partition requires a latency of 116 cycles.
16)(max , =⎟⎟⎠
⎞⎜⎜⎝
⎛= ∑
∈∈ stagesiippathspobj cCostF
Kronecker to GraphConversion Partition/placement
Formulationmanipulator
Area/communicationestimators
DSTKronecker Formulation
HL Description ofTarget Architecture
ImplementationConstraints
High-level partition solution
M0
D0
M1
D1
Mk-1
Dk-1
Crossbar
Partitioning Methodology
Rapid Prototyping TechniquesScalable Floating-point Pease FFT based on UPRM component library
0
10
20
30
40
50
60
70
80
90
100
0 10 20 30 40 50 60 70
Number of points
Slic
es [%
]
f = 1f = 2f = 4
0
20
40
60
80
100
120
140
0 10 20 30 40 50 60 70
Number of points
Max
imum
freq
uenc
y (M
Hz)
f = 1f = 2f = 4
Industrial Affiliates Program (IAP)Provides funds for undergraduate research
Funded by private industry donations
Projects extend for eight monthsFaculty supervisionTwo yearly events:
April & October
Managed by IAP Coordinator Faculty CommitteeIndustry Board Gregg Lowe’s keynote at IAP 20th anniversary
IAP Benefits to TI-UPRM ProgramTI participation for over 12 years
Over 70% of TI recruits at UPRM have been IAP’sProject Incubator
Research projects with TIersMaster student thesis generatorSource for side projects for Co-Ops
Student TrainerVirtual one-year long technical interviewSpecialized technical subject trainer
Topics and toolsSoft skill developer
Independent & team work, presentation, paper writing, etc.
Recent TI-related IAP Projects2009 (From 19 projects)
Study of Transient Vt Shifts in MOSFETSStudents: Sonny Zamot, Yadriel Torres, Willie GonzalezParametric DC Measurements in Circuit ComponentsStudents: William Morales, Juan GarcíaDesign of a VLCT Interface (Part II)Students: Jose Rivera, Jose J. Torrres, Jorge MasFuzzy Compensation Scheme for an Analog IC Configuration (Part II)Students: Pedro Escalona, Aldo BrianoPower Profile of an MSP430 (Part II)Students: Bryant Mercado, David CouvertierDA Converter with Offset Cancellation using Floating GatesJose A. Rivera, Marcelo Quiles
2008 (From 16 projects)SMU Emulation on Keithley 26xxStudents: Rafael Vega, Jorge Moreno, OsvaldoGonzalezFuzzy Compensation Scheme for an Analog IC Configuration (Part I)Students: Pedro Escalona, Aldo BrianoCharacterization of Ferroelectric CapacitorsStudents: Eliud Torres, TBDDesign of a VLCT Interface (Part I)Students: Jose Rivera, Jose J. Torrres, Jorge MasPower Profile of an MSP430 (Part I)Students: Bryant Mercado, María T. Perez, Marinés Chaparro
2007 (From 21 projects)Improvement of the Audio Fidelity, Weight and Output Power of a Class-D Amplifier SystemStudents: Omar Vicente, Javier TafurProgrammable Active Filter ApplicationsStudents: Joel Rosario, Gloria Pizzitola, Pedro Escalona, José PegueroAutomation of PCB Inspection AreaStudents: Rubén Nieves, Javier Tafur, Alex Torres Complex Floating Point Adder for Signal Processing Applications on FPGAsStudents: Jazmin Lantigua, Arnaldo Cruz
2006 (From 24 projects)Design of an Operational TransconductanceAmplifier for Oversampled Data convertersStudents: Christian Medina, William RiveraLow Power-Low Voltage Analog Building Block for Analog to Digital ConvertersJorge Arbona
2005 (From 19 projects)Design of a Current Feedback Operational AmplifierStudents: Francisco Collazo, Marcos Lopez
Design and applications of a MicrocontrollerStudents: Ruben Nieves, Hector Irizarry, Wilfredo
Bermudez, Jose Rodriguez Automatic Generation of Equivalent Circuits Containing NullorsStudents: Abel Labour, Rafael Leavit, Obed Caban
Contact InformationDr. Manuel JiménezEmail: mjimenez@ece.uprm.eduPhone: (787)832-4040 Ext. 3780
Electrical and Computer Engineering DepartmentUniversity of Puerto Rico at MayagüezP.O. Box 9000Mayagüez, PR 00681-9000Fax: (787)831-7564
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