Trends and Challenges in VLSI Technology Scaling

Trends and Challenges in VLSI Trends and Challenges in VLSI Technology ScalingTechnology Scaling

G. Baccarani

Advanced Research Center on Electronic Systems (ARCES),Department of Electronics (DEIS) – University of Bologna, Italy

University of Bologna

Summer School on Information Engineering26-30 June, 2006, Bressanone, Italy


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Outline

Evolution from micro- to nano-electronicsDevice miniaturization and scaling theoryThe ITRS and its impact on the research areaEvolution of interconnects and packagingFunctional requirements of CMOS logic gatesNew device architecturesDevice modeling issuesConclusions


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Size of the Electronic Market


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Working at the length scale of 1-100 nm to create materials, devices, and systems with fundamentally new properties and functionsbecause of their nanoscale size.

from www.nano.gov

Definition of Nanotechnology


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70 nm Gate Length FET

70 nm


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ENIAC - the First Electronic Computer (1946)


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First transistorBell Labs, 1948

The First Transistor (1948)


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The Nobel Prize in Physics 1956"for their researches on semiconductors and their discovery of the transistor effect"

William B. Shockley John Bardeen Walter H. Brattain

The Transistor Revolution (1948)


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J. Kilby:Two transistors laid out onto the same semiconductor substrate and connected by external wiring

R. Noyce: Two transistors laid out onto the same semiconductor substrate and connected by on-chip metallization

The First Integrated Circuit (1961)


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Bipolar logic1960’s

ECL 3-input GateMotorola 1966

The First Commercial Integrated Circuit (1966)


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INTEL 4004 Microprocessor (1971)M. Huff – F. Faggin1000 transistors1 MHz operation

The First Microprocessor (1971)


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INTEL Pentium IVMicroprocessor 42 Million Transistors

INTEL Pentium IV Microprocessor


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In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology would double its effectiveness every 18 months

Moore’s Law (1964)


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1 61 51 41 31 21 11 0

9876543210

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

LOG

2 OF

THE

NU

MB

ER O

FC

OM

PON

ENTS

PER

INTE

GR

ATE

D F

UN

CTI

ON

Electronics, April 19, 1965.

Moore’s Law


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Evolution of Complexity


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40048008

8080 80858086

286386

486 Pentium® procP6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Tran

sist

ors

(MT)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years

Courtesy, Intel

Moore’s Law for Microprocessors

Pentium IVPentium III

Pentium II


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40048008

80808085

8086286

386486 Pentium ® procP6

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

Die size grows by 7% per year to satisfy Moore’s LawDie size grows by 7% per year to satisfy Moore’s Law

Courtesy, Intel

Die Size Growth


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Outline

Evolution from micro- to nano-electronicsDevice miniaturization and scaling theoryEvolution of interconnects and packagingThe ITRS and its impact on the research areaFunctional requirements of CMOS logic gatesNew device architecturesDevice modeling issuesConclusions


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Why Scaling?

Technology shrinks by 0.7/generationWith every generation we can integrate 2x more functions per chip; chip cost does not increase significantlyCost of a function decreases by 2xBut …

How to design chips with more and more functions?Design engineering population does not double every two years…

Hence, a need for more efficient design methodsExploit different levels of abstraction


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Technology Scaling Models

Full Scaling (constant electric field)Dimensions and voltages scale together by the same factor λ

Fixed Voltage ScalingOnly dimensions scale; voltages remain constant

General ScalingVoltages and dimensions scale by different and independent factors


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Constant Field Scaling (Long-channel FETs)


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Constant-Field Scaling (Short-Channel FETs)


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Constant-Field Scaling (Short-Channel FETs)

(R.H. (R.H. DennardDennard, IBM, 1978), IBM, 1978)


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Fixed-Voltage Scaling (Long-Channel FETs)


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Fixed Voltage Scaling (Short-Channel FETs)


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Generalized Scaling Theory


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Scaling Relationships (Long-Channel FETs)


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Scaling Relationships (Short-Channel FETs)


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1 cm 1 mm

100 µm

10 µm

1 µm

100 nm

insects

biological cells

large bacteria

hair diameter

viruses nerve fibers

groove spacing on CD

10 nm

DNA

nano scale

Feature size scaling


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Source: Intel – ISTAC Meeting 2-2004

Si technology: complexity increasing exponentially


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BoronPhosphorousAluminumSiO2Silicon1970

Silicon-GermaniumMetal gatesHigh-k dielectricsLow-k dielectricsCopper interconnectsTungsten plugsCobalt silicideTitanium silicideNichel silicideBPSGPolysiliconSilicon nitrideOxinitridesIndiumArsenicBoronPhosphorousAluminumSiO2Silicon2000

Complexity and acceleration

10 0

10 1

10 2

10 3

1990 1995 2000 2005 2010 2015 2020

Lg

(nm

)

Effective scaling rate

1999

2001

1994

Devic

e d

imen

sio

ns

[nm

]


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P6Pentium ® proc

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Freq

uenc

y (M

hz)

Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years

Doubles every2 years

Courtesy, Intel

Clock Frequency


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P6Pentium ® proc

486386

2868086

808580808008

4004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Pow

er (W

atts

)

Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase

Courtesy, Intel

Power Dissipation


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5KW 18KW

1.5KW 500W

4004800880808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Pow

er (W

atts

)

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

Courtesy, Intel

Power Dissipation Trend


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400480088080

8085

8086

286 386486

Pentium® procP6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Pow

er D

ensi

ty (W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp

Courtesy, Intel

Power Density


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Outline



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ITRS Technology Nodes


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ITRS Technology Nodes


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Medium High Very HighVariability

Energy scaling will slow down>0.5>0.5>0.35Energy/Logic Op scaling

0.5 to 1 layer per generation8-97-86-7Metal Layers

11111111RC Delay

Reduce slowly towards 2-2.5<3~3ILD (K)

Low Probability High ProbabilityAlternate, 3G etc

128

11

2016

High Probability Low ProbabilityBulk Planar CMOS

Delay scaling will slow down>0.7~0.70.7Delay = CV/I scaling

256643216842Integration Capacity (BT)

8162232456590Technology Node (nm)

2018201420122010200820062004High Volume Manufacturing

CMOS Outlook


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Scaling Roadblocks

Reduced line width → EUV lithography (13 nm)

Tunneling through the gate oxide → high-κdielectrics

Poly gate depletion capacitance → metal gate Propagation delay (RC) through long-distance interconnects → low-κ dielectricsThreshold voltage scaling and increased leakage currentIncreased power dissipation per unit area


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Scaling Roadblocks

Increased drain-induced barrier lowering (DIBL)Reduced subthreshold slope (SS)Increased threshold-voltage roll-off Increased gate-induced drain leakage (GIDL)Increased statistical fluctuations of the threshold voltage due to randomness of the dopant atoms Solution: new device architectures


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Outline



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Advanced Metallization

Courtesy, IBM


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Advanced Matallization

Courtesy, IBM


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Advanced Metallization

Courtesy, IBM


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Packaging


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Packaging


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Packaging


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Outline

Evolution from micro- to nano-electronicsThe ITRS and its impact on the research areaGeneralized device scalingEvolution of interconnects and packagingFunctional requirements of CMOS logic gatesNew device architecturesDevice modeling issuesConclusions


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Requirements of CMOS Logic Gates

High noise immunity → voltage gainHigh fan out → power gainHigh fan in → I/O isolationCompatibility of the I/O logic levelsHigh switching speedLow power consumption


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CMOS Inverter I/O Characteristics

VDD

VinVout

NMOS

PMOS

GND

VDD

In Out


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CMOS Inverter I/O Characteristics

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin

(V)

Vou

t(V)

VDD

Vin Vout


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Gain vs. Supply Voltage

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin (V)

Vou

t(V)

Gain=-1

0 0.05 0.1 0.15 0.20

0.05

0.1

0.15

0.2

Vin (V)

Vou

t (V)


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CMOS Inverter Delay

CLCint

Delay

Load

(CL+ Cint) VDD

IDON

Td ≈

Vin Vout

VDD


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Energy Dissipation per Switch

CL CL VDD2Ed ≈

VoutVin

VDD


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Outline



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Alternative Device Architectures

In view of a number of roadblocks which prevent standard CMOS scaling according to the ITRS provisions, new device architectures are being investigated in order to exploit the ultimate potential of the CMOS technology. Among them

Ultra-thin body silicon on insulator (UTB-SOI) FETsSilicon on insulator double-

gate (SOI-DG) FETsTri-gate FinFETs

Gate all around silicon nanowire(GAA NW) FETs.


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Alternative Device Architectures

DG-MOSFET

Source

Drain

Gate

CylindricalNanowireMOSFET

FinFET

SOI-MOSFET

CNW-FET


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Bulk CMOS vs. New Architectures

The short-channel effect (SCE) is reduced as the gate control increases; thus, DIBL, SS and ∆Vtimprove as we move from bulk to nanowire FETsfor equivalent geometriesFor an acceptable DIBL, SS and ∆Vt , the electrical oxide thickness (EOT) scaling may be relaxedUndoped silicon channels prevent statistical doping fluctuation, improve mobility and reduce parasitic capacitance effectsThe presence of two or more channels improves the current drive capability of the FETs.


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Bulk vs. New Architectures

In order to fully exploit the potential of innovative architectures technology enhancements are being investigated High-κ dielectrics for gate isolation, to increase the insulator capacitance while keeping a thicker oxide to prevent tunneling effects Metal gate to replace polycrystalline silicon gate, to prevent poly depletion at the poly-oxide interfaceTensile and compressive stress to enhance channel mobility


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HOT M1 data

~35 % higher pFET Idsat

Developed substrate and processes of high mobility surface orientation for both nFETs & pFETs

10S Beacon testsite

Transport on (110) Surface

Courtesy, IBM


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Outline



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Classical solution:

non linear differential equation.

Electrostatics Solution

⎪⎩

⎪⎨

⎧

=

=−

−

KTq

i

KTq

iF

F

enp

enn)(

)(

ϕϕ

ϕϕ

)())(( Nnpq +−=∇−∇ ϕε

QM solution:

ψ is the solution of the Schrödinger problem.

)())(( Nnpq +−=∇−∇ ϕε[ ])(ϕψnfn =

A coupled Schrödinger-Poisson solution must be worked out.

[ ])(ϕψpfp =


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Electrostatic Solution

PotentialCharge density


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FinFET – Electron Density

QM solution

Classical solution


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Electron concentration in the tri-gate FinFET (hp90)

VG=1 VClassical solution Quantum solution

40 nm

20 nm0.1

-0.3

0.25

-0.21

NA=6x1018 cm-3


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Electron concentration in the tri-gate FinFET (hp45)

VG=1 V

Classical solution Quantum solution

10 nm

5 nm

10 nm

5 nm


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R=10nm

R=5nm

R=2.5nm

SiO2

Si

CNW-FET – Electron Density


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Current Transport in DG and CNW-FETs

Cylindrical nanowire FETDouble-gate FET

dSi = tSi

The DG-FET represents the best trade off between performance and manufacturability among the different multi-gate proposed structures.

The CNW-FET is found to be one of the 1D silicon structures with the greater potential impact on scaled nanoelectronics.


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Simulation Approach: Quantum DD

Error check

Solve the 2D coupled Schrödinger-Poisson problem

n, ϕ

Schrödinger

2D Poisson

ndn/dϕϕ

ϕn0

Extract the quantum potential from the Schrödinger-Poisson solution

ϕ, ΛSolve the 2D drift-diffusion equation to determine the quasi-Fermi potential

2D Drift-diffusion

ϕn


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Simulation approach: full-quantum transport

Error check

Solve the 2D Poisson equation 2D Poisson equation

ϕ

ϕ0

Solve the 1D Schrödinger eq. normal to the interface for each node along the channel

1D Schrödinger (closed boundary)

En (z), ψn (x;z)

The problem is solved by decoupling the Schrödinger equation along the transverse and longitudinal coordinate:

Solve the 1D Schrödinger equation with open boundary conditions

1D Schrödinger (QTBM)

χ (z)

n, dn/dϕ

Charge calculationCalculate the charge density


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Comparison of device performance


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Scaling rules

2.595.518.411.8tSi (nm)0.70.80.91.0VDD (V)

108

0.59

2016HP22

108

0.55

2020HP14

107

0.613

2013HP32

0.9EOT (nm)18Lg (nm)

145

2010HP45

Ioff (nA/um)

Year

The electrical oxide thickness is expected to be scaled down to 0.5 nm for HP22 and HP14:

gate leakage current


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High-κ Dielectrics

tHfO2= εHfO2 / εSiO2 EOT ≈ 6 EOT

High-permittivity dielectrics are thoroughly being investigated as an alternative to the conventional silicon dioxide.

Hafnium oxide is one of the most promising candidates.

A fundamental drawback of high-κ dielectrics is mobility degradation.


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Mobility model


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Mobility model for SiO2 and HfO2

Quantum

HfO2 SiO2


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Device performance: DIBL and SS


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Capacitive contributionBoth the vertical electric field in the channel and the fringing field in the oxide play a role in determining the device performance.

The lateral capacitance is expected to be given by:

If HfO2 is used at a fixed EOT:

with

δ is the average length of the electric field lines originating from drain and ending onto the channel charge.


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Charge distribution and potential profiles: DG HP45 HfO2SiO2

VGS=VDS=VDD VGS=VDS=VDD


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Surface potential within the channel: DG HP45 VGS=VDS=VDD


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QDD

quantum bal.

QDD

quantum bal.

ON current vs. gate length


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Outline



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Conclusions

Microelectronics has evolved to become Nanoelectronics

Moore’s law has been followed for nearly 4 decades mainly by device miniaturization

Conventional scaling now provides diminishing returns

New materials and new device architectures are necessary in order to comply with technology roadblocks

Strong mobility improvements are possible by using strained channel materials, with encouraging effects on the on-current

Device simulation requires a deeper understanding of the underlying device physics