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Introduction toCMOS VLSI
Design
Lecture 21: Scaling and Economics
David Harris
Harvey Mudd CollegeSpring 2004
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21: Scaling and Economics Slide 2CMOS VLSI Design
OutlineScaling– Transistors– Interconnect– Future Challenges
VLSI Economics
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21: Scaling and Economics Slide 3CMOS VLSI Design
Moore’s LawIn 1965, Gordon Moore predicted the exponential growth of the number of transistors on an ICTransistor count doubledevery year since inventionPredicted > 65,000transistors by 1975!Growth limited by power
[Moore65]
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21: Scaling and Economics Slide 4CMOS VLSI Design
More MooreTransistor counts have doubled every 26 months for the past three decades.
Year
Transistors
40048008
8080
8086
80286Intel386
Intel486Pentium
Pentium ProPentium II
Pentium IIIPentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
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21: Scaling and Economics Slide 5CMOS VLSI Design
Speed ImprovementClock frequencies have also increased exponentially– A corollary of Moore’s Law
Year
1
10
100
1,000
10,000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium Pro/II/III
Pentium 4
Clock S
peed (MH
z)
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21: Scaling and Economics Slide 6CMOS VLSI Design
Why?Why more transistors per IC?
Why faster computers?
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21: Scaling and Economics Slide 7CMOS VLSI Design
Why?Why more transistors per IC?– Smaller transistors– Larger dice
Why faster computers?
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21: Scaling and Economics Slide 8CMOS VLSI Design
Why?Why more transistors per IC?– Smaller transistors– Larger dice
Why faster computers?– Smaller, faster transistors– Better microarchitecture (more IPC)– Fewer gate delays per cycle
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21: Scaling and Economics Slide 9CMOS VLSI Design
ScalingThe only constant in VLSI is constant changeFeature size shrinks by 30% every 2-3 years– Transistors become cheaper– Transistors become faster– Wires do not improve
(and may get worse)Scale factor S– Typically – Technology nodes
Year
0.1
1
10
1965 1970 1975 1980 1985 1990 1995 2000 2005
Feat
ure
Siz
e (μ
m)
10
6
3
1.51
0.80.6
0.350.25
0.180.13
0.09
2S =
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21: Scaling and Economics Slide 10CMOS VLSI Design
Scaling AssumptionsWhat changes between technology nodes?Constant Field Scaling– All dimensions (x, y, z => W, L, tox)– Voltage (VDD)– Doping levels
Lateral Scaling– Only gate length L – Often done as a quick gate shrink (S = 1.05)
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21: Scaling and Economics Slide 11CMOS VLSI Design
Device Scaling
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Device Scaling
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Device Scaling
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21: Scaling and Economics Slide 14CMOS VLSI Design
Device Scaling
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21: Scaling and Economics Slide 15CMOS VLSI Design
Device Scaling
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21: Scaling and Economics Slide 16CMOS VLSI Design
Device Scaling
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Device Scaling
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Device Scaling
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Device Scaling
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Device Scaling
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Device Scaling
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Device Scaling
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ObservationsGate capacitance per micron is nearly independent of processBut ON resistance * micron improves with process
Gates get faster with scaling (good)Dynamic power goes down with scaling (good)Current density goes up with scaling (bad)
Velocity saturation makes lateral scaling unsustainable
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21: Scaling and Economics Slide 24CMOS VLSI Design
ExampleGate capacitance is typically about 2 fF/μmThe FO4 inverter delay in the TT corner for a process of feature size f (in nm) is about 0.5f psEstimate the ON resistance of a unit (4/2 λ) transistor.
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21: Scaling and Economics Slide 25CMOS VLSI Design
SolutionGate capacitance is typically about 2 fF/μmThe FO4 inverter delay in the TT corner for a process of feature size f (in nm) is about 0.5f psEstimate the ON resistance of a unit (4/2 λ) transistor.
FO4 = 5 τ = 15 RCRC = (0.5f) / 15 = (f/30) ps/nmIf W = 2f, R = 8.33 kΩ– Unit resistance is roughly independent of f
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Scaling AssumptionsWire thickness– Hold constant vs. reduce in thickness
Wire length– Local / scaled interconnect– Global interconnect
• Die size scaled by Dc ≈ 1.1
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Interconnect Scaling
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Interconnect Scaling
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Interconnect Scaling
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Interconnect Scaling
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Interconnect Scaling
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Interconnect Scaling
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Interconnect Scaling
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Interconnect Scaling
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Interconnect Scaling
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21: Scaling and Economics Slide 36CMOS VLSI Design
Interconnect Delay
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Interconnect Delay
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Interconnect Delay
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Interconnect Delay
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Interconnect Delay
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Interconnect Delay
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Interconnect Delay
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ObservationsCapacitance per micron is remaining constant– About 0.2 fF/μm– Roughly 1/10 of gate capacitance
Local wires are getting faster– Not quite tracking transistor improvement– But not a major problem
Global wires are getting slower– No longer possible to cross chip in one cycle
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21: Scaling and Economics Slide 44CMOS VLSI Design
ITRSSemiconductor Industry Association forecast– Intl. Technology Roadmap for Semiconductors
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Scaling ImplicationsImproved PerformanceImproved CostInterconnect WoesPower WoesProductivity ChallengesPhysical Limits
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Cost ImprovementIn 2003, $0.01 bought you 100,000 transistors– Moore’s Law is still going strong
[Moore03]
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21: Scaling and Economics Slide 47CMOS VLSI Design
Interconnect WoesSIA made a gloomy forecast in 1997– Delay would reach minimum at 250 – 180 nm,
then get worse because of wiresBut…
[SIA97]
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21: Scaling and Economics Slide 48CMOS VLSI Design
Interconnect WoesSIA made a gloomy forecast in 1997– Delay would reach minimum at 250 – 180 nm,
then get worse because of wiresBut…– Misleading scale– Global wires
100 kgate blocks ok
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21: Scaling and Economics Slide 49CMOS VLSI Design
Reachable RadiusWe can’t send a signal across a large fast chip in one cycle anymoreBut the microarchitect can plan around this– Just as off-chip memory latencies were tolerated
Chip size
Scaling ofreachable radius
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Dynamic PowerIntel VP Patrick Gelsinger (ISSCC 2001)– If scaling continues at present pace, by 2005,
high speed processors would have power density of nuclear reactor, by 2010, a rocket nozzle, and by 2015, surface of sun.
– “Business as usual will not work in the future.”Intel stock dropped 8%on the next dayBut attention to power isincreasing
[Moore03]
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Static PowerVDD decreases– Save dynamic power– Protect thin gate oxides and short channels– No point in high value because of velocity sat.
Vt must decrease to maintain device performanceBut this causes exponential increase in OFF leakageMajor future challenge
Static
Dynamic
[Moore03]
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ProductivityTransistor count is increasing faster than designer productivity (gates / week)– Bigger design teams
• Up to 500 for a high-end microprocessor– More expensive design cost– Pressure to raise productivity
• Rely on synthesis, IP blocks– Need for good engineering managers
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Physical LimitsWill Moore’s Law run out of steam?– Can’t build transistors smaller than an atom…
Many reasons have been predicted for end of scaling– Dynamic power– Subthreshold leakage, tunneling– Short channel effects– Fabrication costs– Electromigration– Interconnect delay
Rumors of demise have been exaggerated
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VLSI EconomicsSelling price Stotal
– Stotal = Ctotal / (1-m)m = profit marginCtotal = total cost– Nonrecurring engineering cost (NRE)– Recurring cost– Fixed cost
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NREEngineering cost– Depends on size of design team– Include benefits, training, computers– CAD tools:
• Digital front end: $10K• Analog front end: $100K• Digital back end: $1M
Prototype manufacturing– Mask costs: $500k – 1M in 130 nm process– Test fixture and package tooling
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Recurring CostsFabrication– Wafer cost / (Dice per wafer * Yield)– Wafer cost: $500 - $3000– Dice per wafer:
– Yield: Y = e-AD
• For small A, Y ≈ 1, cost proportional to area• For large A, Y → 0, cost increases exponentially
PackagingTest
2 22
r rNA A
π⎡ ⎤
= −⎢ ⎥⎣ ⎦
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Fixed CostsData sheets and application notesMarketing and advertisingYield analysis
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ExampleYou want to start a company to build a wireless communications chip. How much venture capital must you raise?
Because you are smarter than everyone else, you can get away with a small team in just two years:– Seven digital designers– Three analog designers– Five support personnel
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SolutionDigital designers:– salary– overhead– computer– CAD tools– Total:
Analog designers– salary– overhead– computer– CAD tools– Total:
Support staff– salary– overhead– computer– Total:
Fabrication– Back-end tools: – Masks: – Total:
Summary
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SolutionDigital designers:– $70k salary– $30k overhead– $10k computer– $10k CAD tools– Total: $120k * 7 = $840k
Analog designers– $100k salary– $30k overhead– $10k computer– $100k CAD tools– Total: $240k * 3 = $720k
Support staff– $45k salary– $20k overhead– $5k computer– Total: $70k * 5 = $350k
Fabrication– Back-end tools: $1M– Masks: $1M– Total: $2M / year
Summary– 2 years @ $3.91M / year– $8M design & prototype
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Cost BreakdownNew chip design is fairly capital-intensiveMaybe you can do it for less?
salary
overhead
computer
entry tools
backend tools
fab
25%
25%
26%
9% 4%11%
